Content
CA - Books and Book Chapters
2023
- Machine Learning Support for Logic Diagnosis and Defect Classification. Hans-Joachim Wunderlich. In Machine Learning Support for Fault Diagnosis of System-on-Chip, Patrick Girard; Shawn Blanton and Li-C. Wang (eds.). Springer International Publishing, Cham, 2023, pp. 99–133. DOI: https://doi.org/10.1007/978-3-031-19639-3_4
2022
- Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (4. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2022, pp. 266–289. DOI: https://doi.org/10.3139/9783446470453.009
2021
- Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. In Dependable Embedded Systems, Jörg Henkel and Nikil Dutt (eds.). Springer International Publishing, Cham, 2021, pp. 277–302. DOI: https://doi.org/10.1007/978-3-030-52017-5_12
2019
- Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395–416. DOI: https://doi.org/10.1049/PBPC022E_ch16
2014
- Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262–285.
2010
- Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187–215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
- Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133–155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
- Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117–146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
- Models in Hardware Testing. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.2010. DOI: https://doi.org/10.1007/978-90-481-3282-9
2009
- Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen. Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (Eds.). Springer-Verlag Heidelberg.2009. DOI: https://doi.org/10.1007/978-3-540-85091-5
- Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen. Hans-Joachim Wunderlich; Melanie Elm and Michael A. Kochte. In Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertungin frühen Entwicklungsphasen, Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (eds.). Springer-Verlag Heidelberg, 2009, pp. 391–464. DOI: https://doi.org/10.1007/978-3-540-85091-5_8
2007
- Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (2. Auflage), Christian Siemers and Axel Sikora (eds.). Fachbuchverlag Leipzig im Carl Hanser Verlag, 2007, pp. 267–290.
1998
- Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In On-Line Testing for VLSI, Michael Nicolaidis; Yervant Zorian and Dhiraj K. Pradhan (eds.). Kluwer Academic Publishers, 1998.
- Test and Testable Design. Hans-Joachim Wunderlich. In Architecture Design and Validation Methods, Egon Börger (ed.). Springer-Verlag Heidelberg, 1998, pp. 141–190.
1991
- Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.1991.
- Synthese vollständig testbarer Schaltungen. Sybille Hellebrand (Ed.). VDI Verlag Düsseldorf.1991.
1987
- Probabilistische Verfahren für den Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.1987.
CA - Journals and Conferences
2024
- Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the proceedings of the IEEE InternationalTest Conference (ITC′24), Sandiego, California, USA, 2024.
- RAPPER: Robust and APProximate ERror Tolerating Communication. Somayeh Sadeghi-Kohan; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology System(DFTS´24), Oxfordshire, UK, 2024.
- Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the Proceedings of the IEEE European Test Symposium (ETS´24), The Hague, Netherland, 2024.
- Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. Sybille Hellebrand; Somayeh Sadeghi-Kohan and Hans-Joachim Wunderlich. In To appear in the International Symposium of EDA 2024 (ISEDA´24), Xi’an, China, 2024.
- Robust Tests of Small Delay Faults under PVT-Variations. Hans-Joachim Wunderlich; Hanieh Jafarzadeh and Sybille Hellebrand. In To appear in the International Symposium of EDA 2024 (ISEDA´24), Xi’an, China, 2024.
- Vmin Testing under Variations: Defect vs. Fault Coverage. Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the Proceedings of the IEEE Latin-American Test Symposium (LATS′24), Maceio, Brazil, 2024.
2023
- Optimizing the Streaming of Sensor Data with Approximate Communication. Somayeh Sadeghi-Kohan; Jan Dennis Reimer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the IEEE Asian Test Symposium (ATS′23), Beijing, China, 2023.
- Robust Pattern Generation for Small Delay Faults under Process Variations. Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Zahra Paria Najafi-Haghi; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′23), Disneyland, Anaheim, USA, 2023.
- Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization. Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra . Kourfali and Hans-Joachim Wunderlich. In IEEE 29st International On-Line Testing Symposium (IOLTS`23), Chania (Crete), Greece, 2023, pp. 1–6.
- Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm. Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali and Hans-Joachim Wunderlich. In International Conference on Dependable Systems and Networks(DSN′23), Porto, Portugal, 2023.
- Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. Somayeh Sadeghi-Kohan; Sybille Hellebrand and Hans-Joachim Wunderlich. In International Conference on Dependable Systems and Networks(DSN′23), Porto, Portugal, 2023.
- Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. Payam Habiby; Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich; Sebastian Huhn and Rolf Drechsler. In Proceedings of the 28th IEEE European Test Symposium 2023 (ETS’ 23), Venice, Italy, 2023, pp. 6.
- Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. Zahra Paria Najafi-Haghi; Florian Klemme; Hanieh Jafarzadeh; Hussam Amrouch and Hans-Joachim Wunderlich. In Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE′23), Antwerp, Belgium, 2023.
- Test Aspects of System Health State Monitoring. Hans-Joachim Wunderlich; Hanieh Jafarzadeh; Alexandra Kourfali; Natalia Lylina and Zahra Paria Najafi-Haghi. In IEEE 24nd Latin American Test Symposium (LATS`23), Veracruz, Mexico, 2023, pp. 1–2.
- A Complete Design-for-Test Scheme for Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (January 2023), pp. 1–19. DOI: https://doi.org/10.1007/s10836-022-06038-3
- Identifying Resistive Open Defects in Embedded Cells under Variations. Zahra Paria Najafi-Haghi and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (2023), pp. 1–27. DOI: https://doi.org/10.1007/s10836-023-06044-z
- Workload-Aware Periodic Interconnect BIST. Somayeh Sadeghi-Kohan; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Design & Test (2023), pp. 1. DOI: https://doi.org/10.1109/MDAT.2023.3298849
2022
- Online Periodic Test of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE Asian Test Symposium, Taichung, Taiwan, 2022, pp. 1–6. DOI: https://doi.org/10.1109/ATS56056.2022.00026
- Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning. Yiwen Liao; Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich and Bin Yang. In In Proceedings of the IEEE International Test Conference (ITC′22), Anaheim, CA, USA, 2022. DOI: https://doi.org/10.1109/ITC50671.2022.00026
- On Extracting Reliability Information from Speed Binning. Zahra Paria Najafi-Haghi; Florian Klemme; Hussam Amrouch and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE European Test Symposium (ETS’22), Barcelona, Spain, 2022. DOI: https://doi.org/10.1109/ETS54262.2022.9810443
- Robust Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′22), Antwerp, Belgium, 2022, pp. 1–4. DOI: https://doi.org/10.23919/DATE54114.2022.9774770
- Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
- Stress-Aware Periodic Test of Interconnects. Sadeghi-Kohan Somayeh; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (January 2022). DOI: https://doi.org/10.1007/s10836-021-05979-5
- SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2022), pp. 1–14. DOI: https://doi.org/10.1109/TCAD.2022.3158250
2021
- Resistive Open Defect Classification of Embedded Cells under Variations. Zahra Paria Najafi-Haghi and Hans-Joachim Wunderlich. In Proceedings of the IEEE Latin-American Test Symposium (LATS′21), Virtual, 2021, pp. 1–6. DOI: https://doi.org/10.1109/LATS53581.2021.9651857
- Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′21), Virtual, 2021, pp. 1–10. DOI: https://doi.org/10.1109/ITC50571.2021.00009
- Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. Chih-Hao Wang; Natalia Lylina; Ahmed Atteya; Tong-Yu Hsieh and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS′21), Virtual, 2021, pp. 1–7. DOI: https://doi.org/10.1109/IOLTS52814.2021.9486710
- A Hybrid Protection Scheme for Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya and Hans-Joachim Wunderlich. In Proceedings of the IEEE VLSI Test Symposium (VTS′21), Virtual, 2021, pp. 1–7. DOI: https://doi.org/10.1109/VTS50974.2021.9441029
2020
- Logic Fault Diagnosis of Hidden Delay Defects. Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC′20), Washington DC, USA, 2020. DOI: https://doi.org/10.1109/ITC44778.2020.9325234
- Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′20), Washington DC, USA, 2020. DOI: https://doi.org/10.1109/ITC44778.2020.9325227
- Variation-Aware Defect Characterization at Cell Level. Zahra Najafi Haghi; Marzieh Hashemipour Nazari and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE European Test Symposium (ETS′20), Tallinn, Estonia, 2020, pp. 1–6.
- Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE VLSI TestSymposium (VTS′20), San Diego, US, 2020, pp. 1–6.
- GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEEConference on Design, Automation Test in Europe (DATE′20), Grenoble, France, 2020, pp. 1–6. DOI: https://doi.org/10.23919/DATE48585.2020.9116256
- Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction. Chang Liu; Eric Schneider and Hans-Joachim. Wunderlich. In Proceedings of the ACM/IEEEConference on Design, Automation Test in Europe (DATE′20), Grenoble, France, 2020, pp. 1–6. DOI: https://doi.org/10.23919/DATE48585.2020.9116284
- Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE′20), Grenoble, France, 2020, pp. 1–6. DOI: https://doi.org/10.23919/DATE48585.2020.9116525
Former CA - Journals and Conferences
2019
- Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC′19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000143
- Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC′19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000114
- Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems (TCAD) 38, (October 2019), pp. 1956–1968. DOI: https://doi.org/10.1109/TCAD.2018.2864255
- On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′19), Florence, Italy, 2019, pp. 1016–1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
- Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (January 2019), pp. 78–91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
- SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, (January 2019), pp. 122–135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
2018
- Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS′18), Hefei, Anhui, China, 2018, pp. 92–97. DOI: https://doi.org/10.1109/ATS.2018.00028
- Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 27th IEEE Asian Test Symposium (ATS′18), Hefei, Anhui, China, 2018, pp. 149–154. DOI: https://doi.org/10.1109/ATS.2018.00037
- Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, (October 2018), pp. 7–18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
- Device aging: A reliability and security concern. Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit Singh; Hans-Joachim Wunderlich and Naghmeh Karimi. In Proceedings of the 23rd IEEE European Test Symposium (ETS′18), Bremen, Germany, 2018, pp. 1–10. DOI: https://doi.org/10.1109/ETS.2018.8400702
- Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS′18), Bremen, Germany, 2018, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2018.8400685
- Detecting and Resolving Security Violations in Reconfigurable Scan Networks. Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS′18), Platja d’Aro, Spain, 2018, pp. 91–96. DOI: https://doi.org/10.1109/IOLTS.2018.8474188
- Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, (June 2018), pp. 5–6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
- Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, (March 2018), pp. 1. DOI: https://doi.org/10.1109/LES.2018.2789942
- Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC′18), Jeju Island, Korea, 2018, pp. 470–475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
2017
- Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS′17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
- Trustworthy Reconfigurable Access to On-Chip Infrastructure. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 1st International Test Conference in Asia (ITC-Asia′17), Taipei, Taiwan, 2017, pp. 119–124. DOI: https://doi.org/10.1109/ITC-ASIA.2017.8097125
- Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS′17), Thessaloniki, Greece, 2017, pp. 237–239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
- Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, (June 2017), pp. 957–970. DOI: https://doi.org/10.1109/TC.2016.2616405
- Probabilistic Sensitization Analysis for Variation-Aware Path Delay Fault Test Evaluation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS′17), Limassol, Cyprus, 2017, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2017.7968226
- Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS′17), Limassol, Cyprus, 2017, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2017.7968247
- Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, (May 2017), pp. 848–861. DOI: https://doi.org/10.1109/TC.2016.2628058
- GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 36, (May 2017), pp. 829–841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
- Special Session on Early Life Failures. Jyotirmoy Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 35th VLSI Test Symposium (VTS′17), Caesars Palace, Las Vegas, Nevada, USA, 2017. DOI: https://doi.org/10.1109/VTS.2017.7928933
- Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS′17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1–6. DOI: https://doi.org/10.1109/VTS.2017.7928921
- Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC′17), Fort Worth, Texas, USA, 2017, pp. 1–8. DOI: https://doi.org/10.1109/TEST.2017.8242055
2016
- Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 215–220. DOI: https://doi.org/10.1109/ATS.2016.56
- Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 19–24. DOI: https://doi.org/10.1109/ATS.2016.49
- Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 246–251. DOI: https://doi.org/10.1109/ATS.2016.18
- Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 113–118. DOI: https://doi.org/10.1109/ATS.2016.35
- High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 150–155. DOI: https://doi.org/10.1109/ATS.2016.9
- A Neural-Network-Based Fault Classifier. Laura Rodríguez Gómez and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS′16), Hiroshima, Japan, 2016, pp. 144–149. DOI: https://doi.org/10.1109/ATS.2016.46
- Applying Efficient Fault Tolerance to Enable the Preconditioned Conjugate Gradient Solver on Approximate Computing Hardware. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT′16), University of Connecticut, USA, 2016, pp. 21–26. DOI: https://doi.org/10.1109/DFT.2016.7684063
- Pushing the Limits: How Fault Tolerance Extends the Scope of Approximate Computing. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS′16), Sant Feliu de Guixols, Catalunya, Spain, 2016, pp. 133–136. DOI: https://doi.org/10.1109/IOLTS.2016.7604686
- Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS′16), Amsterdam, The Netherlands, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
- SHIVA: Sichere Hardware in der Informationsverarbeitung. Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 2016.
- Fault Tolerance of Approximate Compute Algorithms. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 34th VLSI Test Symposium (VTS′16), Caesars Palace, Las Vegas, Nevada, USA, 2016. DOI: https://doi.org/10.1109/VTS.2016.7477307
- Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS′16), Foz do Iguaçu, Brazil, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
- Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC′16), Macao SAR, China, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
- Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN′16), Toulouse, France, 2016, pp. 251–262. DOI: https://doi.org/10.1109/DSN.2016.31
2015
- Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, (December 2015), pp. 2025–2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
- Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. Michael Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omana; Cecilia Metra and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS′15), Mumbai, India, 2015, pp. 157–162. DOI: https://doi.org/10.1109/ATS.2015.34
- Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS′15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
- Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS′15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
- STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD′15), Austin, Texas, USA, 2015, pp. 38–45.
- Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT′15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
- Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS′15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
- Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS′15), Elia, Halkidiki, Greece, 2015, pp. 176–181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
- Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS′15), Elia, Halkidiki, Greece, 2015, pp. 95–100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
- Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, (June 2015), pp. 149–158. DOI: https://doi.org/10.1515/itit-2014-1082
- Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, (June 2015), pp. 937–946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
- High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, (June 2015), pp. 37:1––37:21. DOI: https://doi.org/10.1145/2714564
- On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE′15), Grenoble, France, 2015, pp. 589–592. DOI: https://doi.org/10.7873/DATE.2015.0940
- GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE′15), Grenoble, France, 2015, pp. 1174–1179. DOI: https://doi.org/10.7873/DATE.2015.0077
- Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, (February 2015), pp. 30:1––30:27. DOI: https://doi.org/10.1145/2699863
2014
- Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, (December 2014), pp. 711–723. DOI: https://doi.org/10.1007/s10836-014-5484-2
- On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS′14), Hangzhou, China, 2014, pp. 87–92. DOI: https://doi.org/10.1109/ATS.2014.27
- High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS′14), Hangzhou, China, 2014, pp. 298–305. DOI: https://doi.org/10.1109/ATS.2014.62
- Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD′14), San Jose, California, USA, 2014, pp. 17–23. DOI: https://doi.org/10.1109/ICCAD.2014.7001324
- Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine(BIBM′14), Belfast, United Kingdom, 2014, pp. 424–431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
- Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the IEEE International Test Conference (ITC′14), Seattle, Washington, USA, 2014, pp. 1–10. DOI: https://doi.org/10.1109/TEST.2014.7035350
- FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′14), Seattle, Washington, USA, 2014, pp. 1–8. DOI: https://doi.org/10.1109/TEST.2014.7035360
- Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, (September 2014), pp. 527–540. DOI: https://doi.org/10.1007/s10836-014-5477-1
- Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, (August 2014), pp. 37:1––37:21. DOI: https://doi.org/10.1145/2647955
- SAT-Based ATPG beyond Stuck-at Fault Testing. Sybille Hellebrand and Hans-Joachim Wunderlich. it - Information Technology 56, (July 2014), pp. 165–172. DOI: https://doi.org/10.1515/itit-2013-1043
- Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS′14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13–18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
- A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN′14), Atlanta, Georgia, USA, 2014, pp. 443–454. DOI: https://doi.org/10.1109/DSN.2014.48
- A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, (June 2014), pp. 401–413. DOI: https://doi.org/10.1007/s10836-014-5459-3
- GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC′14), San Francisco, California, USA, 2014, pp. 1–6. DOI: https://doi.org/10.1145/2593069.2593146
- Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Ulrich Abelein and Piet Engelke. In Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC′14), San Francisco, California, USA, 2014, pp. 1–9. DOI: https://doi.org/10.1145/2593069.2602971
- Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, (June 2014), pp. 28:1––28:17. DOI: https://doi.org/10.1145/2611760
- Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS′14), Paderborn, Germany, 2014, pp. 81–86. DOI: https://doi.org/10.1109/ETS.2014.6847805
- Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS′14), Paderborn, Germany, 2014, pp. 27–30. DOI: https://doi.org/10.1109/ETS.2014.6847796
- Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS′14), Paderborn, Germany, 2014, pp. 87–92. DOI: https://doi.org/10.1109/ETS.2014.6847806
- Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS′14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
- Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE′14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
- Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures. Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE′14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.373
- Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV′14), Böblingen, Germany, 2014, pp. 137–146.
- Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, (2014), pp. 1066–1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
2013
- Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS′13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
- Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS′13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
- Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT′13), New York City, New York, USA, 2013, pp. 137–142. DOI: https://doi.org/10.1109/DFT.2013.6653596
- SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT′13), New York City, NY, USA, 2013, pp. 38–44. DOI: https://doi.org/10.1109/DFT.2013.6653580
- Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC′13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
- Test Strategies for Reliable Runtime Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. IEEE Transactions on Computers 62, (August 2013), pp. 1494–1507. DOI: https://doi.org/10.1109/TC.2013.53
- Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS′13), Crete, Greece, 2013, pp. 240–243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
- Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS′13), Avignon, France, 2013, pp. 39–45. DOI: https://doi.org/10.1109/ETS.2013.6569354
- Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′13), Grenoble, France, 2013, pp. 276–281. DOI: https://doi.org/10.7873/DATE.2013.069
- Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′13), Grenoble, France, 2013, pp. 436–441. DOI: https://doi.org/10.7873/DATE.2013.098
2012
- Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, (December 2012), pp. 1908–1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
- Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS′12), Niigata, Japan, 2012, pp. 214–219. DOI: https://doi.org/10.1109/ATS.2012.32
- Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS′12), Niigata, Japan, 2012, pp. 344–349. DOI: https://doi.org/10.1109/ATS.2012.14
- Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS′12), Niigata, Japan, 2012, pp. 155–160. DOI: https://doi.org/10.1109/ATS.2012.23
- Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′12), Anaheim, California, USA, 2012, pp. 1–9. DOI: https://doi.org/10.1109/TEST.2012.6401555
- Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM′12), Philadelphia, Pennsylvania, USA, 2012, pp. 1–6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
- Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, (October 2012), pp. 831–841. DOI: https://doi.org/10.1007/s10836-012-5329-9
- Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS′12), Sitges, Spain, 2012, pp. 37–42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
- OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS′12), Erlangen, Germany, 2012, pp. 38–45. DOI: https://doi.org/10.1109/AHS.2012.6268667
- A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS′12), Hyatt Maui, Hawaii, USA, 2012, pp. 50–55. DOI: https://doi.org/10.1109/VTS.2012.6231079
- Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW′12), Quito, Ecuador, 2012, pp. 1–4. DOI: https://doi.org/10.1109/LATW.2012.6261229
- Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD′12), Montreal, Canada, 2012, pp. 207–212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
- Efficient System-Level Aging Prediction. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS′12), Annecy, France, 2012, pp. 164–169. DOI: https://doi.org/10.1109/ETS.2012.6233028
- Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. Alejandro Cook; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS′12), Annecy, France, 2012, pp. 146–151. DOI: https://doi.org/10.1109/ETS.2012.6233025
- Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS′12), Annecy, France, 2012, pp. 98–103. DOI: https://doi.org/10.1109/ETS.2012.6233017
2011
- Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS′11), New Delhi, India, 2011, pp. 213–218. DOI: https://doi.org/10.1109/ATS.2011.60
- Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS′11), New Delhi, India, 2011, pp. 285–290. DOI: https://doi.org/10.1109/ATS.2011.55
- A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS′11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
- Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS′11), New Delhi, India, 2011, pp. 383–388. DOI: https://doi.org/10.1109/ATS.2011.52
- Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS′11), Taipei, Taiwan, 2011, pp. 69–78. DOI: https://doi.org/10.1145/2039370.2039384
- Robuster Selbsttest mit Diagnose. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′11), Hamburg-Harburg, Germany, 2011, pp. 48–53.
- Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′11), Hamburg-Harburg, Germany, 2011, pp. 76–83.
- Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′11), Hamburg-Harburg, Germany, 2011, pp. 43–47.
- P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC′11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
- A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing. Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara and Laung-Terng Wang. In Proceedings of the IEEE International Test Conference (ITC′11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139162
- Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults. Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich and Christian G. Zoellin. SCIENCE CHINA Information Sciences 54, (September 2011), pp. 1784–1796. DOI: https://doi.org/10.1007/s11432-011-4366-9
- Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, (September 2011), pp. 1813–1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
- SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures. Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED′11), Fukuoka, Japan, 2011, pp. 33–38. DOI: https://doi.org/10.1109/ISLPED.2011.5993600
- Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS′11), Athens, Greece, 2011, pp. 169–174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
- Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS′11), Athens, Greece, 2011, pp. 278–283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
- Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS′11), Trondheim, Norway, 2011, pp. 111–116. DOI: https://doi.org/10.1109/ETS.2011.25
- Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS′11), Trondheim, Norway, 2011, pp. 219–225. DOI: https://doi.org/10.1109/ETS.2011.51
- Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS′11), Trondheim, Norway, 2011, pp. 183–188. DOI: https://doi.org/10.1109/ETS.2011.33
- Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing. Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard and Mohammad Tehranipoor. In Proceedings of the 29th IEEE VLSI Test Symposium (VTS′11), Dana Point, California, USA, 2011, pp. 166–171. DOI: https://doi.org/10.1109/VTS.2011.5783778
- SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE′11), Grenoble, France, 2011, pp. 1303–1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
2010
- On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS′10), Shanghai, China, 2010, pp. 39–44. DOI: https://doi.org/10.1109/ATS.2010.16
- Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS′10), Shanghai, China, 2010, pp. 87–93. DOI: https://doi.org/10.1109/ATS.2010.24
- Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS′10), Shanghai, China, 2010, pp. 3–8. DOI: https://doi.org/10.1109/ATS.2010.10
- Efficient Concurrent Self-Test with Partially Specified Patterns. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 26, (October 2010), pp. 581–594. DOI: https://doi.org/10.1007/s10836-010-5167-6
- Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′10), Wildbad Kreuth, Germany, 2010, pp. 25–32.
- Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen; Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, (August 2010), pp. 209–215. DOI: https://doi.org/10.1524/itit.2010.0593
- Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC′10), Anaheim, California, USA, 2010, pp. 380–385. DOI: https://doi.org/10.1145/1837274.1837369
- Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS′10), Praha, Czech Republic, 2010, pp. 253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
- Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS′10), Santa Cruz, California, USA, 2010, pp. 93–98. DOI: https://doi.org/10.1109/VTS.2010.5469607
- BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE′10), Dresden, Germany, 2010, pp. 1243–1248.
- System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC′10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
- Parity Prediction Synthesis for Nano-Electronic Gate Designs. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In IEEE International Test Conference (ITC′10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699312
- Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W′10), Chicago, Illinois, USA, 2010, pp. 95–100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
2009
- XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′09), Stuttgart, Germany, 2009, pp. 21–28.
- Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, (August 2009), pp. 259–268. DOI: https://doi.org/10.1007/s10836-009-5109-3
- Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS′09), Sevilla, Spain, 2009, pp. 53–58. DOI: https://doi.org/10.1109/ETS.2009.26
- Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS′09), Sevilla, Spain, 2009, pp. 155–160. DOI: https://doi.org/10.1109/ETS.2009.22
- Restrict Encoding for Mixed-Mode BIST. Abdul-Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke and Andreas Glowatz. In Proceedings of the 27th IEEE VLSI Test Symposium (VTS′09), Santa Cruz, California, USA, 2009, pp. 179–184. DOI: https://doi.org/10.1109/VTS.2009.43
- Test Exploration and Validation Using Transaction Level Models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′09), Nice, France, 2009, pp. 1250–1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
- A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE′09), Nice, France, 2009, pp. 1355–1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
2008
- Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS′08), Rhodes, Greece, 2008, pp. 59–64. DOI: https://doi.org/10.1109/IOLTS.2008.31
- Scan Chain Clustering for Test Power Reduction. Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra and Nicolas Maeding. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC′08), Anaheim, California, USA, 2008, pp. 828–833. DOI: https://doi.org/10.1145/1391469.1391680
- Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS′08), Lago Maggiore, Italy, 2008, pp. 185–190. DOI: https://doi.org/10.1109/ETS.2008.30
- A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer. Michael A. Kochte and Ramesh Natarajan. In Proceedings of the 2008 conference on Computing frontiers (CF′08), Ischia, Italy, 2008, pp. 97–104. DOI: https://doi.org/10.1145/1366230.1366245
- Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE′08), Munich, Germany, 2008, pp. 468–473. DOI: https://doi.org/10.1109/DATE.2008.4484725
- Test Set Stripping Limiting the Maximum Number of Specified Bits. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE International Symposium on ElectronicDesign, Test and Applications (DELTA′08), 2008, pp. 581–586. DOI: https://doi.org/10.1109/DELTA.2008.64
- Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen; On the Reliability Modeling of Hardware-Software-Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′08), Ingolstadt, Germany, 2008, pp. 83–90.
- Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung; Detection of transient faults in circuits with reduced power dissipation. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′08), Ingolstadt, Germany, 2008, pp. 107–114.
- Signature Rollback – A Technique for Testing Robust Circuits. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE VLSI Test Symposium (VTS′08), San Diego, California, USA, 2008, pp. 125–130. DOI: https://doi.org/10.1109/VTS.2008.34
2007
- Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. Informacije MIDEM 37, (December 2007), pp. 212–219.
- Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, (December 2007), pp. 235–243.
- Academic Network for Microelectronic Test Education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean Pierre Van Der Heyden. The International Journal of Engineering Education 23, (November 2007), pp. 1245–1253.
- Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Juergen Schloeffel and Laurent Souef. In Proceedings of the International Test Conference (ITC′07), Santa Clara, California, USA, 2007, pp. 1–9. DOI: https://doi.org/10.1109/TEST.2007.4437611
- A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT′07), Rome, Italy, 2007, pp. 50–58. DOI: https://doi.org/10.1109/DFT.2007.43
- Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper). Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM′07), Bled, Slovenia, 2007, pp. 3–10.
- Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM′07), Bled, Slovenia, 2007, pp. 27–36.
- Scan Test Planning for Power Reduction. Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC′07), San Diego, California, USA, 2007, pp. 521–526. DOI: https://doi.org/10.1145/1278480.1278614
- Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS′07), Freiburg, Germany, 2007, pp. 7–12. DOI: https://doi.org/10.1109/ETS.2007.9
- An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS′07), Freiburg, Germany, 2007, pp. 91–96. DOI: https://doi.org/10.1109/ETS.2007.10
- Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. IET Computers & Digital Techniques 1, (May 2007), pp. 180–186. DOI: https://doi.org/http://digital-library.theiet.org/content/journals/10.1049/iet-cdt_20060131
- Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE Workshop on Design and Diagnostics ofElectronic Circuits and Systems (DDECS′07), Krakow, Poland, 2007, pp. 185–190. DOI: https://doi.org/10.1109/DDECS.2007.4295278
- Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute. Michael E. Imhof; Christian G. Zöllin; Hans-Joachim Wunderlich; Nicolas Mäding and Jens Leenstra. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′07), Munich, Germany, 2007, pp. 69–76.
- Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE′07), Munich, Germany, 2007, pp. 139–140.
- Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen. Michael Wedel; Peter Göhner; Jochen Gäng; Bernd Bertsche; Talal Arnaout and Hans-Joachim Wunderlich. In 5. Paderborner Workshop “Entwurf mechatronischer Systeme”, Paderborn, Germany, 2007, pp. 257–272.
- Synthesis of Irregular Combinational Functions with Large Don’t Care Sets. Valentin Gherman; Hans-Joachim Wunderlich; Rio Mascarenhas; Juergen Schloeffel and Michael Garbers. In Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI′07), Stresa - Lago Maggiore, Italy, 2007, pp. 287–292. DOI: https://doi.org/10.1145/1228784.1228856
2006
- BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the International Test Conference (ITC′06), Santa Clara, California, USA, 2006, pp. 1–8. DOI: https://doi.org/10.1109/TEST.2006.297695
- Structural-based Power-aware Assignment of Don’t Cares for Peak Power Reduction during Scan Testing. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Virazel Arnaud and Hans-Joachim Wunderlich. In Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, 2006, pp. 403–408. DOI: https://doi.org/10.1109/VLSISOC.2006.313222
- DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme; DFG-Project – Test and Reliability of Nano-Electronic Systems. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. it - Information Technology 48, (October 2006), pp. 304–311. DOI: https://doi.org/10.1524/itit.2006.48.5.304
- Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS′06), Tunis, Tunisia, 2006, pp. 359–364. DOI: https://doi.org/10.1109/DTIS.2006.1708693
- Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. In Proceedings of the 11th European Test Symposium (ETS′06), Southampton, United Kingdom, 2006, pp. 123–130. DOI: https://doi.org/10.1109/ETS.2006.12
- Software-Based Self-Test of Processors under Power Constraints. Jun Zhou and Hans-Joachim Wunderlich. In Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE′06), Munich, Germany, 2006, pp. 430–436. DOI: https://doi.org/10.1109/DATE.2006.243798
- X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilian Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14, (February 2006), pp. 193–202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
- Some Common Aspects of Design Validation, Debug and Diagnosis. Talal Arnaout; Günter Bartsch and Hans-Joachim Wunderlich. In Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA′06), Kuala Lumpur, Malaysia, 2006, pp. 3–10. DOI: https://doi.org/10.1109/DELTA.2006.79
2005
- On the Reliability Evaluation of SRAM-based FPGA Designs. Oliver Héron; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL′05), Tampere, Finland, 2005, pp. 403–408. DOI: https://doi.org/10.1109/FPL.2005.1515755
- Development of an Audio Player as System-on-a-Chip using an Open Source Platform. Kiatisevi Pattara; Luis Azuara; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS′05), Kobe, Japan, 2005, pp. 2935–2938. DOI: https://doi.org/10.1109/ISCAS.2005.1465242
- From Embedded Test to Embedded Diagnosis. Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE European Test Sypmposium (ETS′05), Tallinn, Estonia, 2005, pp. 216–221. DOI: https://doi.org/10.1109/ETS.2005.26
- Implementing a Scheme for External Deterministic Self-Test. Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS′05), Palm Springs, California, USA, 2005, pp. 101–106. DOI: https://doi.org/10.1109/VTS.2005.50
- Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS′05), Sopron, Hungary, 2005, pp. 11–18.
- Frühe Zuverlässigkeitsanalyse mechatronischer Systeme; Early Reliability Analysis for Mechatronic Systems. Patrick Jäger; Bernd Bertsche; Talal Arnout and Hans-Joachim Wunderlich. In 22. VDI Tagung Technische Zuverlässigkeit (TTZ′05), Stuttgart, Germany, 2005, pp. 39–56.
2004
- X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In Proceedings of the 35th IEEE International Test Conference (ITC′04), Charlotte, New York, USA, 2004, pp. 442–451. DOI: https://doi.org/10.1109/TEST.2004.1386980
- Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke and Michael Garbers. In Proceedings of the 35th IEEE International Test Conference (ITC′04), Charlotte, New York, USA, 2004, pp. 48–56. DOI: https://doi.org/10.1109/TEST.2004.1386936
- Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke and Michael Wittke. In Proceedings of the 9th IEEE European Test Sypmposium (ETS′04), Ajaccio, Corsica, France, 2004, pp. 327–332.
- Reliability Considerations for Mechatronic Systems on the Basis of a State Model. Peter Göhner; Eduard Zimmer; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 17th International Conference on Architecture of Computing Systems (ARCS′04) - Organic and Pervasive Computing, Augsburg, Germany, 2004, pp. 106–112.
- Impact of Test Point Insertion on Silicon Area and Timing during Layout. Harald Vranken; Ferry Syafei Sapei and Hans-Joachim Wunderlich. In Proceedings of the 7th Conference on Design, Automation and Test in Europe (DATE′04), Paris, France, 2004, pp. 20810–20815. DOI: https://doi.org/10.1109/DATE.2004.1268981
2003
- Test Engineering Education in Europe: the EuNICE-Test Project. Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Anton Biasizzo; Frank Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean-Pierre Van der Heyden. In Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE′03), Anaheim, California, USA, 2003, pp. 85–86. DOI: https://doi.org/10.1109/MSE.2003.1205266
2002
- Adapting an SoC to ATE Concurrent Test Capabilities. Rainer Dorsch; Ramón Huerta Rivera; Hans-Joachim Wunderlich and Martin Fischer. In Proceedings of the 33rd International Test Conference (ITC′02), Baltimore, Maryland, USA, 2002, pp. 1169–1175. DOI: https://doi.org/10.1109/TEST.2002.1041875
- Efficient Online and Offline Testing of Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets and Vyacheslav N. Yarmolik. IEEE Transactions on Computers 51, (July 2002), pp. 801–809. DOI: https://doi.org/10.1109/TC.2002.1017700
- Combining Deterministic Logic BIST with Test Point Insertion. Harald Vranken; Florian Meister and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW′02), Korfu, Greece, 2002, pp. 105–110. DOI: https://doi.org/10.1109/ETW.2002.1029646
- RESPIN++ - Deterministic Embedded Test. Lars Schäfer; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW′02), Korfu, Greece, 2002, pp. 37–44. DOI: https://doi.org/10.1109/ETW.2002.1029637
- Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, (April 2002), pp. 231–240. DOI: https://doi.org/10.1023/A:1014968930415
- Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, (April 2002), pp. 159–170. DOI: https://doi.org/10.1023/A:1014993509806
- A Mixed-Mode BIST Scheme Based on Folding Compression. Huaguo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Computer Science and Technology 17, (March 2002), pp. 203–212. DOI: https://doi.org/10.1007/BF02962213
- High Defect Coverage with Low Power Test Sequences in a BIST Environment. Patrick Girard; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel and Hans-Joachim Wunderlich. IEEE Design & Test of Computers 19, (2002), pp. 44–52. DOI: https://doi.org/10.1109/MDT.2002.1033791
2001
- A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, (June 2001), pp. 341–349. DOI: https://doi.org/10.1023/A:1012279716236
- Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, (June 2001), pp. 351–362. DOI: https://doi.org/10.1023/A:1012283800306
- On Applying the Set Covering Model to Reseeding. Silvia Chiusano; Stefano Di Carlo; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE′01), Munich, Germany, 2001, pp. 156–160. DOI: https://doi.org/10.1109/DATE.2001.915017
- Circuit Partitioning for Efficient Logic BIST Synthesis. Alexander Irion; Gundolf Kiefer; Harald Vranken and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE′01), Munich, Germany, 2001, pp. 86–91. DOI: https://doi.org/10.1109/DATE.2001.915005
- Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability. Michael Kessler; Gundolf Kiefer; Jens Leenstra; Knut Schünemann; Thomas Schwarz and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC′01), Baltimore, Maryland, USA, 2001, pp. 461–469. DOI: https://doi.org/10.1109/TEST.2001.966663
- Tailoring ATPG for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC′01), Baltimore, Maryland, USA, 2001, pp. 530–537. DOI: https://doi.org/10.1109/TEST.2001.966671
- Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC′01), Baltimore, Maryland, USA, 2001, pp. 894–902. DOI: https://doi.org/10.1109/TEST.2001.966712
- Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 6th European Test Workshop (ETW′01), Stockholm, Sweden, 2001, pp. 124–132. DOI: https://doi.org/10.1109/ETW.2001.946677
- A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. Patrick Girard; Lois Guiller; Christian Landrault; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 19th VLSI Test Symposium (VTS′01), Marina Del Rey, California, USA, 2001, pp. 306–311. DOI: https://doi.org/10.1109/VTS.2001.923454
2000
- A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC′00), Atlantic City, New Jersey, USA, 2000, pp. 778–784. DOI: https://doi.org/10.1109/TEST.2000.894274
- Non-Intrusive BIST for Systems-on-a-Chip. Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC′00), Atlantic City, New Jersey, USA, 2000, pp. 644–651. DOI: https://doi.org/10.1109/TEST.2000.894259
- Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC′00), Atlantic City, New Jersey, USA, 2000, pp. 105–114. DOI: https://doi.org/10.1109/TEST.2000.894197
- Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, (June 2000), pp. 169–177. DOI: https://doi.org/10.1023/A:1008374811502
- Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, (June 2000), pp. 203–212. DOI: https://doi.org/10.1023/A:1008383013319
- Optimal Hardware Pattern Generation for Functional BIST. Silvia Cataldo; Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 7th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Paris, France, 2000, pp. 292–297. DOI: https://doi.org/10.1109/DATE.2000.840286
1999
- Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE International Test Conference (ITC′99), Atlantic City, New Jersey, USA, 1999, pp. 77–84. DOI: https://doi.org/10.1109/TEST.1999.805616
- Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms. Vyacheslav N. Yarmolik; I.V. Bykov; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 3rd European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999, pp. 339–350. DOI: https://doi.org/10.1007/3-540-48254-7_23
- Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE European Test Workshop (ETW′99), Constance, Germany, 1999, pp. 110–117. DOI: https://doi.org/10.1109/ETW.1999.804415
- Error Detecting Refreshment for Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander Ivaniuk; Yuri Klimets and Vyacheslav N. Yarmolik. In Proceedings of the 17th IEEE VLSI Test Symposium (VTS′99), Dana Point, California, USA, 1999, pp. 384–390. DOI: https://doi.org/10.1109/VTEST.1999.766693
- Symmetric Transparent BIST for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE′99), Munich, Germany, 1999, pp. 702–707. DOI: https://doi.org/10.1109/DATE.1999.761206
- Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 14, (February 1999), pp. 85–93. DOI: https://doi.org/10.1023/A:1008353423305
1998
- BIST for Systems-on-a-Chip. Hans-Joachim Wunderlich. Integration, the VLSI Journal - Special issue on VLSI testing 26, (December 1998), pp. 55–78. DOI: https://doi.org/10.1016/S0167-9260(98)00021-2
- Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Madhavi Karkala; Nur A. Touba and Hans-Joachim Wunderlich. In Proceedings of the 7th Asian Test Symposium (ATS′98), Singapore, 1998, pp. 492–499. DOI: https://doi.org/10.1109/ATS.1998.741662
- Accumulator Based Deterministic BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC′98), Washington, DC, USA, 1998, pp. 412–421. DOI: https://doi.org/10.1109/TEST.1998.743181
- Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC′98), Washington, DC, USA, 1998, pp. 1057–1064. DOI: https://doi.org/10.1109/TEST.1998.743304
- New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Vyacheslav N. Yarmolik; Yuri Klimets; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the Design and Diagnostics of Electronic Circuits and Systems (DDECS′98), Szczyrk, Poland, 1998, pp. 27–33.
- Hardware-Optimal Test Register Insertion. Albrecht P. Stroele and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 17, (June 1998), pp. 531–539. DOI: https://doi.org/10.1109/43.703833
- Fast Self-Recovering Controllers. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE VLSI Test Symposium (VTS′98), Monterey, California, USA, 1998, pp. 296–302. DOI: https://doi.org/10.1109/VTEST.1998.670883
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE′98), Paris, France, 1998, pp. 173–179. DOI: https://doi.org/10.1109/DATE.1998.655853
- Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. Journal of Electronic Testing: Theory and Applications (JETTA) 12, (February 1998), pp. 127–138. DOI: https://doi.org/10.1023/A:1008294125692
- Synthesizing Fast, Online-Testable Control Units. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. IEEE Design & Test of Computers 15, (1998), pp. 36–41. DOI: https://doi.org/10.1109/54.735925
1997
- Using BIST Control for Pattern Generation. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 28th IEEE International Test Conference (ITC′97), Washington, DC, USA, 1997, pp. 347–355. DOI: https://doi.org/10.1109/TEST.1997.639636
- STARBIST: Scan Autocorrelated Random Pattern Generation. Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski and Malgorzata Marek-Sadowska. In Proceedings of the 34th ACM/IEEE Design Automation Conference (DAC′97), Anaheim, California, USA, 1997, pp. 472–477. DOI: https://doi.org/10.1109/DAC.1997.597194
- Fast Controllers for Data Dominated Applications. Andre Hertwig and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC′97), Paris, France, 1997, pp. 84–89. DOI: https://doi.org/10.1109/EDTC.1997.582337
1996
- Bit-Flipping BIST. Hans-Joachim Wunderlich and Gundolf Kiefer. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD′96), San Jose, California, USA, 1996, pp. 337–343. DOI: https://doi.org/10.1109/ICCAD.1996.569803
- Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In Proceedings of the 27th IEEE International Test Conference (ITC′96), Washington, DC, USA, 1996, pp. 195–204. DOI: https://doi.org/10.1109/TEST.1996.556962
- Deterministic Pattern Generation for Weighted Random Pattern Testing. Birgit Reeb and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC′96), Paris, France, 1996, pp. 30–36. DOI: https://doi.org/10.1109/EDTC.1996.494124
1995
- Test Register Insertion with Minimum Hardware Cost. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD′95), San Jose, California, USA, 1995, pp. 95–101. DOI: https://doi.org/10.1109/ICCAD.1995.479998
- Pattern Generation for a Deterministic BIST Scheme. Sybille Hellebrand; Birgit Reeb; Steffen Tarnick and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD′95), San Jose, California, USA, 1995, pp. 88–94. DOI: https://doi.org/10.1109/ICCAD.1995.479997
- Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors. Hans-Joachim Wunderlich; M. Herzog; Joan Figueras; J.A. Carrasco and A. Calderón. In Proceedings of the European Design & Test Conference (ED&TC′95), Paris, France, 1995, pp. 573–580. DOI: https://doi.org/10.1109/EDTC.1995.470342
- Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. Sybille Hellebrand; Janusz Rajski; Steffen Tarnick; Srikanth Venkataraman and Bernard Courtois. IEEE Transactions on Computers 44, (February 1995), pp. 223–233. DOI: https://doi.org/10.1109/12.364534
1994
- A Unified Method for Assembling Global Test Schedules. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 3rd Asian Test Symposium (ATS′94), Nara, Japan, 1994, pp. 268–273. DOI: https://doi.org/10.1109/ATS.1994.367220
- An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD′94), San Jose, California, USA, 1994, pp. 110–116. DOI: https://doi.org/10.1109/ICCAD.1994.629752
- Simulation Results of an Efficient Defect Analysis Procedure. Olaf Stern and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC′94), Washington, DC, USA, 1994, pp. 729–738. DOI: https://doi.org/10.1109/TEST.1994.528019
- Configuring Flip-Flops to BIST Registers. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC′94), Washington, DC, USA, 1994, pp. 939–948. DOI: https://doi.org/10.1109/TEST.1994.528043
- Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the European Design Automation Conference (EDAC/ETC/EuroAsic′94), Paris, France, 1994, pp. 580–585. DOI: https://doi.org/10.1109/EDTC.1994.326815
1993
- An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers. Srikanth Venkataraman; Janusz Rajski; Sybille Hellebrand and Steffen Tarnick. In Proceedings of the ACM/IEEE International Conference on CAD-93 (ICCAD′93), Santa Clara, California, USA, 1993, pp. 572–577. DOI: https://doi.org/10.1109/ICCAD.1993.580117
1992
- Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In Proceedings of the 23rd IEEE International Test Conference (ITC′92), Baltimore, Maryland, USA, 1992, pp. 120–129. DOI: https://doi.org/10.1109/TEST.1992.527812
- Efficient Test Set Evaluation. Hans-Joachim Wunderlich and M. Warnecke. In Proceedings of the 3rd European Conference on Design Automation (EDAC′92), Brussels, Belgium, 1992, pp. 428–433. DOI: https://doi.org/10.1109/EDAC.1992.205970
- Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen. Olaf Stern and Hans-Joachim Wunderlich. In 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, 1992, pp. 117–122. DOI: https://doi.org/10.18419/opus-7903
- Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich and Michael H. Schulz. Informatik-Spektrum 15, (March 1992), pp. 23–32. DOI: https://doi.org/10.18419/opus-7897
- Optimized Synthesis Techniques for Testable Sequential Circuits. Bernhard Eschermann and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, (March 1992), pp. 301–312. DOI: https://doi.org/10.1109/43.124417
- The Pseudoexhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, (January 1992), pp. 26–33. DOI: https://doi.org/10.1109/43.108616
1991
- A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. Thomas Kropf and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE International Test Conference (ITC′91), Nashville, Tennessee, USA, 1991, pp. 57–66. DOI: https://doi.org/10.1109/TEST.1991.519494
- Emulation of Scan Paths in Sequential Circuit Synthesis. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 5th International GI/ITG/GMA Conference on Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment, Nürnberg, Germany, 1991, pp. 136–147. DOI: https://doi.org/10.18419/opus-7904
- TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle and Hans-Joachim Wunderlich. IEEE Journal of Solid-State Circuits 26, (July 1991), pp. 1056–1063. DOI: https://doi.org/10.1109/4.92026
- Signature Analysis and Test Scheduling for Self-Testable Circuits. Albrecht P. Ströle and Hans-Joachim Wunderlich. In Proceedings of the 21st International Symposium on Fault-Tolerant Computing (FTCS-21), Montreal, Canada, 1991, pp. 96–103. DOI: https://doi.org/10.1109/FTCS.1991.146640
- Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures. Hans-Joachim Wunderlich and Albrecht P. Ströle. In Proceedings of the IEEE International Sympoisum on Circuits and Systems (ISCAS′91), Singapur, 1991, pp. 1881–1884. DOI: https://doi.org/10.1109/ISCAS.1991.176774
- A Unified Approach for the Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC′91), San Francisco, California, USA, 1991, pp. 372–377. DOI: https://doi.org/10.1145/127601.127697
- Parallel Self-Test and the Synthesis of Control Units. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 2nd European Test Conference (ETC′91), Munich, Germany, 1991, pp. 73–82. DOI: https://doi.org/10.18419/opus-7920
1990
- TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 16th European Solid-State Circuits Conference (ESSCIRC′90), Grenoble, France, 1990, pp. 101–104. DOI: https://doi.org/10.18419/opus-7921
- Generating Pseudo-Exhaustive Vectors for External Testing. Sybille Hellebrand; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 21st IEEE International Test Conference (ITC′90), Washington, DC, USA, 1990, pp. 670–679. DOI: https://doi.org/10.1109/TEST.1990.114082
- Error Masking in Self-Testable Circuits. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International Test Conference (ITC′90), Washington, DC, USA, 1990, pp. 544–552. DOI: https://doi.org/10.1109/TEST.1990.114066
- Optimized Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 20th International Symposium on Fault-Tolerant Computing (FTCS-20), Newcastle Upon Tyne, United Kingdom, 1990, pp. 390–397. DOI: https://doi.org/10.1109/FTCS.1990.89393
- An Analytical Approach to the Partial Scan Problem. Arno Kunzmann and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 1, (June 1990), pp. 163–174. DOI: https://doi.org/10.1007/BF00137392
- Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 9, (June 1990), pp. 584–593. DOI: https://doi.org/10.1109/43.55187
- The Effectiveness of Different Test Sets for PLAs. Peter C. Maxwell and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC′90), Glasgow, United Kingdom, 1990, pp. 628–632. DOI: https://doi.org/10.1109/EDAC.1990.136722
- A Synthesis Approach to Reduce Scan Design Overhead. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC′90), Glasgow, United Kingdom, 1990, pp. 671. DOI: https://doi.org/10.18419/opus-7927
- Tools and Devices Supporting the Pseudo-Exhaustive Test. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC′90), Glasgow, United Kingdom, 1990, pp. 13–17. DOI: https://doi.org/10.1109/EDAC.1990.136612
- Methoden der Testvorbereitung zum IC-Entwurf. Martin H. Schulz and Hans-Joachim Wunderlich. Mikroelektronik 4, (1990), pp. 112–115. DOI: https://doi.org/10.18419/opus-7919
1989
- Methoden der Testvorbereitung. Hans-Joachim Wunderlich and Martin H. Schulz. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 55–62. DOI: https://doi.org/10.18419/opus-7932
- Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen. F. Kesel and Hans-Joachim Wunderlich. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 63–68. DOI: https://doi.org/10.18419/opus-7933
- The Pseudo-Exhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 20th IEEE International Test Conference (ITC′89), Washington, DC, USA, 1989, pp. 19–27. DOI: https://doi.org/10.1109/TEST.1989.82273
- The Design of Random-Testable Sequential Circuits. Hans-Joachim Wunderlich. In Proceedings of the 19th International Symposium on Fault-Tolerant Computing (FTCS-19), Chicago, Illinois, USA, 1989, pp. 110–117. DOI: https://doi.org/10.1109/FTCS.1989.105552
- The Synthesis of Self-Test Control Logic. Oliver F. Haberl and Hans-Joachim Wunderlich. In Proceedings of the CompEuro ’89., ‘VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks’, Hamburg, Germany, 1989, pp. 5. DOI: https://doi.org/10.1109/CMPEUR.1989.93499
- Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern. Frank Kesel and Hans-Joachim Wunderlich. In GMD Berichte, 4. E.I.S.-Workshop, Bonn, Germany, 1989, pp. 75–84. DOI: https://doi.org/10.18419/opus-7936
1988
- Automatisierung des Entwurfs vollständig testbarer Schaltungen. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 18. GI Jahrestagung II, Hamburg, Germany, 1988, pp. 145–159. DOI: https://doi.org/10.1007/978-3-642-74135-7_10
- Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE International Test Conference (ITC′88). New Frontiers in Testing, International, Washington, DC, USA, 1988, pp. 236–244. DOI: https://doi.org/10.1109/TEST.1988.207808
- Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 18th International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, 1988, pp. 36–41. DOI: https://doi.org/10.1109/FTCS.1988.5294
- Weighted Random Patterns with Multiple Distributions. Hans-Joachim Wunderlich. In Proceedings of the 11th International Conference on Fault Tolerant Systems and Diagnostics, Suhl, German Democratic Republic, 1988, pp. 88–93. DOI: https://doi.org/10.18419/opus-7941
- Output-maximal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1988, pp. 1011–1020. DOI: https://doi.org/10.1080/00207728808547182
1987
- Integrated Tools for Automatic Design for Testability. D. Schmid; Hans-Joachim Wunderlich; F. Feldbusch; Sybille Hellebrand; J. Holzinger and Arno Kunzmann. In Proceedings of the IFIP WG 10.2 Workshop on Tool Integration and Design Environments, Paderborn, Germany, 1987, pp. 233–258. DOI: https://doi.org/10.18419/opus-7942
- The Random Pattern Testability of Programmable Logic Arrays. Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Computer Design (ICCD′87), Port Chester, New York, USA, 1987, pp. 682–685. DOI: https://doi.org/10.18419/opus-7944
- Self Test Using Unequiprobable Random Patterns. Hans-Joachim Wunderlich. In Proceedings of the 17th International Symposium on Fault-Tolerant Computing (FTCS-17), Pittsburgh, Pennsylvania, USA, 1987, pp. 258–263. DOI: https://doi.org/10.18419/opus-7946
- On Computing Optimized Input Probabilities for Random Tests. Hans-Joachim Wunderlich. In Proceedings of the 24th ACM/IEEE Design Automation Conference (DAC′87), Miami Beach, Florida, USA, 1987, pp. 392–398. DOI: https://doi.org/10.1145/37888.37947
1986
- The Integration of Test and High Level Synthesis in a General Design Environment. D. Schmid; R. Camposano; Arno Kunzmann; Wolfgang Rosenstiel and Hans-Joachim Wunderlich. In Proceedings of the Integrated Circuits Technology Conference (ICTC′86), Limerick, Ireland, 1986, pp. 317–331. DOI: https://doi.org/10.18419/opus-7947
- On Fault Modeling for Dynamic MOS Circuits. Hans-Joachim Wunderlich and Wolfgang Rosenstiel. In Proceedings of the 23rd ACM/IEEE Design Automation Conference (DAC′86), Las Vegas, Nevada, USA, 1986, pp. 540–546. DOI: https://doi.org/10.1145/318013.318100
1985
- Design Automation of Random Testable Circuits. Arno Kunzmann and Hans-Joachim Wunderlich. In Proceedings of the 11th European Solid-State Circuits Conference (ESSCIRC′85), Toulouse, France, 1985, pp. 277–285. DOI: https://doi.org/10.18419/opus-7949
- PROTEST: A Tool for Probabilistic Testability Analysis. Hans-Joachim Wunderlich. In Proceedings of the 22nd ACM/IEEE Design Automation Conference (DAC′85), Las Vegas, Nevada, USA, 1985, pp. 204–211. DOI: https://doi.org/10.1145/317825.317858
1984
- Time-optimal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1984, pp. 513–524. DOI: https://doi.org/10.1080/00207729408926580
CA - Workshop Contributions
2017
- Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
2016
- Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
- Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.
2015
- ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
- Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′15), Bad Urach, Germany, 2015.
- Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′15), Bad Urach, Germany, 2015.
2014
- A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE′14 Conference, Dresden, Germany, 2014.
2013
- Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW′13), Cordoba, Argentina, 2013.
- Cross-Layer Dependability Modeling and Abstraction in Systems on Chip. Andreas Herkersdorf; Michael Engel; Michael Glaß; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. In Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 2013.
2012
- Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
2011
- SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Ena, Gifu, Japan, 2011.
- Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′11), Passau, Germany, 2011.
- Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′11), Passau, Germany, 2011, pp. 55–58.
- Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′11), Passau, Germany, 2011.
2010
- Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T′10), Austin, Texas, USA, 2010.
- On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 2010.
- Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′10), Paderborn, Germany, 2010.
- Application Dependent Vulnerability of Combinational Circuits. Rafal Baranowski and Hans-Joachim Wunderlich. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′10), Paderborn, Germany, 2010.
2009
- Modellierung der Testinfrastruktur auf der Transaktionsebene. Michael A. Kochte; Christian Zöllin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In 21th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′09), Bremen, Germany, 2009, pp. 61–66.
- Diagnose mit extrem kompaktierten Fehlerdaten. Stefan Holst and Hans-Joachim Wunderlich. In 21. ITG/GI/GMM Workshop “Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen” (TuZ′09), Bremen, Germany, 2009, pp. 15–20.
2008
- On the Reliability Modeling of Embedded Hardware-Software Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 1st IEEE Workshop on Design for Reliability and Variability (DRV′08), Santa Clara, California, USA, 2008.
- Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian Zöllin. In 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR′08), Verbania, Italy, 2008.
- Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. Torsten Coym; Sybille Hellebrand; Stefan Ludwig; Bernd Straube; Hans-Joachim Wunderlich and Christian Zöllin. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′08), Wien, Austria, 2008, pp. 153–157.
- Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′08), Wien, Austria, 2008.
- Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information. Michael E. Imhof; Hans-Joachim Wunderlich; Christian Zöllin; Jens Leenstra and Nicolas Maeding. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′08), Wien, Austria, 2008, pp. 137–141.
- Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung. Melanie Elm and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′08), Wien, Austria, 2008, pp. 7–11.
2007
- Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian Zöllin; Andreas Glowatz; Jürgen Schlöffel and Friedrich Hapke. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′07), Erlangen, Germany, 2007, pp. 61–65.
- An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′07), Erlangen, Germany, 2007, pp. 56–60.
- Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′07), Erlangen, Germany, 2007, pp. 82–86.
2006
- BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zöllin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′06), Titisee, Germany, 2006, pp. 101–103.
- Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′06), Titisee, Germany, 2006, pp. 95–100.
2005
- Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. Jun Zhou and Hans-Joachim Wunderlich. In INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 2005, pp. 441.
- DLBIST for Delay Testing. Michael Garbers; Jürgen Schlöffel; Valentin Gherman and Hans-Joachim Wunderlich. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′05), Innsbruck, Austria, 2005, pp. 39–43.
- Implementing a Scheme for External Deterministic Self-Test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′05), Innsbruck, Austria, 2005, pp. 27–31.
- Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilian Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′05), Innsbruck, Austria, 2005, pp. 16–20.
2004
- X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In 5th IEEE International Workshop on Test Resource Partitioning (TRP′04), Napa Valley, California, USA, 2004, pp. 442–451.
- EuNICE-Test: European network for test education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS′04), Tatranska Lomnica, Slovakia, 2004.
- Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE International Workshop on Electronic Design, Test and Applications (DELTA′04), Perth, Australia, 2004, pp. 135–140.
- Masking X-Responses During Deterministic Self-Test. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Garbers and Jürgen Schlöffel. In 16th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′04), Dresden, Germany, 2004, pp. 13–19.
2003
- Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level. Yves Bertrand; Marie-Lise Flottes; Nicoleta Pricopi and Hans-Joachim Wunderlich. In 15th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′03), Timmendorfer Strand, Germany, 2003.
2002
- Power Conscious BIST Approaches. Arnaud Virazel and Hans-Joachim Wunderlich. In 3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, 2002, pp. 128–135.
2001
- Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In European Test Workshop (ETW′01), Stockholm, Sweden, 2001, pp. 307–315.
2000
- Using Mission Logic for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In 1st IEEE International Workshop on Test Resource Partitioning (TRP′00), Atlantic City, New Jersey, USA, 2000.
- Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW′00), Informal digest, Cascais, Portugal, 2000, pp. 99–104.
- Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest. Rainer Dorsch and Hans-Joachim Wunderlich. In 12th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′00), Grassau, Germany, 2000, pp. 1–7.
- Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In 7th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 2000.
1999
- Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW′99), Constance, Germany, 1999, pp. 110–116.
- Exploiting Symmetries to Speed Up Transparent BIST. Sybille Hellebrand; Hans-Joachim Wunderlich and Vyacheslav N. Yarmolik. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′99), Potsdam, Germany, 1999, pp. 12–15.
- Minimum Scan Insertion for Generating Pipeline-Structured Modules. Gundolf Kiefer and Hans-Joachim Wunderlich. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′99), Potsdam, Germany, 1999, pp. 30–33.
1998
- Low-Power Serial Built-In Self Test. Andre Hertwig and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW′98), Sitges, Barcelona, Spain, 1998, pp. 51.
- Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW′98), Sitges, Barcelona, Spain, 1998, pp. 39–43.
- Efficient Consistency Checking for Embedded Memories. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
- Pattern Selection for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
- Scan Path Design for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′98), Herrenberg, Germany, 1998.
1997
- Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
- Using BIST Control for Pattern Generation. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop, Cagliari, Italy, 1997.
- STARBIST: Scan Autocorrelated Random Pattern Generation. Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski and Malgorzata Marek-Sadowska. In 4th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1997.
- Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand. Gundolf Kiefer and Hans-Joachim Wunderlich. In 9th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′97), Bremen, Germany, 1997, pp. 49–52.
1996
- Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In 2nd IEEE International On-Line Testing Workshop, Biarritz, France, 1996.
- Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead. Hans-Joachim Wunderlich and Gundolf Kiefer. In IEEE European Test Workshop, Montpellier, France, 1996, pp. 60–64.
- Using Embedded Processors for BIST. Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1996.
1995
- Pattern Generation for a Deterministic BIST Scheme. Sybille Hellebrand; Birgit Reeb; Steffen Tarnick and Hans-Joachim Wunderlich. In 2nd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1995.
- Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest. Olaf Stern and Hans-Joachim and Wunderlich. In 7th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′95), Hannover, Germany, 1995.
1994
- Synthese schneller selbsttestbarer Steuerwerke. Sybille Hellebrand and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme”, Oberwiesenthal, Germany, 1994, pp. 3–11.
- Testsynthese für Datenpfade. Albrecht P. Ströle and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme”, Oberwiesenthal, Germany, 1994, pp. 162–171.
- Synthesis for Testability - the ARCHIMEDES Approach. Sybille Hellebrand; J. P. Teixeira and Hans-Joachim and Wunderlich. In 1st IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1994.
- Ein Verfahren zur testfreundlichen Steuerwerkssynthese. Sybille Hellebrand and Hans-Joachim and Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′94), Vaals, Netherlands, 1994.
- Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. Srikanth Venkataraman; Janusz and Rajski; Sybille and Hellebrand and Steffen and Tarnick. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′94), Vaals, Netherlands, 1994.
- Analyse und Simulation realistischer Fehler. Olaf Stern; Wu and Hans-Joachim Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′94), Vaals, Netherlands, 1994.
1993
- Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
- Effiziente Erzeugung deterministischer Muster im Selbsttest. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ′93), Holzhau, Germany, 1993.
1992
- Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In Workshop on New Directions for Testing, Montreal, Canada, 1992.
- Generation of Test Patterns through Reseeding of Multiple-Polynomial LFSRs. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In IEEE Design for Testability Workshop, Vail, Colorado, USA, 1992.
1990
- Generating Pseudo-Exhaustive Vectors for External Testing. Sybille Hellebrand; Hans-Joachim Wunderlich and Oliver F. Haberl. In IEEE Design for Testability Workshop, Vail, Colorado, USA, 1990.

Hans-Joachim Wunderlich
Prof. Dr. rer. nat. habil.Research Group Computer Architecture,
retired