Publications

Abstract

Die Simulation kleiner Verzögerungsfehler ist ein wichtiger Bestandteil der Validierung nano-elektronischer Schaltungen. Prozessvariationen während der Herstellung haben großen Einfluss auf die Erkennung dieser Fehler und müssen bei der Simulation berücksichtigt werden. Die zeitgenaue Simulation von Verzögerungsfehlern ist verglichen mit traditioneller Logiksimulation oder statischer Zeitanalyse sehr aufwändig und die Rechenkomplexität steigt durch die Berücksichtigung von Variationen zusätzlich an. In dieser Arbeit wird ein hochparalleles Verfahren vorgestellt, welches Grafikprozessoren zur beschleunigten parallelen Simulation kleiner Verzögerungsfehler unter Variation anwendet. Das Verfahren berechnet akkurate Signalverläufe in der Schaltung und ermöglicht die Bestimmung einer Monte-Carlo-basierten statistischen Fehlererfassung für industrielle Schaltkreise unter zufälliger sowie systematischer Variation.

Abstract

General-purpose computations on graphics processing units (GPUs) enable large-scale scientific applications and simulations on the desktop. Such applications typically have high performance and reliability requirements. For GPUs, which are still designed for the graphics mass-market, hardware-based fault tolerance measures often do not have the highest priority, which makes the application of appropriate software-based fault tolerance mandatory. Algorithm-based Fault Tolerance (ABFT) allows the efficient and effective protection of important kernels from scientific computing. Some ABFT schemes have already been adapted for GPU architectures. However, due to roundoff error introduced by floating-point arithmetic, ABFT requires the determination of tight error bounds for the error detection. The determination of such error bounds is a highly challenging task. In this work, we introduce A-ABFT for GPUs, a new parallel ABFT scheme that determines appropriate error bounds for the checksum comparison step autonomously and which therefore enables the transparent operation of ABFT without any user interaction.

Abstract

The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture level resilience methods.

Abstract

In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional diagnosis is applied during integration and in workshops for infield failures or break-downs. However, functional diagnosis does not yield sufficient coverage to allow for short repair times and fast reaction on systematic failures in the production. Structural diagnosis could yield the desired coverage, yet recent builtin architectures which could be reused in the field either do not reveal diagnostic information or necessitate dedicated test schemes. The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection. The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can seamlessly be integrated with recent, commercial DfT techniques. Experiments with industrial designs show that its overhead is marginal and its structural diagnostic capabilities are comparable to those of external diagnosis on high-end test equipment.

Abstract

Die Mustererzeugung für den eingebetteten Test besteht häufig aus einer Phase zur Erzeugung von Zufallsmustern und einer Phase, in der deterministische Muster angelegt werden. Der vorliegende Beitrag stellt eine Methode vor, die erste Phase signifikant zu optimieren, um dadurch die Defekterfassung zu vergrößern und zugleich die Zahl der erforderlichen deterministischen Muster in der zweiten Phase zu reduzieren. Die Methode beruht auf dem pseudo-erschöpfenden Test (PET), der als Verfahren zum fehlermodellunabhängigen Test mit hoher Defekterfassung vorgeschlagen wurde. Da seine Testzeit exponentiell mit der Schaltungsgröße wachsen kann, ist die Anwendung auf große Schaltungen in der Regel ausgeschlossen. In der vorliegenden Arbeit werden eingebaute Testregister für den partiellen pseudo-erschöpfenden Test (P-PET) vorgeschlagen, der mit aktueller Technologie skaliert und hinsichtlich Testkosten und Testzeit mit dem üblichen pseudo-zufälligen Test (PZT) vergleichbar ist. Die Vorteile bezüglich der Defekterfassung, N-Detektierbarkeit für Haftfehler und der Reduktion deterministischer Testlängen werden anhand aktueller industrieller Schaltungen nachgewiesen.

Abstract

Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design- for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.

Abstract

Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch. The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design.

Abstract

Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking. Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are overmasked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.

Abstract

Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.

Abstract

Im Hochvolumentest sind Testzeit, Testdatenvolumen und hochperformante Tester die entscheidenden Kostenfaktoren. Techniken des eingebetteten Tests wie ”Built–in Self–test“ (BIST) und ”Multi–site“–Testen senken effizient die Testkosten, machen die Diagnose aber schwerer. Diese Arbeit stellt ein Verfahren zur Antwortkompaktierung und ein entsprechendes Diagnoseverfahren vor, das sich besonders für BIST und den ”Multi–site“–Test eignet. Die experimentellen Ergebnisse an industriellen Schaltungen zeigen, dass sich mit diesem Ansatz gleichzeitig die Testzeit verk¨ urzt, das Antwortvolumen reduziert und die diagnostische Auflösung verbessert. Ein Vergleich mit X-Compact zeigt, dass einfache Paritäts–Informationen höhere diagnostische Auflösungen pro Antwortbit ermöglichen als komplexere Signaturen.

Abstract

In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. In arrays, error correcting coding is the dominant technique to achieve acceptable soft-error rates. For low power applications, often latches are clock gated and have to retain their states during longer periods while miniaturization has led to elevated susceptibility and further increases the need for protection. This paper presents a fault-tolerant register latch organization that is able to detect single-bit errors while it is clock gated. With small addition, single and multiple errors are detected in the clocked mode, too. The registers can be efficiently integrated similar to the scan design flow, and error detecting or locating information can be collected at module level. The resulting structure can be efficiently reused for offline and general online testing.

Abstract

Der während des Selbsttests von Schaltungen mit deaktivierbaren Prüfpfaden verwendete Testplan entscheidet über die Verlustleistung während des Tests. Bestehende Verfahren zur Erzeugung des Testplans verwenden überwiegend topologische Information, zum Beispiel den Ausgangskegel eines Fehlers. Aufgrund der implizit gegebenen Verknüpfung zwischen Testplan und Mustermenge ergeben sich weitreichende Synergieeffekte durch die Ausschöpfung mustermengenabhängiger Informationen. Die Verwendung von testmengenspezifischer Information im vorgestellten Algorithmus zeigt bei gleichbleibender Fehlererfassungsrate und Testdauer deutliche Einsparungen in der benötigten Verlustleistung. Das Verfahren wird an industriellen und Benchmark-Schaltungen mit bestehenden, überwiegend topologisch arbeitenden Verfahren verglichen.

Abstract

In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministric patterns than existing programmable methods and provides high flexibilily for test engineering in bolh internal and external test. Theoretical analysis suggests that significanlly more care bits can be encoded in the seed or a Linear Feedback Shift Register (LFSR) if a limited number of conflicting equations are ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern, but in contrast to bit-flipping BIST, the test set is not embedded by a synthesized logic function. Instead, this information is stored in memory using a special compression architecture. Experiments for benchmark circuits industrial designs demonstrate that the approach has considerably higher overall coding efficency than the existing methods.

Abstract

Built-in self test is a major part of the manufacturing test procedure for the Cell Processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by dynamic clock gating. Therefore, the test power envelope is expected to be so high, that the scan-speed has to be reduced significantly, thus extending test time. We propose a test power reduction method that uses scan-gating with Logic BIST. In LBIST, except for the first dozens of patterns, patterns that detect additional faults (effective patterns) are very scarce and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern even requires only a reduced set of the available scan chains to detect the fault and all don't-care scan chains can be disabled, therefore significantly reducing test power.

Abstract

Der softwarebasierende Selbsttest von Prozessoren (SBST) bietet zahlreiche Vorteile wie den Verzicht auf teure Testautomaten, die autonome Testdurchführung während der Wartung oder die Möglichkeit, einen Initialisierungstest für das Gesamtsystem zu implementieren. In dieser Arbeit wird eine strukturbasierte SBST Methode vorgestellt, die bezüglich Energieaufnahme, durchschnittlicher Verlustleistung, Testlänge und Fehlerüberdeckung gleichzeitig optimiert.

Abstract

Due to its inherent support for at-speed test, BIST is an attractive approach to test delay faults. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to enhance the quality of BIST in the case of stuck-at test. The test of delay faults requires the application of pattern pairs. Consequently, delay faults have a lower random pattern testability than stuck-at faults and this increases the need for a DLBIST scheme. On the other hand, a DLBIST solution is expected to require a larger mapping effort and logic overhead than in the case of stuck-at test. In this paper, we present the extension of a DLBIST scheme which becomes available for the test of both delay (transition) faults and stuck-at faults. Functional justification is used to generate the pattern pairs required by the target delay faults. We investigate the efficiency of the extended scheme in the case of some industrial benchmarks.

Abstract

Software-basierender Selbsttest (SBST) von Prozessoren wird schon seit Jahrzehnten verwendet, da er erhebliche Vorteile bietet, wie z. B. die Wiederverwendbarkeit in allen Stadien des Lebenszykluses des Systems, der Verzicht auf kostspielige Tester und geringe oder sogar gar kein Aufwand für „Design for Test“. Die größten Nachteile sind die unzureichende strukturelle Fehlerabdeckung sowie relativ lange Testanwendungszeiten. In jüngster Zeit wurden große Fortschritte bei der Kombination der Erzeugung von strukturellen Testmustern und SBST gemacht. Dieser Ansatz macht das „Peak Power Problem” weniger dringend, da der Test im Systemmodus und nicht in einem speziellen Testmodus durchgeführt wird, der zu einer erhöhten Schaltaktivität führt. Der durchschnittliche Energiebedarf muss jedoch immer noch optimiert werden. Geringer Speicherbedarf, kurze Ausführungzeiten sowie eine hohen Fehlerabdeckung sind für den effizienten Einsatz der SBST Methode unerlässlich. In diesem Beitrag wird eine strukturelle SBST Methode präsentiert, welche diese drei Parameter gleichzeitig optimiert. Zuerst stellen wir einen Algorithmus vor, mit dem ein effektives Testprogramm mit minimalem menschlichem Eingreifen synthetisiert werden kann. Die konventionellen Techniken zur Energieoptimierung der Software können an dieser Stelle nicht angewandt werden, da mit ihnen das Ziel verfolgt wird, die Semantik eines Programms beizubehalten, während bei SBST hingegen die strukturelle Fehlerabdeckung beibehalten werden muss. Um dieser speziellen Anforderung gerecht zu werden, stellen wir anschließend unseren Optimierungsprozess vor, der das Verhalten des eingebetteten Tests analysiert, um dieselbe Fehlerüberdeckung zu erhalten, und dabei Freiheitsgrade bei der Befehlsreihenfolge und Don’t Cares verwendet , um Energie zu sparen. Schließlich wird die Methode auf Gatterebene validiert. Den Ergebnissen zufolge kann die Energie um 40% und die Testdauer um 30% reduziert werden ohne an Fehlerabdeckung einzubüßen.

Abstract

A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression method for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.

Abstract

For the first time, we study the coverage of non-target defects for Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST implementation options that result in test sequences of different lengths. Resistive bridging faults are used as a surrogate of non-target defects. Experimental data obtained for largest ISCAS benchmarks suggests that, although DLBIST always guarantees complete stuck-at coverage, test sequence length does influence the non-target defect detection capabilities. For circuits with a large fraction of random-pattern resistant faults, the embedded deterministic patterns as well as a sufficient amount of random patterns are both demonstrated to be essential for non-target defect detection. It turns out, moreover, that area cost is lower for DLBIST solutions with longer test sequences, due to additional degrees of freedom for the embedding procedure and a lower number of faults undetected by pseudorandom patterns. This implies that DLBIST is particularly effective in covering non-target defects.

Abstract

The launching of the EuNICE-Test project was announced two years ago at the first DELTA Conference 1. This project is now completed and it is the objective of the present paper to describe the project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and remote experiment. This objective is fully fulfilled and we have now in Europe five centres of competence that are able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centres propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode after project end. Nevertheless a new European proposal with several new partners and new test lessons is under construction.

Abstract

We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the area overhead low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

Abstract

The paper deals with a European experience of education in industrial test of ICs and SoCs using remote testing facilities. The project addresses the problem of the shortage in microelectronics engineers aware with the new challenge of testing mixed-signal SoCs for multimedia/telecom market. It aims at providing test training facilities at a European scale in both initial and continuing education contexts. This is done by allowing the academic and industrial partners of the consortium to train engineers using the common test resources center (CRTC) hosted by LIRMM (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France). CRTC test tools include up-to-date/high-tech testers that are fully representative of real industrial testers as used on production testfloors. At the end of the project, it is aimed at reaching a cruising speed of about 16 trainees per year per center. Each trainee will have attend at least one one-week training using the remote test facilities of CRTC.

Abstract

The System-On-Chip (SOC) revolution has brought some new challenges to both design and test engineers. The most important challenges of today’s VLSI systems testing are linked to test cost, defect coverage and power dissipation. Implementing a self-testable system may reduce test costs as expensive external high performance test equipment is not required and it may increase defect coverage as testing is performed at system speed. Unfortunately, the classic BIST approaches lead to a significant increase of power consumption compared to the system mode and even compared to external testing. The paper will review required changes to be applied to classic BIST techniques for power reduction. A recently developed new BIST approach called functional BIST is introduced and its consequences for power dissipation are discussed.

Abstract

The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

Abstract

Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.

Abstract

Testing logic cores of a system-on-a-chip causes a high test data volume which has to be stored on the external automatic test equipement (ATE), a high bandwidth requirement between ATE and the chip under test implying the need for high-speed ATE. This paper reduces these requirements by reusing embedded cores during test mode as embedded testers. Hard, firm, and soft cores may be reused, since only the functionality of the core in system mode is used.

Abstract

Der deterministische funktionale Selbsttest vereint die Vorteile des funktionalen und des deterministischen strukturellen Tests. Der deterministische funktionale Selbsttest wird wie der funktionale Test mit Systemgeschwindigkeit durchgeführt, beeinflußt die Geschwindigkeit im Systembetrieb nicht und erkennt Verzögerungsfehler. Zudem besitzt er die hohe Fehlerüberdeckung des deterministischen strukturellen Tests. Dies wird erreicht, indem funktionale Einheiten auf dem System so gesteuert werden, daß berechnete deterministische Testvektoren erzeugt werden. Wir stellen eine neue Methode zur Steuerung der funktionalen Einheiten vor, die einen deterministischen Mustersatz stärker komprimiert als bisher bekannte Verfahren.

Abstract

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

Abstract

An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.

Abstract

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

Abstract

A target structure for implementing fast on-line testable control units for data-dominated applications is presented. In many cases, the proposed controller structure leads to a performance improvement of more than 30% for a standard benchmark set whereas the area overhead is less than 15% compared with conventional on-line testable finite state machines (FSM). The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.

Abstract

A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be bused for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.

Abstract

This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order and polarity in scan synthesis, effectively converting the scan chain into a ROM capable of storing some “center” patterns from which the other vectors are derived by randomly complementing some of their coordinates. Experimental results demonstrate that a very high fault coverage can be obtained without any modification of the mission logic, no test data to store and very simple BIST hardware which does not depend on the size of the circuit.

Abstract

Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.

Abstract

Es wird ein Verfahren vorgestellt, Steuerwerke als Pipelinestruktur zu synthetisieren. Dadurch kann ein Selbsttest ohne Integration zusätzlicher Testregister implementiert werden, so daß die durch den Selbsttest verursachten Laufzeitverzögerungen reduziert, die Fehlererfassung verbessert und in vielen Fällen die Gesamtfläche der testbaren Schaltungen verringert werden können. Eine selbsttestbare Struktur für einen vorgegebenen endlichen Automaten kann aus einer geeigneten Realisierung der Maschine erzeugt werden, es wird gezeigt, daß solche Realisierungen stets konstruierbar sind. Ein Algorithmus zur Bestimmung optimaler Realisierungen wird vorgestellt, und die Ergebnisse werden an Hand von Benchmarkschaltungen validiert.

Abstract

The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach .

Abstract

In the past years special chips for external test have been successfully used for random pattern testing. In this paper a technique is presented to combine the advantages of such a low cost test with the advantages of pseudo-exhaustive testing, which are an enhanced fault coverage and a simplified test pattern generation. To achieve this goal two tasks are solved. Firstly, an algorithm is developed for pseudo-exhaustive test pattern generation, which ensures a feasible test length. Secondly, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the presented algorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.