Functional BIST

01.1999 - 03.2003, BMBF - Project

Integrating complex systems into single chips has become a widespread approach in developing electronic systems. A variety of embedded coreware can be found on the market, which allows to appropriately split the system functionality into both hardware (HW) and software (SW) modules. Since for these systems, as for any microelectronic product, defect free manufacturing cannot be guaranteed, efficient test approaches are required to identify and sort out faulty products. With the recent technology developments, however, system testing has become an enormous challenge: the complexity and the restricted accessibility of HW components require sophisticated test strategies, and it has been widely accepted that built-in self-test (BIST) helps to tackle the problem at low costs. Established BIST solutions use special hardware for pattern generation (TPG) and test response evaluation (TRE) on chip, but this may introduce significant area overhead and performance degradation.

To overcome these problems, recently new methods have been proposed which exploit specific functional units such as arithmetic units or processor cores for on-chip test pattern generation and test response evaluation [1-3]. In particular, it has been shown that adders can be used as TPGs for pseudo-random, pseudo-exhaustive and deterministic patterns. But up to now there is no general method how to use arbitrary functional units for built-in TPG or TRE. The goal of this project is to close this gap and to develop a general method which rigorously exploits the functionality of the system itself for implementing an efficient low cost BIST.