ROCK

ROCK: Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

08.2011 - 12.2015, DFG-Project: WU 245/12-1

Activities

H.-J. Wunderlich: "Fault Tolerance Meets Diagnosis", Keynote at the 21st IEEE International On-Line Testing Symposium (IOLTS), Elia, Halkidiki, Greece, July 6-8, 2015

Publications

2017
1. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (May 2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
  Abstract
  In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g. by operating concurrently vs. pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis.
  BibTeX
  @article{SchleDEHWR2017, abstract = {In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g. by operating concurrently vs. pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis. }, abteilung = {ra}, author = {Schley, Gert and Dalirsani, Atefe and Eggenberger, Marcus and Hatami, Nadereh and Wunderlich, Hans-Joachim and Radetzki, Martin}, day = 1, doi = {10.1109/TC.2016.2628058}, journal = {IEEE Transactions on Computers}, month = {05}, number = 5, owner = {hellmelr}, pages = {848--861}, project = {ROCK}, title = {{Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_SchleDEHWR2017.pdf}, volume = 66, year = 2017 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_SchleDEHWR2017.pdf
  DOI
  10.1109/TC.2016.2628058
2. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (May 2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
  Abstract
  In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g. by operating concurrently vs. pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis.
  BibTeX
  @article{SchleDEHWR2017, abstract = {In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g. by operating concurrently vs. pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis. }, abteilung = {ra}, author = {Schley, Gert and Dalirsani, Atefe and Eggenberger, Marcus and Hatami, Nadereh and Wunderlich, Hans-Joachim and Radetzki, Martin}, day = 1, doi = {10.1109/TC.2016.2628058}, journal = {IEEE Transactions on Computers}, month = {05}, number = 5, owner = {hellmelr}, pages = {848--861}, project = {ROCK}, title = {{Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_SchleDEHWR2017.pdf}, volume = 66, year = 2017 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/TC_SchleDEHWR2017.pdf
  DOI
  10.1109/TC.2016.2628058
2015
1. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
  Abstract
  Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.
  BibTeX
  @inproceedings{WundeR2015, abstract = {Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.}, abteilung = {ra}, address = {Vancouver, BC, Canada}, author = {Wunderlich, Hans-Joachim and Radetzki, Martin}, booktitle = {Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS'15)}, day = {28--30}, doi = {10.1145/2786572.2788708}, location = {Vancouver, BC, Canada}, month = {09}, owner = {haefneht}, project = {ROCK}, title = {{Multi-Layer Test and Diagnosis for Dependable NoCs}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/NOCS_WundeR2015.pdf}, year = 2015 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/NOCS_WundeR2015.pdf
  DOI
  10.1145/2786572.2788708
2. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
  Abstract
  Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.
  BibTeX
  @inproceedings{WundeR2015, abstract = {Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.}, abteilung = {ra}, address = {Vancouver, BC, Canada}, author = {Wunderlich, Hans-Joachim and Radetzki, Martin}, booktitle = {Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS'15)}, day = {28--30}, doi = {10.1145/2786572.2788708}, location = {Vancouver, BC, Canada}, month = {09}, owner = {haefneht}, project = {ROCK}, title = {{Multi-Layer Test and Diagnosis for Dependable NoCs}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/NOCS_WundeR2015.pdf}, year = 2015 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/NOCS_WundeR2015.pdf
  DOI
  10.1145/2786572.2788708
2014
1. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
  Abstract
  This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.
  BibTeX
  @inproceedings{DalirKW2014, abstract = {This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.}, abteilung = {ra}, address = {Platja d'Aro, Catalunya, Spain}, author = {Dalirsani, Atefe and Kochte, Michael A. and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS'14)}, day = {7--9}, doi = {10.1109/IOLTS.2014.6873662}, location = {Platja d'Aro, Catalunya, Spain}, month = {07}, owner = {haefneht}, pages = {13--18}, project = {ROCK}, title = {{Area-Efficient Synthesis of Fault-Secure NoC Switches}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/IOLTS_DalirKW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/IOLTS_DalirKW2014.pdf
  DOI
  10.1109/IOLTS.2014.6873662
2. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
  Abstract
  This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.
  BibTeX
  @inproceedings{DalirKW2014, abstract = {This paper introduces a hybrid method to synthesize area-efficient fault-secure NoC switches to detect all errors resulting from any single-point combinational or transition fault in switches and interconnect links. Firstly, the structural faults that are always detectable by data encoding at flit-level are identified. Next, the fault-secure structure is constructed with minimized area such that errors caused by the remaining faults are detected under any given input vector. The experimental evaluation shows significant area savings compared to conventional fault-secure schemes. In addition, the resulting structure can be reused for test compaction. This reduces the amount of test response data and test time without loss of fault coverage or diagnostic resolution.}, abteilung = {ra}, address = {Platja d'Aro, Catalunya, Spain}, author = {Dalirsani, Atefe and Kochte, Michael A. and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 20th IEEE International On-Line Testing Symposium (IOLTS'14)}, day = {7--9}, doi = {10.1109/IOLTS.2014.6873662}, location = {Platja d'Aro, Catalunya, Spain}, month = {07}, owner = {haefneht}, pages = {13--18}, project = {ROCK}, title = {{Area-Efficient Synthesis of Fault-Secure NoC Switches}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/IOLTS_DalirKW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/IOLTS_DalirKW2014.pdf
  DOI
  10.1109/IOLTS.2014.6873662
3. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
  Abstract
  Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.
  BibTeX
  @inproceedings{DalirHIESRW2014, abstract = {Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.}, abteilung = {ra}, address = {Hangzhou, China}, author = {Dalirsani, Atefe and Hatami, Nadereh and Imhof, Michael E. and Eggenberger, Marcus and Schley, Gert and Radetzki, Martin and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 23rd IEEE Asian Test Symposium (ATS'14)}, day = {16--19}, doi = {10.1109/ATS.2014.27}, location = {Hangzhou, China}, month = {11}, owner = {imhofml}, pages = {87--92}, project = {ROCK}, title = {{On Covering Structural Defects in NoCs by Functional Tests}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ATS_DalirHIESRW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ATS_DalirHIESRW2014.pdf
  DOI
  10.1109/ATS.2014.27
4. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
  Abstract
  Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.
  BibTeX
  @inproceedings{DalirIW2014, abstract = {Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.}, abteilung = {ra}, address = {Napa, California, USA}, author = {Dalirsani, Atefe and Imhof, Michael E. and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 32nd IEEE VLSI Test Symposium (VTS'14)}, day = {13--17}, doi = {10.1109/VTS.2014.6818754}, location = {Napa, California, USA}, month = {04}, owner = {imhofml}, project = {ROCK}, title = {{Structural Software-Based Self-Test of Network-on-Chip}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/VTS_DalirIW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/VTS_DalirIW2014.pdf
  DOI
  10.1109/VTS.2014.6818754
5. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
  Abstract
  Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.
  BibTeX
  @inproceedings{DalirHIESRW2014, abstract = {Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering structural faults. The method targets NoC switches and links, and it is independent of the switch structure and the network topology. It can be applied for any structural fault type as it relies on a generalized structural fault model.}, abteilung = {ra}, address = {Hangzhou, China}, author = {Dalirsani, Atefe and Hatami, Nadereh and Imhof, Michael E. and Eggenberger, Marcus and Schley, Gert and Radetzki, Martin and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 23rd IEEE Asian Test Symposium (ATS'14)}, day = {16--19}, doi = {10.1109/ATS.2014.27}, location = {Hangzhou, China}, month = {11}, owner = {imhofml}, pages = {87--92}, project = {ROCK}, title = {{On Covering Structural Defects in NoCs by Functional Tests}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ATS_DalirHIESRW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ATS_DalirHIESRW2014.pdf
  DOI
  10.1109/ATS.2014.27
6. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
  Abstract
  Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.
  BibTeX
  @inproceedings{DalirIW2014, abstract = {Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips (NoC). Test patterns for structural faults are turned into valid packets by using satisfiability (SAT) solvers. The test technique provides a high fault coverage for both manufacturing test and online test.}, abteilung = {ra}, address = {Napa, California, USA}, author = {Dalirsani, Atefe and Imhof, Michael E. and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 32nd IEEE VLSI Test Symposium (VTS'14)}, day = {13--17}, doi = {10.1109/VTS.2014.6818754}, location = {Napa, California, USA}, month = {04}, owner = {imhofml}, project = {ROCK}, title = {{Structural Software-Based Self-Test of Network-on-Chip}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/VTS_DalirIW2014.pdf}, year = 2014 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/VTS_DalirIW2014.pdf
  DOI
  10.1109/VTS.2014.6818754
2012
1. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (October 2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
  Abstract
  Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.
  BibTeX
  @article{DalirHEW2012, abstract = {Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.}, abteilung = {ra}, author = {Dalirsani, Atefe and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim}, doi = {10.1007/s10836-012-5329-9}, issn = {0923-8174}, journal = {Journal of Electronic Testing: Theory and Applications (JETTA)}, language = {English}, month = {10}, number = 6, owner = {Thomas}, pages = {831--841}, project = {ROCK}, publisher = {Springer-Verlag}, title = {{Structural Test and Diagnosis for Graceful Degradation of NoC Switches}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/JETTA_DalirHEW2012.pdf}, volume = 28, year = 2012 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/JETTA_DalirHEW2012.pdf
  DOI
  10.1007/s10836-012-5329-9
2. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (October 2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
  Abstract
  Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.
  BibTeX
  @article{DalirHEW2012, abstract = {Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.}, abteilung = {ra}, author = {Dalirsani, Atefe and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim}, doi = {10.1007/s10836-012-5329-9}, issn = {0923-8174}, journal = {Journal of Electronic Testing: Theory and Applications (JETTA)}, language = {English}, month = {10}, number = 6, owner = {Thomas}, pages = {831--841}, project = {ROCK}, publisher = {Springer-Verlag}, title = {{Structural Test and Diagnosis for Graceful Degradation of NoC Switches}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/JETTA_DalirHEW2012.pdf}, volume = 28, year = 2012 }
  Link
  https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2012/JETTA_DalirHEW2012.pdf
  DOI
  10.1007/s10836-012-5329-9

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ROCK: Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration

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