ROCK: Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

08.2011 - 12.2015, DFG-Project: WU 245/12-1


  • H.-J. Wunderlich: "Fault Tolerance Meets Diagnosis", Keynote at the 21st IEEE International On-Line Testing Symposium (IOLTS), Elia, Halkidiki, Greece, July 6-8, 2015


  1. 2017

    1. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (2017), pp. 848--861. DOI:
  2. 2015

    1. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI:
  3. 2014

    1. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI:
    2. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI:
    3. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI:
  4. 2013

    1. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI:
  5. 2012

    1. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (2012), pp. 831--841. DOI:
Hans-Joachim Wunderlich (i.R.)
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Heading the Research Group Computer Architecture

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