MAYA: Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität

Until 2008 digital circuitry will increase up to nearly 100 million gate equivalences; that will result in about 4 times more test vec-tors than required today. The costs of testing these new ICs and their huge data volume produced will add up to at least a factor of three, the required test time to a factor of 10. Even if not considering the increased number of pins, test cost per IC will explode to a factor of 120. The project MAYA will address this challenge by developing and integrating innovative technology for capturing data massively in parallel on-chip as well as multisite testing, and fast data processing to off-chip. These solutions will meet the demand for the next higher through-put increase of high-volume production testing at high quality.

05.2006 - 04.2009, BMBF - Project

For further information please visit our German pages.


This image shows Hans-Joachim Wunderlich

Hans-Joachim Wunderlich

Prof. Dr. rer. nat. habil.

Research Group Computer Architecture,

To the top of the page