FAQs RISC-V Processor Design
The pre-registration on this website will open on September 15, 15:00. Read through the following information carefully and if you still want to register (and it is after September 15, 15:00), please enter your information (name; Matrikelnummer; and the semester in which you did the CAO exam) into the field below. There will be C@mpus and ILIAS entries for the lab course later.
The course is divided into 10 weekly problem sheets B1-B10 (with theoretical and practical parts) and a 4-week project phase. A RISC-V processor core will be designed from scratch in Verilog, integrated into the open-source PULPUS system-on-chip, and mapped onto an FPGA platform.
The topics of the 10 sheets are as follows:
B1: Full adder
B2: Design and test of an ALU
B3: Register bank and program counter
B4: Traffic-light circuit
B5-B6: Control unit
B8: Synthesis of the processor and a test program
B9: Instruction cache
B10: Control & status register; unaligned memory accesses
Our COVID-19 concept, which is currently under evaluation by University-internal authorities, allows up to 12 students (6 groups of two). This is a firm limit, which we cannot exceed. We are hopeful to offer this course in future semesters with a higher participation limit.
Yes, we will accept only students who have successfully passed the exam in Computer Architecture and Organization (CAO). That course covers the RISC-V instruction set and its basic organization, and this lab course strongly builds on this knowledge. Prior knowledge of Verilog is not necessary, you will learn it in the course.
No, we insist on a passed CAO exam as a formal qualification. This lab course will be inappropriately difficult for someone without basic knowledge, and we have to expect that students with insufficient knowledge will drop out in the middle of semester. It would be very unfortunate to have rejected some qualified students just to give a chance to unqualified students. Moreover, the situation of the teammate of someone who dropped out becomes difficult. If you know the material, please take the CAO exam this semester and participate in this lab course in one of the following semesters.
Yes, we have obligatory attendance for this course. You will need the physical access to the FPGA board, to computers with FPGA synthesis software, to VGA monitors on which test images will be displayed. Moreover, you will have to explain your solutions to the instructor and demonstrate them live. If you cannot arrange attendance every week (e.g., if you are working, or you are not in Stuttgart), please do not register, in order to not take away seats from those who can participate.
Keep 1.5 distance; wear the mask when entering/leaving/walking through the lab (you can work on your seat without mask); wash hands before entering; use designated doors for entering and leaving the lab. We will use one-time covers for keyboards and disinfect tables and equipment after use. We will have airflow through the lab’s windows (you may want to wear something warm in winter) and have our AC switched off.
The grade will depend on the number of sheets you passed, the 4-weeks project phase and the final presentation. There will be no written or oral exam. You can expect that passing sheets B1-B8 will be sufficient for grade 4.0 (while passing everything will obviously give you a 1.0); we will announce a detailed grading scheme in the beginning of the course. A sheet is considered “passed” if the theoretical part is solved correctly (at home, before a meeting); the practical part is functional in the corresponding or in the next week; and, once the processor is functional and integrated, the test program (Mandelbrot set computation) is executed correctly.
No, every sheet can only be passed in its corresponding week or in the next week. If you are more than one week behind, your participation is unsuccessful. Please take this into account when deciding whether to register; if you are not sure you will have time to work throughout the semester, do not register and give a chance to others.
Registration for Infotech RISC-V Kurs
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