RM-BIST: Reliability Monitoring and Managing Built-In Self Test

The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

07.2012 - 06.2015, DFG-Project: WU 245/13-1



    This image shows Hans-Joachim Wunderlich (i.R.)

    Hans-Joachim Wunderlich (i.R.)

    Prof. Dr. rer. nat. habil.

    Heading the Research Group Computer Architecture

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