RM-BIST

RM-BIST: Reliability Monitoring and Managing Built-In Self Test

The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

07.2012 - 06.2015, DFG-Project: WU 245/13-1

 

Publications

  1. 2015

    1. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    2. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    3. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    4. Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. Michael Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omana; Cecilia Metra and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 157–162. DOI: https://doi.org/10.1109/ATS.2015.34
    5. On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 589--592. DOI: https://doi.org/10.7873/DATE.2015.0940
  2. 2014

    1. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    2. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    3. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    4. Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
  3. 2013

    1. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    2. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    3. Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS’13), Avignon, France, 2013, pp. 39--45. DOI: https://doi.org/10.1109/ETS.2013.6569354
  4. 2012

    1. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
Dieses Bild zeigt Wunderlich (i.R.)
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Heading the Research Group Computer Architecture

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