VIVA / LEISTE

VIVA: Self-test under Power and Energy Constraints

What is VIVA?

With the popularity of embedded applications and portable devices, power consumption of systems receives higher attention throughout all design levels. The programme of "Grundlagen und Verfahren verlustarmer Informationsverarbeitung (VIVA)", sponsored by Deutsche Forschungsgemeinschaft (DFG), studies fundamentals and methods for low-power information processing.

Project: Self-test under Power and Energy Constraints

Software-based self-test (SBST) is viewed as a promising alternative as traditional hardware-based test methods for microprocessors due to its benefits of at-speed test, dispense with expensive test equipments and low design-for-testability (DfT) overhead. Its principle is illustrated in the following figure which involves generation, storage and execution of test programs.

 

Fig.: Software-based self-test (SBST)

 

Test quality is maximized under the consideration of the structure of the core under test (CUT) during test program synthesis. The SBST operates under the functional mode so that it meets the peak power specification of the system; nevertheless, it is of great significance for reliability reasons to optimize programs causing above-average switching activities. It is particularly true when such a test is deployed autonomously where both average power and energy consumption play a crucial role. This project proposed a novel method that tackles fault coverage, test length, energy and average power consumption at the same time.

Journals and Conference Proceedings

  1. 2006

    1. Software-Based Self-Test of Processors under Power Constraints. Jun Zhou and Hans-Joachim Wunderlich. In Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE’06), Munich, Germany, 2006, pp. 430--436. DOI: https://doi.org/10.1109/DATE.2006.243798

Workshop Contributions

  1. 2006

    1. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 95--100.
  2. 2005

    1. Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. Jun Zhou and Hans-Joachim Wunderlich. In INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 2005, pp. 441--441.
  3. 2002

    1. Power Conscious BIST Approaches. Arnaud Virazel and Hans-Joachim Wunderlich. In 3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, 2002, pp. 128--135.
Hans-Joachim Wunderlich (i.R.)
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Heading the Research Group Computer Architecture

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