Publications

ES - Publications

  1. 2019

    1. Combined MPSoC Task Mapping and Memory Optimization for Low-Power. Manuel Strobel; Gereon Führ; Martin Radetzki and Rainer Leupers. In to appear in Proc. IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Bangkok, Thailand, 2019.
    2. A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. Jie Hou; Q. Han and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, 2019.
    3. Design-Time Memory Subsystem Optimization for Low- Power Multi-Core Embedded Systems. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded (MCSoC), Singapore, 2019.
    4. A Methodology to Compute Long-Term Fault Resilience of NoCs under Fault-Tolerant Routing Algorithms. Jie Hou and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages(FDL), Southampton, UK, 2019.
    5. Power-Mode-Aware Memory Subsystem Optimization for Low-Power System-on-Chip Design. Manuel Strobel and Martin Radetzki. To appear in ACM Transactions on Embedded Computing Systems(TECS) (2019).
    6. A Backend Tool for the Integration of Memory Optimizations into Embedded Software. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages (FDL), Southampton, UK, 2019.
    7. Automated Sensor Firmware Development - Generation, Optimization, and Analysis. Jens Rudolf; Manuel Strobel; Joscha Benz; Cristian Haubelt; Martin Radetzki and Oliver Bringmann. In MBMV 2019; 22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019, pp. 1–12.
  2. 2018

    1. Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. Jie Hou and Martin Radetzki. In 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2018, Cambridge, United Kingdom, March 21-23, 2018, 2018, pp. 609--616. DOI: https://doi.org/10.1109/PDP2018.2018.00102

Former ES - Publications

  1. 2017

    1. Low power memory allocation and mapping for area-constrained systems-on-chips. Manuel Strobel; Marcus Eggenberger and Martin Radetzki. EURASIP J. Emb. Sys. 2017, (2017), pp. 2. DOI: https://doi.org/10.1186/s13639-016-0039-5
    2. Hybrid instruction set simulation for fast and accurate memory access profiling. Manuel Strobel and Martin Radetzki. In 13th Workshop on Intelligent Solutions in Embedded Systems, WISES 2017, Hamburg, Germany, June 12-13, 2017, 2017, pp. 23--28. DOI: https://doi.org/10.1109/WISES.2017.7986927
    3. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Trans. Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    4. Semi-symbolic operational computation for robust control system design. Leandro Gil and Martin Radetzki. In 22nd International Conference on Methods and Models in Automation and Robotics, MMAR 2017, Miedzyzdroje, Poland, August 28-31, 2017, 2017, pp. 779--784. DOI: https://doi.org/10.1109/MMAR.2017.8046927
  2. 2016

    1. Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Gert Schley; Ibrahim Ahmed; Muhammad Afzal and Martin Radetzki. Computers & Electrical Engineering 51, (2016), pp. 195--206. DOI: https://doi.org/10.1016/j.compeleceng.2016.02.013
    2. Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. Leandro Gil and Martin Radetzki. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 499--504.
    3. Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. Marcus Eggenberger; Manuel Strobel and Martin Radetzki. In 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, 2016, pp. 763--770. DOI: https://doi.org/10.1109/PDP.2016.118
  3. 2015

    1. Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. Gert Schley and Martin Radetzki. In 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, 2015, pp. 379--386. DOI: https://doi.org/10.1109/PDP.2015.36
    2. Optimal memory selection for low power embedded systems. Marcus Eggenberger and Martin Radetzki. In 12th International Workshop on Intelligent Solutions in Embedded Systems, WISES 2015, Ancona, Italy, October 29-30, 2015, 2015, pp. 11--16.
    3. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, 2015, pp. 5:1--5:8. DOI: https://doi.org/10.1145/2786572.2788708
  4. 2014

    1. SystemC AMS power electronic modeling with ideal instantaneous switches. Leandro Gil and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119365
    2. Asynchronous parallel simulation with transaction events. Bastian Haetzer and Martin Radetzki. In XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, 2014, pp. 242--249. DOI: https://doi.org/10.1109/SAMOS.2014.6893217
    3. Editorial introduction - Special issue on languages, models and model based design for embedded systems. Martin Radetzki and Axel Jantsch. Design Autom. for Emb. Sys. 18, 1–2 (2014), pp. 61--62. DOI: https://doi.org/10.1007/s10617-012-9094-x
    4. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    5. A comparison of parallel systemc simulation approaches at RTL. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119355
  5. 2013

    1. Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. Gert Schley; Nikolaos Batzolis and Martin Radetzki. In 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013, pp. 454--461. DOI: https://doi.org/10.1109/PDP.2013.74
    2. Simulation analysis and validation. Frank Oppenheimer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    3. Fine grained adaptive simulation with application to NoCs. Marcus Eggenberger and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--8.
    4. Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. Khalid Latif; Amir-Mohammad Rahmani; Ethiopia Nigussie; Tiberiu Seceleanu; Martin Radetzki and Hannu Tenhunen. J. Electronic Testing 29, 3 (2013), pp. 431--452. DOI: https://doi.org/10.1007/s10836-013-5389-5
    5. Optimal placement of vertical connections in 3D Network-on-Chip. Thomas Canhao Xu; Gert Schley; Pasi Liljeberg; Martin Radetzki; Juha Plosila and Hannu Tenhunen. Journal of Systems Architecture - Embedded Systems Design 59, 7 (2013), pp. 441--454. DOI: https://doi.org/10.1016/j.sysarc.2013.05.002
    6. Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. Adán Kohler and Martin Radetzki. In 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, Physical and Social Computing (CPSCom), Beijing, China, August 20-23, 2013, 2013, pp. 77--85. DOI: https://doi.org/10.1109/GreenCom-iThings-CPSCom.2013.38
    7. Systemc transaction level modeling with transaction events. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--6.
    8. Platform based design. Jean-Philippe Babau and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    9. Scalable parallel simulation of networks on chip. Marcus Eggenberger and Martin Radetzki. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013, 2013, pp. 1--8. DOI: https://doi.org/10.1109/NoCS.2013.6558402
    10. Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Weiyun Lu and Martin Radetzki. Microprocessors and Microsystems - Embedded Hardware Design 37, 2 (2013), pp. 115--128. DOI: https://doi.org/10.1016/j.micpro.2012.09.005
    11. Methods for fault tolerance in networks-on-chip. Martin Radetzki; Chaochao Feng; Xueqian Zhao and Axel Jantsch. ACM Comput. Surv. 46, 1 (2013), pp. 8:1--8:38. DOI: https://doi.org/10.1145/2522968.2522976
  6. 2012

    1. Low-Latency Collectives for the Intel SCC. Adán Kohler; Martin Radetzki; Philipp Gschwandtner and Thomas Fahringer. In 2012 IEEE International Conference on Cluster Computing, CLUSTER 2012, Beijing, China, September 24-28, 2012, 2012, pp. 346--354. DOI: https://doi.org/10.1109/CLUSTER.2012.58
    2. Minimal MPI as programming interface for multicore System-on-Chips. Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross and Martin Radetzki. In Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, 2012, pp. 127--134.
    3. Latency-optimized Collectives for High Performance on Intel’s Single-chip Cloud Computer. Adán Kohler and Martin Radetzki. In Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, November 29th-30th 2012, Aachen, Germany, 2012, pp. 7--12.
    4. Semantics and efficient simulation of accuracy-adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. Design Autom. for Emb. Sys. 16, 3 (2012), pp. 1--29. DOI: https://doi.org/10.1007/s10617-012-9095-9
    5. Optimized Reduce for Mesh-Based NoC Multiprocessors. Adán Kohler and Martin Radetzki. In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, 2012, pp. 904--913. DOI: https://doi.org/10.1109/IPDPSW.2012.111
  7. 2011

    1. Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. Martin Radetzki. In IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, Melbourne, Australia, October 24-26, 2011, 2011, pp. 33--40. DOI: https://doi.org/10.1109/EUC.2011.36
    2. A metamodel and semantics for transaction level modeling. Rauf Salimi Khaligh and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    3. Cost-Based Deflection Routing for Intelligent NoC Switches. Martin Radetzki and Adán Kohler. In Solutions on Embedded Systems, Massimo Conti; Simone Orcioni; Natividad Mart\’ınez Madrid and Ralf E. D. Seepold (eds.). Springer, 2011, pp. 77--90. DOI: https://doi.org/10.1007/978-94-007-0638-5_6
    4. Efficient Fault Simulation of SystemC Designs. Weiyun Lu and Martin Radetzki. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, 2011, pp. 487--494. DOI: https://doi.org/10.1109/DSD.2011.68
    5. Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 6th Workshop on Embedded Systems Education, WESE 2011, Taipei, Taiwan, October 13, 2011, 2011, pp. 1--8. DOI: https://doi.org/10.1145/2077370.2077371
    6. A case study on message-based discrete event simulation for Transaction Level Modeling. Bastian Haetzer and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    7. Optimal distribution of privileged nodes in networks-on-chip. Gert Schley and Martin Radetzki. In Proceedings of the Ninth Workshop on Intelligent Solutions in Embedded Systems, WISES 2011, Regensburg, Germany, July 7-8, 2011, 2011, pp. 87--92.
  8. 2010

    1. Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). Gert Schley; Martin Radetzki and Adán Kohler. it - Information Technology 52, 4 (2010), pp. 201--208. DOI: https://doi.org/10.1524/itit.2010.0592
    2. A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 2010 Forum on specification & Design Languages,FDL 2010, September 14-16, 2010, Southampton, UK, 2010, pp. 130--135.
    3. Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. Adán Kohler; Gert Schley and Martin Radetzki. IEEE Trans. on CAD of Integrated Circuits and Systems 29, 6 (2010), pp. 883--896. DOI: https://doi.org/10.1109/TCAD.2010.2048399
    4. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010, pp. 1183--1188. DOI: https://doi.org/10.1109/DATE.2010.5456987
  9. 2009

    1. Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. Adán Kohler and Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, 2009, pp. 207--216.
    2. An intelligent deflection router for networks-on-chip. Martin Radetzki and Adán Kohler. In Seventh Workshop on Intelligent solutions in Embedded Systems, WISES 2009, Ancona, Italy, June 25-26, 2009, 2009, pp. 57--62.
    3. Test exploration and validation using transaction level models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    4. A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. Adán Kohler and Martin Radetzki. In Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, 2009, pp. 1--4.
    5. Fault-tolerant architecture and deflection routing for degradable NoC switches. Adán Kohler and Martin Radetzki. In Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, 2009, pp. 22--31. DOI: https://doi.org/10.1109/NOCS.2009.5071441
    6. Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL’08, September 23-25, 2008, Stuttgart, Germany. Martin Radetzki (Ed.). 2009. DOI: https://doi.org/10.1007/978-1-4020-9714-0
    7. Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. Rauf Salimi Khaligh and Martin Radetzki. In Analysis, Architectures and Modelling of Embedded Systems, Third IFIPTC 10 International Embedded Systems Symposium, IESS 2009, Langenargen,Germany, September 14-16, 2009. Proceedings, 2009, pp. 149--158. DOI: https://doi.org/10.1007/978-3-642-04284-3_14
  10. 2008

    1. A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. Rauf Salimi Khaligh and Martin Radetzki. In Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings, 2008, pp. 37--42. DOI: https://doi.org/10.1109/FDL.2008.4641418
    2. Adaptive Interconnect Models for Transaction-Level Simulation. Rauf Salimi Khaligh and Martin Radetzki. In Languages for Embedded Systems and their Applications - Selected Contributionson Specification, Design, and Verification from FDL’08, September23-25, 2008, Stuttgart, Germany, 2008, pp. 149--165. DOI: https://doi.org/10.1007/978-1-4020-9714-0_10
    3. A data traffic efficient H.264 deblocking IP. Weining Hao and Martin Radetzki. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, 2008, pp. 3430--3433. DOI: https://doi.org/10.1109/ISCAS.2008.4542196
    4. Accuracy-Adaptive Simulation of Transaction Level Models. Martin Radetzki and Rauf Salimi Khaligh. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 788--791. DOI: https://doi.org/10.1109/DATE.2008.4484912
  11. 2007

    1. Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. Rauf Salimi Khaligh and Martin Radetzki. In Embedded System Design: Topics, Techniques and Trends, IFIP TC10Working Conference: International Embedded Systems Symposium (IESS),May 30 - June 1, 2007, Irvine, CA, USA, 2007, pp. 313--324. DOI: https://doi.org/10.1007/978-0-387-72258-0_27
    2. Modelling Alternatives for Cycle Approximate Bus TLMs. Martin Radetzki and Rauf Salimi Khaligh. In Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, 2007, pp. 74--79.
    3. Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007, 2007, pp. 181--190.
  12. 2006

    1. SystemC TLM Transaction Modelling and Dispatch for Active Object. Martin Radetzki. In Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings, 2006, pp. 203--209.
  13. 2004

    1. Intelligent IP retrieval driven by application requirements. Martin Schaaf; Andrea Freßmann; Rainer Maximini; Ralph Bergmann; Alexander Tartakovski and Martin Radetzki. Integration 37, 4 (2004), pp. 253--287. DOI: https://doi.org/10.1016/j.vlsi.2004.01.002
    2. IPQ: IP Qualification for Efficient System Design. Hans-Jürgen Brand; Steffen Rülke and Martin Radetzki. In 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, 2004, pp. 478--482. DOI: https://doi.org/10.1109/ISQED.2004.1283719
    3. Measurement of IP Qualification Costs and Benefits. Andreas Vörg; Martin Radetzki and Wolfgang Rosenstiel. In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, 2004, pp. 996--1001. DOI: https://doi.org/10.1109/DATE.2004.1269023
  14. 2003

    1. sciPROVE: C++ Based Verification Environment for IP and SoC Design1. U. Badelt; H. Kühl and Martin Radetzki. In Forum on specification and Design Languages, FDL 2003, September 23-26, 2003, Frankfurt, Germany, Proceedings, 2003, pp. 617--627.
  15. 2002

    1. Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions). Martin Radetzki. it+ti - Informationstechnik und Technische Informatik 44, 2 (2002), pp. 99--102. DOI: https://doi.org/10.1524/itit.2002.44.2.099
    2. A Qualification Platform for Design Reuse. Ralf Seepold; Natividad Mart\’ınez Madrid; Andreas Vörg; Wolfgang Rosenstiel; Martin Radetzki; P. Neumann and J. Haase. In 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, 2002, pp. 75--80. DOI: https://doi.org/10.1109/ISQED.2002.996698
  16. 2000

    1. Synthesis of digital circuits from object oriented specifications. Martin Radetzki. University of Oldenburg, Germany.2000.
  17. 1999

    1. Data Type Analysis for Hardware Synthesis from Object-Oriented Models. Martin Radetzki; Ansgar Stammermann; Wolfram Putzke-Röming and Wolfgang Nebel. In 1999 Design, Automation and Test in Europe (DATE ’99), 9-12 March 1999, Munich, Germany, 1999, pp. 491. DOI: https://doi.org/10.1109/DATE.1999.761171
  18. 1998

    1. A Unified Approach to Object-Oriented VHDL. Martin Radetzki; Wolfram Putzke-Röming and Wolfgang Nebel. J. Inf. Sci. Eng. 14, 3 (1998), pp. 523--545.
    2. A Flexible Message Passing Mechanism for Objective VHDL. Wolfram Putzke-Röming; Martin Radetzki and Wolfgang Nebel. In 1998 Design, Automation and Test in Europe (DATE ’98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, 1998, pp. 242--249. DOI: https://doi.org/10.1109/DATE.1998.655863
    3. ATM Cell Modelling using Objective VHDL. Alberto Allara; Massimo Bombana; Patrizia Cavalloro; Wolfgang Nebel; Wolfram Putzke-Röming and Martin Radetzki. In Proceedings of the ASP-DAC ’98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, 1998, pp. 261--264. DOI: https://doi.org/10.1109/ASPDAC.1998.669461
    4. Übersetzung von Objektorientiertem VHDL nach Standard VHDL. Martin Radetzki; Wolfram Putzke-Röming and Wolfgang Nebel. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Paderborn, Germany, March 9-11, 1998, 1998, pp. 21--29.
  19. 1996

    1. Development of a Telephone Answering Machine in a Lab - FPGAs in Education. Guido Schumacher; Bernhard Josko; Gerhard Wagner and Martin Radetzki. In Field-Programmable Logic, Smart Applications, New Paradigms and Compilers,6th International Workshop on Field-Programmable Logic, FPL ’96,Darmstadt, Germany, September 23-25, 1996, Proceedings, 1996, pp. 400--404. DOI: https://doi.org/10.1007/3-540-61730-2_46
Prof. Dr.-Ing.

Martin Radetzki

Chair of Embedded Systems

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