Publications

Publications of the Hardware Orientied Computer Science Chair

HOCOS - Publications

  1. 2023

    1. Exploring gate-diversity enabled by reconfigurable memristive technology. Sebastian Brandhofer; Ziang Chen; Li-Wei Chen; Nan Du and Ilia Polian. In To appear in Proceedings of IEEE Int’l Conf. on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey, 2023.
    2. Side-channel Attacks on Memristive Circuits Under External Disturbances. Li-Wei Chen; Xianyue Zhao; Ziang Chen; Nan Du and Ilia Polian. In 2023 IEEE 32nd Asian Test Symposium (ATS), Beijing, China, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ATS59501.2023.10317969
    3. Optimal qubit reuse for near-term quantum computers. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. In To appear in Proceedings Quantum Computing and Engineering Conf.~(QCE), Seattle, Washington, USA, 2023.
    4. A modular open-source cryptographic co-processor for Internet of Things. Dina Hesse; Maël Gay; Ilia Polian and Elif Bilge Kavun. In To appear in Proceedings of Euromicro Conf. Digital System Design (DSD), Durres, Albania, 2023.
    5. Optimizing quantum algorithms on bipotent architectures. Yanjun Ji; Kathrin F. Koenig and Ilia Polian. Phys. Rev. A 108, 2 (August 2023), pp. 022610. DOI: https://doi.org/10.1103/PhysRevA.108.022610
    6. Stochastic Computing as a Defence Against Adversarial Attacks. Florian Neugebauer; Vivek Vekariya; Ilia Polian and John P. Hayes. In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), Porto, Portugal, 2023, pp. 191–194. DOI: https://doi.org/10.1109/DSN-W58399.2023.00053
    7. Overview of Memristive Cryptography. Ilia Polian; Nan Du and Werner Schindler. In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 2023, pp. 1–5. DOI: https://doi.org/10.1109/NEWCAS57931.2023.10198201
    8. Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing. Lorenzo Masciullo; Roberto Passerone; Francesco Regazzoni and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ETS56758.2023.10174181
    9. Automating Greybox System-Level Test Generation. Denis Schwachhofer; Maik Betka; Steffen Becker; Stefan Wagner; Matthias Sauer and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–4. DOI: https://doi.org/10.1109/ETS56758.2023.10173985
    10. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. Jens Anders; Pablo Andreu; Bernd Becker; Steffen Becker; Riccardo Cantoro; Nikolaos I. Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernandez; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; Abolfazl Sajadi; Mathias Sauer; Denis Schwachhofer; Matteo Sonza Reorda; Todor Stefanov; Ilya Tuzov; Stefan Wagner and Nuša Zidarič. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–10. DOI: https://doi.org/10.1109/ETS56758.2023.10174099
    11. LEDA: Locking enabled differential analysis of cryptographic circuits. Devanshi Upadhyaya; Mael Gay and Ilia Polian. In To appear in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, USA, 2023.
    12. SAT-Based Quantum Circuit Adaptation. Sebastian Brandhofer; Jinwoong Kim; Siyuan Niu and Nicholas T. Bronn. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    13. Review on Resistive Switching Devices Based on Multiferroic              BiFeO(3). Xianyue Zhao; Stephan Menzel; Ilia Polian; Heidemarie Schmidt and Nan Du. Nanomaterials (Basel) 13, 8 (April 2023). DOI: https://doi.org/10.3390/nano13081325
    14. Design Rationale for Symbiotically Secure Key Management Systems in IoT and Beyond. W. Bartsch; P. Gope; E. Kavun; O. Millwood; A. Mohammadi Pasikhani; A. Panchenko and I. Polian. In To appear In 9th International Conference on Information System Security and Privacy (ICISSP 2023), Lisbon, Portugal, 2023.
    15. Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor. Paul R. Genssler; Florian Klemme; Shivendra Singh Parihar; Sebastian Brandhofer; Girish Pahwa; Ilia Polian; Yogesh Singh Chauhan and Hussam Amrouch. IEEE Transactions on Quantum Engineering (2023). DOI: https://doi.org/10.1109/TQE.2023.3300833
    16. Optimal Partitioning of Quantum Circuits Using Gate Cuts and Wire Cuts. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. IEEE Transactions on Quantum Engineering (2023), pp. 1–10. DOI: https://doi.org/10.1109/TQE.2023.3347106
    17. On Side-Channel Analysis of Memristive Cryptographic Circuits. Li-Wei Chen; Ziang Chen; Werner Schindler; Xianyue Zhao; Heidemarie Schmidt; Nan Du and Ilia Polian. IEEE Transactions on Information Forensics and Security 18, (2023), pp. 463–476. DOI: https://doi.org/10.1109/TIFS.2022.3223232
    18. On the limitations of logic locking the approximate circuits. Karthik Nayak; Devanshi Upadhyaya; Francesco Regazzoni and Ilia Polian. In To appear in Proceedings of IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Singapore, SG, 2023.
  2. 2022

    1. Benchmarking the performance of portfolio optimization with QAOA. Daniel Brandhofer, Sebastianand Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. Quantum Information Processing 22, 1 (December 2022), pp. 25. DOI: https://doi.org/10.1007/s11128-022-03766-5
    2. Physics inspired compact modelling of BiFe₃ based memristors. Sahitya Yarragolla; Nan Du; Torben Hemke; Xianyue Zhao; Ziang Chen; Ilia Polian and Thomas Mussenbrock. Scientific Reports 12, 1 (November 2022), pp. 20490. DOI: https://doi.org/10.1038/s41598-022-24439-4
    3. Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
    4. Calibration-Aware Transpilation for Variational Quantum Optimization. Yanjun Ji; Sebastian Brandhofer and Ilia Polian. In 2022 IEEE International Conference on Quantum Computing and Engineering (QCE), 2022, pp. 204–214. DOI: https://doi.org/10.1109/QCE53715.2022.00040
    5. Human vs. Automatic Detection of Deepfake Videos Over Noisy Channels. Swaroop Shankar Prasad; Ofer Hadar; Thang Vu and Ilia Polian. In 2022 IEEE International Conference on Multimedia and Expo (ICME), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ICME52920.2022.9859954
    6. Benchmarking the performance of portfolio optimization with QAOA. Sebastian Brandhofer; Daniel Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2207.10555
    7. Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. Hussam Amrouch; Krishnendu Chakrabarty; Dirk Pflüger; Ilia Polian; Matthias Sauer and Matteo Sonza Reorda. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810416
    8. Stochastic Computing Architectures for Lightweight LSTM Neural Networks. Roshwin Sengupta; Ilia Polian and John P. Hayes. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2022, pp. 124–129. DOI: https://doi.org/10.1109/DDECS54261.2022.9770167
    9. Security in an Approximated World: New Threats and Opportunities in the Approximate Computing Paradigm. Paolo Palmieri; Ilia Polian and Francesco Regazzoni. In Approximate Computing Techniques: From Component- to Application-Level, Alberto Bosio; Daniel Ménard and Olivier Sentieys (eds.). Springer International Publishing, Cham, 2022, pp. 323--348. DOI: https://doi.org/10.1007/978-3-030-94705-7_11
    10. On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks. Florian Neugebauer; Stefan Holst and Ilia Polian. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810429
    11. Second Harmonic Generation Exploiting Ultra-Stable Resistive Switching Devices for Secure Hardware Systems. Ziang Chen; Nan Du; Mahdi Kiani; Xianyue Zhao; Ilona Skorupa; Stefan E. Schulz; Danilo Bürger; Massimiliano Di Ventra; Ilia Polian and Heidemarie Schmidt. IEEE Transactions on Nanotechnology 21, (2022), pp. 71–80. DOI: https://doi.org/10.1109/TNANO.2021.3135713
  3. 2021

    1. Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security. Domenic Forte; Debdeep Mukhopadhyay; Ilia Polian; Yunsi Fei and Rosario Cammarota. J. Emerg. Technol. Comput. Syst. 17, 3 (June 2021). DOI: https://doi.org/10.1145/3464326
    2. ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), Virtual, 2021, pp. 1--6.
    3. Security, Reliability and Test Aspects of the RISC-V Ecosystem. Jaume Abella; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernandez; Mike Hutter; Leonidas Kosmidis; Ilia Polian; Matthias Sauer; Stefan Wagner and Francesco Regazzoni. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), 2021.
    4. Noisy Intermediate-Scale Quantum (NISQ) Computers: How They Work, How They Fail, How to Test Them? Sebastian Brandhofer; Simon Devitt; Thomas Wellens and Ilia Polian. In Proceedings of the 39th IEEE VLSI Test Symposium (VTS’21), Virtual, 2021, pp. 1--6.
    5. Machine Learning for Semiconductor Test and Reliability. Hussam Amrouch; Animesh Basak Chowdhury; Wentian Jin; Ramesh Karri; Khorrami Farshad; Prashanth Krishnamurthy; Ilia Polian; Victor M. van Santen; Benjamin Tan and Sheldon Tan. In IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
    6. Nano Security: From Nano-Electronics to Secure Systems. Ilia Polian; Frank Altmann; Tolga Arul; Christian Boit; Ralf Brederlow; Lucas Davi; Rolf Drechsler; Nan Du; Thomas Eisenbarth; Tim Güneysu; Sascha Hermann; Matthias Hiller; Rainer Leupers; Farhad Merchant; Thomas Mussenbrock; Stefan Katzenbeisser; Akash Kumar; Wolfgang Kunz; Thomas Mikolajick; Vivek Pachauri; Jean-Pierre Seifert; Frank Sill Torres and Jens Trommer. In Proceedings of the Conference on Design, Automation &  Test in Europe (DATE’21), Virtual Event, 2021.
    7. System-Level Test: State of the art and challenges. Davide Appello; H. H. Chen; Matthias Sauer; Ilia Polian; Paolo Bernardi and Matteo Sonza Reorda. In Proc. IEEE Int’l On-Line Test Test Symp., online, 2021.
    8. Towards reliable in-memory computing: From emerging devices to post-von-Neumann architectures. Hussam Amrouch; Nan Du; Anteneh Gebregiorgis; Said Hamdioui and Ilia Polian. In Proc. IFIP / IEEE Int’l Conf. on Very Large Scale Integration (VLSI-SoC). (Accepted), online, 2021.
    9. Detection of malicious spatial-domain steganography over noisy channels. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. In Multidisciplinary Approach to Modern Digital Steganography, Sabyasachi Pramanik; Mangesh Manikrao Ghonge; Renjith V. Ravi and Korhan Cengiz (eds.). IGI Global, 2021.
    10. Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications. Ilia Polian; John P. Hayes; Vincent T. Lee and Weikang Qian. IEEE Design & Test 38, 6 (2021), pp. 5–15. DOI: https://doi.org/10.1109/MDAT.2021.3080989
    11. Extending circuit design flow for early assessment of fault attack vulnerabilities. Felipe Valencia; Ilia Polian and Francesco Regazzoni. In Proc. Euromicro Conf. on Digital System Design. (Accepted), online, 2021.
    12. Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning. Francesco Regazzoni; Paolo Palmieri; Fethulah Smailbegovic; Rosario Cammarota and Ilia Polian. CAAI Transactions on Intelligence Technology 6, 2 (2021), pp. 180–191. DOI: https://doi.org/10.1049/cit2.12029
    13. On resilience of security-oriented error detecting architectures against power attacks: A theoretical analysis. Osnat Keren and I. Polian. In Proc. Computing Frontiers Conference / MalIoT Workshop., online, 2021.
    14. Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms. Sebastian Brandhofer; Ilia Polian and Hans Peter Büchler. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1–7. DOI: https://doi.org/10.1109/ICCAD51958.2021.9643490
    15. Low-power emerging memristive designs towards secure hardware systems for applications in internet of things. Nan Du; Heidemarie Schmidt and Ilia Polian. Nano Materials Science 3, 2 (2021), pp. 186–204.
    16. Error Analysis of the Variational Quantum Eigensolver Algorithm. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021, pp. 1–6. DOI: https://doi.org/10.1109/NANOARCH53687.2021.9642249

Former HOCOS - Publications

  1. 2024

    1. Scenario-based test content optimization: Scan-test vs.~system-level test. Nourhan Elhamawy; Ilia Polian; Jens Anders and Matthias Sauer. In To appear in Proceedings of 42nd IEEE VLSI Test Symposium (VTS), Tempe, AZ, USA, 2024.
    2. Locking enabled security analysis of cryptographic circuits. Devanshi Upadhyaya; Maël Gay and Ilia Polian. Cryptography 8, 1 (2024).
  2. 2020

    1. Machine learning and hardware security: challenges and opportunities. Francesco Regazzoni; Shivam Bhasin; Amir Ali Pour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natal; Paul Franzon; David Hely; Naofumi Homma; Akira Ito; Dirmanto Jap; Priyank Kashyap; Ilia Polian; Seetal Potluri; Rei Ueno; Elena Ioana Vatajelu and Ville Yli-Mayry. In Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD’20), 2020.
    2. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
    3. Hardware-based fast real-time image classification with stochastic computing. Ponana Kelettira Muthappa; Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 38th IEEE International Conference on Computer Design (ICCD’20), 2020.
    4. Side Channel Attacks vs Approximated Computing. Francesco Regazzoni and Ilia Polian. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), 2020, pp. 321–326. DOI: https://doi.org/10.1145/3386263.3407592
    5. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
    6. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
    7. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
    8. IPM-RED: combining higher-order masking with robust error detection. Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00229-4
    9. Error control scheme for malicious and natural faults in cryptographic modules. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00234-7
    10. Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont and Ilia Polian. In 2020 Design, Automation  Test in Europe Conference  Exhibition (DATE), 2020, pp. 508–513. DOI: https://doi.org/10.23919/DATE48585.2020.9116483
    11. Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. Electronic Imaging 2020, 4 (January 2020), pp. 76-1-76–7. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
    12. Information leakage from robust codes protecting cryptographic primitives. Osnat Keren and Ilia Polian. In Frontiers in Hardware Security and Trust: Theory, design and practice, C.H. Chang and Y Cao (eds.). The Institution of Engineering and Technology, 2020.
    13. Detection of malicious spatial-domain steganography over noisy channels using convolutional neural networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. In Proc. Media Watermarking, Security, and Forensics Conference at IS&T Electronic Imaging, 2020. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
  3. 2019

    1. On the Limits of Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In 2019 IEEE International Conference on Rebooting Computing, ICRC, 2019, pp. 98--105. DOI: https://doi.org/10.1109/ICRC.2019.8914706
    2. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Mael Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019, pp. 25–32. DOI: https://doi.org/10.1109/FDTC.2019.00012
    3. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    4. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    5. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
    6. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    7. A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives. Osnat Keren and Ilia Polian. In Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019, pp. 49--63. DOI: https://doi.org/10.29007/r2sc
    8. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
    9. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
    10. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    11. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
  4. 2018

    1. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    2. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    3. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    4. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    5. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    6. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
    7. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    8. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    9. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    10. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    11. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    12. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    13. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    14. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    15. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    16. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
  5. 2017

    1. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    2. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    3. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    4. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    5. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    6. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    7. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    8. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    9. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    10. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    11. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    12. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
    13. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    14. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    15. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    16. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    17. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    18. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
  6. 2016

    1. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    2. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    3. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    4. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    5. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    6. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    7. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    8. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    9. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    10. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
    11. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    12. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    13. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    14. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
  7. 2015

    1. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    2. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
    3. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    4. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    5. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    6. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    7. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    8. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    9. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    10. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  8. 2014

    1. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    2. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    3. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    4. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    5. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
    6. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    7. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    8. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    9. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    10. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    11. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    12. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    13. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    14. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    15. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    16. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    17. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    18. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
    19. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    20. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    21. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    22. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    23. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    24. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    25. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    26. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
    27. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    28. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
    29. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    30. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
    31. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    32. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
  9. 2013

    1. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    2. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    3. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    4. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    5. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    6. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    7. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    8. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    9. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    10. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
    11. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    12. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    13. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    14. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    15. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    16. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    17. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    18. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
  10. 2012

    1. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    2. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    3. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    4. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    5. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    6. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    7. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    8. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    9. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    10. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    11. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    12. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    13. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    14. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    15. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    16. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
    17. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    18. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    19. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    20. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    21. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    22. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    23. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    24. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    25. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    26. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    27. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    28. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    29. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    30. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
  11. 2011

    1. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    2. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    3. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    4. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    5. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    6. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    7. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    8. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    9. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    10. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    11. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    12. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    13. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    14. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    15. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    16. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    17. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    18. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    19. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    20. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  12. 2010

    1. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    2. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    3. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    4. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
    5. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    6. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    7. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    8. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    9. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    10. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    11. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    12. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    13. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    14. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    15. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    16. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  13. 2009

    1. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
    2. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    3. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
    4. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
    5. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
    6. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    7. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
    8. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
    9. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
    10. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    11. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    12. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
    13. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
    14. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
  14. 2008

    1. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
    2. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    3. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
    4. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
    5. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
    6. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
    7. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
    8. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
    9. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
    10. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
    11. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
    12. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
    13. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
    14. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
    15. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
    16. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
    17. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
    18. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    19. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
    20. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    21. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    22. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
  15. 2007

    1. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
    2. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    3. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
    4. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
    5. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
    6. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
    7. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
    8. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    9. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
    10. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
    11. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
    12. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
  16. 2006

    1. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
    2. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
    3. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
    4. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
    5. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
    6. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    7. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
    8. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
    9. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
    10. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
    11. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
    12. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
    13. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
    14. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
    15. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    16. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
    17. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
    18. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
  17. 2005

    1. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
    2. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
    3. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
    4. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
    5. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
    6. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
    7. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
    8. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
    9. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
    10. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
    11. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
    12. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
    13. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
    14. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
  18. 2004

    1. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
    2. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
    3. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    4. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
    5. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
    6. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
    7. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
    8. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    9. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
    10. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
    11. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
    12. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
    13. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
    14. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
  19. 2003

    1. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25--44. DOI: https://doi.org/10.1016/S0167-9260(03)00003-8
    2. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
    3. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, 2003, pp. 11184--11185. DOI: https://doi.org/10.1109/DATE.2003.10051
    4. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. Jonathan Bradford; Hartmut Delong; Ilia Polian and Bernd Becker. J. Electronic Testing 19, 4 (2003), pp. 387--395. DOI: https://doi.org/10.1023/A:1024635824944
    5. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
    6. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423

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This image shows Ilia Polian

Ilia Polian

Prof. Dr. rer. nat. habil.

Head of Institute and Chair of Hardware Oriented Computer Science

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