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Publications of the Hardware Orientied Computer Science Chair

HOCOS - Publications

2020
1. Machine learning and hardware security: challenges and opportunities. Francesco Regazzoni; Shivam Bhasin; Amir Ali Pour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natal; Paul Franzon; David Hely; Naofumi Homma; Akira Ito; Dirmanto Jap; Priyank Kashyap; Ilia Polian; Seetal Potluri; Rei Ueno; Elena Ioana Vatajelu and Ville Yli-Mayry. In to appear in Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{regazzoni2020machine, abteilung = {hocos}, author = {Regazzoni, Francesco and Bhasin, Shivam and Ali Pour, Amir and Alshaer, Ihab and Aydin, Furkan and Aysu, Aydin and Beroulle, Vincent and Di Natal, Giorgio and Franzon, Paul and Hely, David and Homma, Naofumi and Ito, Akira and Jap, Dirmanto and Kashyap, Priyank and Polian, Ilia and Potluri, Seetal and Ueno, Rei and Vatajelu, Elena Ioana and Yli-Mayry, Ville}, booktitle = {to appear in Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD'20)}, month = nov, title = {Machine learning and hardware security: challenges and opportunities}, year = 2020 }
2. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In to appear in Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{polian2020exploring, abteilung = {hocos}, author = {Polian, Ilia and Anders, Jens and Becker, Stefan and Bernardi, Paolo and Chakrabarty, Krishnendu and Elhamawy, Nourhan and Sauer, Matthias and Singh, Adith and Sonza Reorda, Matteo and Wagner, Stefan}, booktitle = {to appear in Proceedings of the 29th IEEE Asian Test Symposium (ATS'20)}, month = nov, title = {Exploring the mysteries of system-level test.}, year = 2020 }
3. Hardware-based fast real-time image classification with stochastic computing. Ponana Kelettira Muthappa; Florian Neugebauer; Ilia Polian and John P. Hayes. In to appear in Proceedings of the 38th IEEE International Conference on Computer Design (ICCD’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{kelettiramuthappa2020hardwarebased, abteilung = {hocos}, author = {Kelettira Muthappa, Ponana and Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, booktitle = {to appear in Proceedings of the 38th IEEE International Conference on Computer Design (ICCD'20)}, month = oct, title = {Hardware-based fast real-time image classification with stochastic computing}, year = 2020 }
4. Side Channel Attacks vs Approximated Computing. Francesco Regazzoni and Ilia Polian. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), 2020, pp. 321–326. DOI: https://doi.org/10.1145/3386263.3407592
  - BibTeX
  BibTeX
  @inproceedings{regazzoni2020channel, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, booktitle = {Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI '20)}, doi = {10.1145/3386263.3407592}, month = sep, pages = {321-326}, title = {Side Channel Attacks vs Approximated Computing}, year = 2020 }
5. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
  - Abstract
  - BibTeX
  Abstract
  Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.
  BibTeX
  @inproceedings{9154942, abstract = {Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.}, abteilung = {hocos}, author = {{Oh}, Junseok and {Neugebauer}, Florian and {Polian}, Ilia and {Hayes}, John}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00052}, issn = {2159-3477}, month = {July}, pages = {246-251}, title = {Retraining and Regularization to Optimize Neural Networks for Stochastic Computing}, year = 2020 }
6. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
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  - BibTeX
  Abstract
  Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.
  BibTeX
  @inproceedings{9154961, abstract = {Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.}, abteilung = {hocos}, author = {Elhamawy, Nourhan and Gay, Mael and Polian, Ilia}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00031}, issn = {2159-3477}, month = {July}, pages = {120-125}, title = {An Open-Source Area-Optimized ECEG Cryptosystem in Hardware}, year = 2020 }
7. Error control scheme for malicious and natural faults in cryptographic modules. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (2020). DOI: https://doi.org/10.1007/s13389-020-00234-7
  - Abstract
  - BibTeX
  Abstract
  Today’s electronic systems must simultaneously fulfill strict requirements on security and reliability. In particular, their cryptographic modules are exposed to faults, which can be due to natural failures (e.g., radiation or electromagnetic noise) or malicious fault-injection attacks. We present an architecture based on a new class of error-detecting codes that combine robustness properties with a minimal distance. The new architecture guarantees (with some probability) the detection of faults injected by an intelligent and strategic adversary who can precisely control the disturbance. At the same time it supports automatic correction of low-multiplicity faults. To this end, we discuss an efficient technique to correct single nibble/byte errors while avoiding full syndrome analysis. We also examine a Compact Protection Code (CPC)-based system level fault manager that considers this code an inner code (and the CPC as its outer code). We report experimental results obtained by physical fault injection on the SAKURA-G FPGA board. The experimental results reconfirm the assumption that faults may cause an arbitrary number of bit flips. They indicate that a combined inner–outer coding scheme can significantly reduce the number of fault events that go undetected due to erroneous corrections of the inner code.
  BibTeX
  @article{gay2020error, abstract = {Today’s electronic systems must simultaneously fulfill strict requirements on security and reliability. In particular, their cryptographic modules are exposed to faults, which can be due to natural failures (e.g., radiation or electromagnetic noise) or malicious fault-injection attacks. We present an architecture based on a new class of error-detecting codes that combine robustness properties with a minimal distance. The new architecture guarantees (with some probability) the detection of faults injected by an intelligent and strategic adversary who can precisely control the disturbance. At the same time it supports automatic correction of low-multiplicity faults. To this end, we discuss an efficient technique to correct single nibble/byte errors while avoiding full syndrome analysis. We also examine a Compact Protection Code (CPC)-based system level fault manager that considers this code an inner code (and the CPC as its outer code). We report experimental results obtained by physical fault injection on the SAKURA-G FPGA board. The experimental results reconfirm the assumption that faults may cause an arbitrary number of bit flips. They indicate that a combined inner–outer coding scheme can significantly reduce the number of fault events that go undetected due to erroneous corrections of the inner code.}, abteilung = {hocos}, author = {Gay, Mael and Karp, Batya and Keren, Osnat and Polian, Ilia}, doi = {10.1007/s13389-020-00234-7}, issn = {2190-8516}, journal = {Journal of Cryptographic Engineering}, month = jun, title = {Error control scheme for malicious and natural faults in cryptographic modules}, volume = 10, year = 2020 }
8. IPM-RED: combining higher-order masking with robust error detection. Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (2020). DOI: https://doi.org/10.1007/s13389-020-00229-4
  - Abstract
  - BibTeX
  Abstract
  Cryptographic hardware becomes increasingly vulnerable to physical attacks--both passive side-channel analysis and active fault injections--performed by skillful and well-equipped adversaries. In this paper, we introduce a technique that provides very high security against both types of attacks. It combines inner product masking (IPM), which offers higher-order side-channel attack resistance on word level and on bit level, with nonlinear security-oriented error-detection codes that provide robustness, i.e., strong detection guarantees for arbitrary faults. We prove that our scheme has the same security against side-channel attacks that an earlier, non-robust IPM-based solution has and in addition preserves robustness during addition and multiplication (and therefore arbitrary computations). Moreover, we prove that the information leakage from the checker is small and that the attack will be detected far before the attacker will gain significant information.
  BibTeX
  @article{keren2020ipmred, abstract = {Cryptographic hardware becomes increasingly vulnerable to physical attacks--both passive side-channel analysis and active fault injections--performed by skillful and well-equipped adversaries. In this paper, we introduce a technique that provides very high security against both types of attacks. It combines inner product masking (IPM), which offers higher-order side-channel attack resistance on word level and on bit level, with nonlinear security-oriented error-detection codes that provide robustness, i.e., strong detection guarantees for arbitrary faults. We prove that our scheme has the same security against side-channel attacks that an earlier, non-robust IPM-based solution has and in addition preserves robustness during addition and multiplication (and therefore arbitrary computations). Moreover, we prove that the information leakage from the checker is small and that the attack will be detected far before the attacker will gain significant information.}, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, doi = {10.1007/s13389-020-00229-4}, issn = {2190-8516}, journal = {Journal of Cryptographic Engineering}, month = jun, title = {IPM-RED: combining higher-order masking with robust error detection.}, volume = 10, year = 2020 }
9. Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116525
  Abstract
  On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.
  BibTeX
  @inproceedings{BrandKW2020, abstract = {On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.}, abteilung = {hocos;ra}, address = {Grenoble, France}, author = {Brandhofer, Sebastian and Kochte, Michael A. and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20)}, day = {9--13}, doi = {10.23919/DATE48585.2020.9116525}, location = {Grenoble, France}, month = {March}, owner = {brandhsn}, pages = {1--6}, project = {ACCESS}, title = {{Synthesis of Fault-Tolerant Reconfigurable Scan Networks}}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2020/DATE_BrandKW2020.pdf}, year = 2020 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2020/DATE_BrandKW2020.pdf
10. Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont and Ilia Polian. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE), 2020, pp. 508–513. DOI: https://doi.org/10.23919/DATE48585.2020.9116483
  - Abstract
  - BibTeX
  Abstract
  Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.
  BibTeX
  @inproceedings{9116483, abstract = {Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.}, abteilung = {hocos}, author = {Knechtel, Johann and Kavun, Elif Bilge and Regazzoni, Francesco and Heuser, Annelie and Chattopadhyay, Anupam and Mukhopadhyay, Debdeep and Dey, Soumyajit and Fei, Yunsi and Belenky, Yaacov and Levi, Itamar and Güneysu, Tim and Schaumont, Patrick and Polian, Ilia}, booktitle = {2020 Design, Automation Test in Europe Conference Exhibition (DATE)}, doi = {10.23919/DATE48585.2020.9116483}, issn = {1558-1101}, month = {March}, pages = {508-513}, title = {Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA}, year = 2020 }
11. Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. Electronic Imaging 2020, 4 (2020), pp. 76-1-76–7. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
  Abstract
  Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an images visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.
  BibTeX
  @article{prasad2020detection, abstract = {Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an images visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.}, abteilung = {hocos}, author = {Prasad, Swaroop Shankar and Hadar, Ofer and Polian, Ilia}, doi = {10.2352/ISSN.2470-1173.2020.4.MWSF-076}, issn = {2470-1173}, journal = {Electronic Imaging}, month = jan, number = 4, pages = {76-1-76-7}, title = {Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks}, url = {https://www.ingentaconnect.com/content/ist/ei/2020/00002020/00000004/art00007}, volume = 2020, year = 2020 }
  Link
  https://www.ingentaconnect.com/content/ist/ei/2020/00002020/00000004/art00007
12. Information leakage from robust codes protecting cryptographic primitives. Osnat Keren and Ilia Polian. In Frontiers in Hardware Security and Trust: Theory, design and practice, C.H. Chang and Y Cao (eds.). The Institution of Engineering and Technology, 2020.
  - BibTeX
  BibTeX
  @inbook{keren2020information, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, booktitle = {Frontiers in Hardware Security and Trust: Theory, design and practice}, editor = {Chang, C.H. and Cao, Y}, isbn = {978-1-78561-927-4}, publisher = {The Institution of Engineering and Technology}, title = {Information leakage from robust codes protecting cryptographic primitives}, year = 2020 }
2019
1. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Mael Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019, pp. 25–32. DOI: https://doi.org/10.1109/FDTC.2019.00012
  - Abstract
  - BibTeX
  Abstract
  The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.
  BibTeX
  @inproceedings{8844472, abstract = {The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.}, abteilung = {hocos}, author = {Gay, Mael and Paxian, Tobias and Upadhyaya, Devanshi and Becker, Bernd and Polian, Ilia}, booktitle = {2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)}, doi = {10.1109/FDTC.2019.00012}, month = aug, pages = {25-32}, title = {Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support}, year = 2019 }
2. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
  Abstract
  Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.
  BibTeX
  @inbook{polian2019automatic, abstract = {Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.}, abteilung = {hocos}, address = {Cham}, author = {Polian, Ilia and Gay, Maël and Paxian, Tobias and Sauer, Matthias and Becker, Bernd}, booktitle = {Automated Methods in Cryptographic Fault Analysis}, chapter = 6, doi = {10.1007/978-3-030-11333-9_6}, editor = {Breier, Jakub and Hou, Xiaolu and Bhasin, Shivam}, isbn = {978-3-030-11332-2}, pages = {151-170}, publisher = {Springer International Publishing}, title = {Automatic construction of fault attacks on cryptographic hardware implementations}, url = {https://doi.org/10.1007/978-3-030-11333-9_6}, year = 2019 }
  Link
  https://doi.org/10.1007/978-3-030-11333-9_6
3. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian19, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2019-0008}, journal = {it - Information Technology}, number = 1, pages = {1--2}, title = {Hardware-oriented security}, url = {https://doi.org/10.1515/itit-2019-0008}, volume = 61, year = 2019 }
  Link
  https://doi.org/10.1515/itit-2019-0008
4. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
  - BibTeX
  - Link
  BibTeX
  @proceedings{DBLP:conf/cosade/2019, abteilung = {hocos}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/978-3-030-16350-1}, editor = {Polian, Ilia and St{\"{o}}ttinger, Marc}, isbn = {978-3-030-16349-5}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, title = {Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, {COSADE} 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings}, url = {https://doi.org/10.1007/978-3-030-16350-1}, volume = 11421, year = 2019 }
  Link
  https://doi.org/10.1007/978-3-030-16350-1
5. A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives. Osnat Keren and Ilia Polian. In Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019, pp. 49--63. DOI: https://doi.org/10.29007/r2sc
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  - Link
  BibTeX
  @inproceedings{PROOFS2019:comment_on_information_leakage, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia}, bibsource = {EasyChair, https://easychair.org}, booktitle = {Proceedings of 8th International Workshop on Security Proofs for Embedded Systems}, doi = {10.29007/r2sc}, editor = {Heydemann, Karine and K\textbackslash{}"uhne, Ulrich and Li, Letitia}, issn = {2515-1762}, pages = {49--63}, publisher = {EasyChair}, series = {Kalpa Publications in Computing}, title = {A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives}, url = {https://easychair.org/publications/paper/ZDvk}, volume = 11, year = 2019 }
  Link
  https://easychair.org/publications/paper/ZDvk
6. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cf/NeugebauerPH19, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 16th {ACM} International Conference on Computing Frontiers, {CF} 2019, Alghero, Italy, April 30 - May 2, 2019.}, crossref = {DBLP:conf/cf/2019}, doi = {10.1145/3310273.3323050}, pages = {59--66}, title = {On the maximum function in stochastic computing}, url = {https://doi.org/10.1145/3310273.3323050}, year = 2019 }
  Link
  https://doi.org/10.1145/3310273.3323050

Former HOCOS - Publications

2018
1. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/samos/RegazzoniFP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Fowler, Austin G. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018.}, crossref = {DBLP:conf/samos/2018}, doi = {10.1145/3229631.3264737}, pages = {173--178}, title = {Quantum era challenges for classical computers}, url = {https://doi.org/10.1145/3229631.3264737}, year = 2018 }
  Link
  https://doi.org/10.1145/3229631.3264737
2. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewme/PolianG18, abteilung = {hocos}, author = {Polian, Ilia and Gay, Mael}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th European Workshop on Microelectronics Education, {EWME} 2018, Braunschweig, Germany, September 24-26, 2018}, crossref = {DBLP:conf/ewme/2018}, doi = {10.1109/EWME.2018.8629483}, pages = {59--62}, title = {Hardware-oriented Security in a Computer Science Curriculum}, url = {https://doi.org/10.1109/EWME.2018.8629483}, year = 2018 }
  Link
  https://doi.org/10.1109/EWME.2018.8629483
3. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/esl/Polian18, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/LES.2017.2754446}, journal = {Embedded Systems Letters}, number = 1, pages = {26--29}, title = {Test and Reliability Challenges for Approximate Circuitry}, url = {https://doi.org/10.1109/LES.2017.2754446}, volume = 10, year = 2018 }
  Link
  https://doi.org/10.1109/LES.2017.2754446
4. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ches/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Ma{\"{e}}l and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{PROOFS} 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with {CHES} 2018, Amsterdam, The Netherlands, September 13, 2018}, crossref = {DBLP:conf/ches/2018proofs}, pages = {68--82}, title = {Detection and Correction of Malicious and Natural Faults in Cryptographic Modules}, url = {http://www.easychair.org/publications/paper/zMjh}, year = 2018 }
  Link
  http://www.easychair.org/publications/paper/zMjh
5. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/mam/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/j.micpro.2018.06.009}, journal = {Microprocessors and Microsystems - Embedded Hardware Design}, pages = {316--326}, title = {S-box-based random number generation for stochastic computing}, url = {https://doi.org/10.1016/j.micpro.2018.06.009}, volume = 61, year = 2018 }
  Link
  https://doi.org/10.1016/j.micpro.2018.06.009
6. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jetc/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/3183345}, journal = {{JETC}}, number = 2, pages = {31:1--31:21}, title = {Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design}, url = {https://doi.org/10.1145/3183345}, volume = 14, year = 2018 }
  Link
  https://doi.org/10.1145/3183345
7. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/RegazzoniAP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018}, crossref = {DBLP:conf/iccad/2018}, doi = {10.1145/3240765.3243497}, pages = 44, title = {Security: the dark side of approximate computing?}, url = {https://doi.org/10.1145/3240765.3243497}, year = 2018 }
  Link
  https://doi.org/10.1145/3240765.3243497
8. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dcis/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Mael and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Conference on Design of Circuits and Integrated Systems, {DCIS} 2018, Lyon, France, November 14-16, 2018}, crossref = {DBLP:conf/dcis/2018}, doi = {10.1109/DCIS.2018.8681476}, pages = {1--6}, title = {Security-oriented Code-based Architectures for Mitigating Fault Attacks}, url = {https://doi.org/10.1109/DCIS.2018.8681476}, year = 2018 }
  Link
  https://doi.org/10.1109/DCIS.2018.8681476
9. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/esl/Polian18, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/LES.2017.2754446}, journal = {Embedded Systems Letters}, number = 1, pages = {26--29}, title = {Test and Reliability Challenges for Approximate Circuitry}, url = {https://doi.org/10.1109/LES.2017.2754446}, volume = 10, year = 2018 }
  Link
  https://doi.org/10.1109/LES.2017.2754446
10. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/mam/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/j.micpro.2018.06.009}, journal = {Microprocessors and Microsystems - Embedded Hardware Design}, pages = {316--326}, title = {S-box-based random number generation for stochastic computing}, url = {https://doi.org/10.1016/j.micpro.2018.06.009}, volume = 61, year = 2018 }
  Link
  https://doi.org/10.1016/j.micpro.2018.06.009
11. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewme/PolianG18, abteilung = {hocos}, author = {Polian, Ilia and Gay, Mael}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th European Workshop on Microelectronics Education, {EWME} 2018, Braunschweig, Germany, September 24-26, 2018}, crossref = {DBLP:conf/ewme/2018}, doi = {10.1109/EWME.2018.8629483}, pages = {59--62}, title = {Hardware-oriented Security in a Computer Science Curriculum}, url = {https://doi.org/10.1109/EWME.2018.8629483}, year = 2018 }
  Link
  https://doi.org/10.1109/EWME.2018.8629483
12. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dcis/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Mael and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Conference on Design of Circuits and Integrated Systems, {DCIS} 2018, Lyon, France, November 14-16, 2018}, crossref = {DBLP:conf/dcis/2018}, doi = {10.1109/DCIS.2018.8681476}, pages = {1--6}, title = {Security-oriented Code-based Architectures for Mitigating Fault Attacks}, url = {https://doi.org/10.1109/DCIS.2018.8681476}, year = 2018 }
  Link
  https://doi.org/10.1109/DCIS.2018.8681476
13. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/samos/RegazzoniFP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Fowler, Austin G. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018.}, crossref = {DBLP:conf/samos/2018}, doi = {10.1145/3229631.3264737}, pages = {173--178}, title = {Quantum era challenges for classical computers}, url = {https://doi.org/10.1145/3229631.3264737}, year = 2018 }
  Link
  https://doi.org/10.1145/3229631.3264737
14. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ches/KarpGKP18, abteilung = {hocos}, author = {Karp, Batya and Gay, Ma{\"{e}}l and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{PROOFS} 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with {CHES} 2018, Amsterdam, The Netherlands, September 13, 2018}, crossref = {DBLP:conf/ches/2018proofs}, pages = {68--82}, title = {Detection and Correction of Malicious and Natural Faults in Cryptographic Modules}, url = {http://www.easychair.org/publications/paper/zMjh}, year = 2018 }
  Link
  http://www.easychair.org/publications/paper/zMjh
15. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jetc/NeugebauerPH18, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/3183345}, journal = {{JETC}}, number = 2, pages = {31:1--31:21}, title = {Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design}, url = {https://doi.org/10.1145/3183345}, volume = 14, year = 2018 }
  Link
  https://doi.org/10.1145/3183345
16. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/RegazzoniAP18, abteilung = {hocos}, author = {Regazzoni, Francesco and Alippi, Cesare and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the International Conference on Computer-Aided Design, {ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018}, crossref = {DBLP:conf/iccad/2018}, doi = {10.1145/3240765.3243497}, pages = 44, title = {Security: the dark side of approximate computing?}, url = {https://doi.org/10.1145/3240765.3243497}, year = 2018 }
  Link
  https://doi.org/10.1145/3240765.3243497
2017
1. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/socc/PolianRS17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco and Sep{\'{u}}lveda, Johanna}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017, Munich, Germany, September 5-8, 2017}, crossref = {DBLP:conf/socc/2017}, doi = {10.1109/SOCC.2017.8226017}, pages = {102--107}, title = {Introduction to hardware-oriented security for MPSoCs}, url = {https://doi.org/10.1109/SOCC.2017.8226017}, year = 2017 }
  Link
  https://doi.org/10.1109/SOCC.2017.8226017
2. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ivsw/BurchardEHG0SKP17, abteilung = {hocos}, author = {Burchard, Jan and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Gay, Mael and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} 2nd International Verification and Security Workshop, {IVSW} 2017, Thessaloniki, Greece, July 3-5, 2017}, crossref = {DBLP:conf/ivsw/2017}, doi = {10.1109/IVSW.2017.8031537}, pages = {7--12}, title = {Towards mixed structural-functional models for algebraic fault attacks on ciphers}, url = {https://doi.org/10.1109/IVSW.2017.8031537}, year = 2017 }
  Link
  https://doi.org/10.1109/IVSW.2017.8031537
3. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRF0RP17, abteilung = {hocos}, author = {Sauer, Matthias and Raiola, Pascal and Feiten, Linus and Becker, Bernd and R{\"{u}}hrmair, Ulrich and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927076}, pages = {680--685}, title = {Sensitized path {PUF:} {A} lightweight embedded physical unclonable function}, url = {https://doi.org/10.23919/DATE.2017.7927076}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927076
4. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7926949}, pages = {1--6}, title = {Framework for quantifying and managing accuracy in stochastic circuit design}, url = {https://doi.org/10.23919/DATE.2017.7926949}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7926949
5. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/BurchardGEH00KP17, abteilung = {hocos}, author = {Burchard, Jan and Gay, Mael and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2017, Taipei, Taiwan, September 25, 2017}, crossref = {DBLP:conf/fdtc/2017}, doi = {10.1109/FDTC.2017.13}, pages = {65--72}, title = {AutoFault: Towards Automatic Construction of Algebraic Fault Attacks}, url = {https://doi.org/10.1109/FDTC.2017.13}, year = 2017 }
  Link
  https://doi.org/10.1109/FDTC.2017.13
6. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/RegazzoniP17, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC} 2017, Chiba, Japan, January 16-19, 2017}, crossref = {DBLP:conf/aspdac/2017}, doi = {10.1109/ASPDAC.2017.7858319}, pages = {194--199}, title = {Securing the hardware of cyber-physical systems}, url = {https://doi.org/10.1109/ASPDAC.2017.7858319}, year = 2017 }
  Link
  https://doi.org/10.1109/ASPDAC.2017.7858319
7. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsd/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Euromicro Conference on Digital System Design, {DSD} 2017, Vienna, Austria, August 30 - Sept. 1, 2017}, crossref = {DBLP:conf/dsd/2017}, doi = {10.1109/DSD.2017.29}, pages = {1--8}, title = {Building a Better Random Number Generator for Stochastic Computing}, url = {https://doi.org/10.1109/DSD.2017.29}, year = 2017 }
  Link
  https://doi.org/10.1109/DSD.2017.29
8. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianR17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus, May 22-26, 2017}, crossref = {DBLP:conf/ets/2017}, doi = {10.1109/ETS.2017.7968230}, pages = {1--10}, title = {Counteracting malicious faults in cryptographic circuits}, url = {https://doi.org/10.1109/ETS.2017.7968230}, year = 2017 }
  Link
  https://doi.org/10.1109/ETS.2017.7968230
9. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherHP17, abteilung = {hocos}, author = {Kinseher, Josef and Heis, Leonhard and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927106}, pages = {852--857}, title = {Analyzing the effects of peripheral circuit aging of embedded {SRAM} architectures}, url = {https://doi.org/10.23919/DATE.2017.7927106}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927106
10. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherHP17, abteilung = {hocos}, author = {Kinseher, Josef and Heis, Leonhard and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927106}, pages = {852--857}, title = {Analyzing the effects of peripheral circuit aging of embedded {SRAM} architectures}, url = {https://doi.org/10.23919/DATE.2017.7927106}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927106
11. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/BurchardGEH00KP17, abteilung = {hocos}, author = {Burchard, Jan and Gay, Mael and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2017, Taipei, Taiwan, September 25, 2017}, crossref = {DBLP:conf/fdtc/2017}, doi = {10.1109/FDTC.2017.13}, pages = {65--72}, title = {AutoFault: Towards Automatic Construction of Algebraic Fault Attacks}, url = {https://doi.org/10.1109/FDTC.2017.13}, year = 2017 }
  Link
  https://doi.org/10.1109/FDTC.2017.13
12. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7926949}, pages = {1--6}, title = {Framework for quantifying and managing accuracy in stochastic circuit design}, url = {https://doi.org/10.23919/DATE.2017.7926949}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7926949
13. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianR17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus, May 22-26, 2017}, crossref = {DBLP:conf/ets/2017}, doi = {10.1109/ETS.2017.7968230}, pages = {1--10}, title = {Counteracting malicious faults in cryptographic circuits}, url = {https://doi.org/10.1109/ETS.2017.7968230}, year = 2017 }
  Link
  https://doi.org/10.1109/ETS.2017.7968230
14. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsd/NeugebauerPH17, abteilung = {hocos}, author = {Neugebauer, Florian and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Euromicro Conference on Digital System Design, {DSD} 2017, Vienna, Austria, August 30 - Sept. 1, 2017}, crossref = {DBLP:conf/dsd/2017}, doi = {10.1109/DSD.2017.29}, pages = {1--8}, title = {Building a Better Random Number Generator for Stochastic Computing}, url = {https://doi.org/10.1109/DSD.2017.29}, year = 2017 }
  Link
  https://doi.org/10.1109/DSD.2017.29
15. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/socc/PolianRS17, abteilung = {hocos}, author = {Polian, Ilia and Regazzoni, Francesco and Sep{\'{u}}lveda, Johanna}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017, Munich, Germany, September 5-8, 2017}, crossref = {DBLP:conf/socc/2017}, doi = {10.1109/SOCC.2017.8226017}, pages = {102--107}, title = {Introduction to hardware-oriented security for MPSoCs}, url = {https://doi.org/10.1109/SOCC.2017.8226017}, year = 2017 }
  Link
  https://doi.org/10.1109/SOCC.2017.8226017
16. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRF0RP17, abteilung = {hocos}, author = {Sauer, Matthias and Raiola, Pascal and Feiten, Linus and Becker, Bernd and R{\"{u}}hrmair, Ulrich and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2017, Lausanne, Switzerland, March 27-31, 2017}, crossref = {DBLP:conf/date/2017}, doi = {10.23919/DATE.2017.7927076}, pages = {680--685}, title = {Sensitized path {PUF:} {A} lightweight embedded physical unclonable function}, url = {https://doi.org/10.23919/DATE.2017.7927076}, year = 2017 }
  Link
  https://doi.org/10.23919/DATE.2017.7927076
17. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/RegazzoniP17, abteilung = {hocos}, author = {Regazzoni, Francesco and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC} 2017, Chiba, Japan, January 16-19, 2017}, crossref = {DBLP:conf/aspdac/2017}, doi = {10.1109/ASPDAC.2017.7858319}, pages = {194--199}, title = {Securing the hardware of cyber-physical systems}, url = {https://doi.org/10.1109/ASPDAC.2017.7858319}, year = 2017 }
  Link
  https://doi.org/10.1109/ASPDAC.2017.7858319
18. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ivsw/BurchardEHG0SKP17, abteilung = {hocos}, author = {Burchard, Jan and Ekossono, Ange Salome Messeng and Hor{\'{a}}cek, Jan and Gay, Mael and Becker, Bernd and Schubert, Tobias and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} 2nd International Verification and Security Workshop, {IVSW} 2017, Thessaloniki, Greece, July 3-5, 2017}, crossref = {DBLP:conf/ivsw/2017}, doi = {10.1109/IVSW.2017.8031537}, pages = {7--12}, title = {Towards mixed structural-functional models for algebraic fault attacks on ciphers}, url = {https://doi.org/10.1109/IVSW.2017.8031537}, year = 2017 }
  Link
  https://doi.org/10.1109/IVSW.2017.8031537
2016
1. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/eusipco/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th European Signal Processing Conference, {EUSIPCO} 2016, Budapest, Hungary, August 29 - September 2, 2016}, crossref = {DBLP:conf/eusipco/2016}, doi = {10.1109/EUSIPCO.2016.7760523}, pages = {1623--1627}, title = {Memory error resilient detection for massive {MIMO} systems}, url = {https://doi.org/10.1109/EUSIPCO.2016.7760523}, year = 2016 }
  Link
  https://doi.org/10.1109/EUSIPCO.2016.7760523
2. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dagstuhl-reports/KerenPT16, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.4230/DagRep.6.5.72}, journal = {Dagstuhl Reports}, number = 5, pages = {72--93}, title = {Hardware Security (Dagstuhl Seminar 16202)}, url = {https://doi.org/10.4230/DagRep.6.5.72}, volume = 6, year = 2016 }
  Link
  https://doi.org/10.4230/DagRep.6.5.72
3. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherZPL16, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia and Leininger, Andreas}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, crossref = {DBLP:conf/date/2016}, pages = {984--989}, title = {Improving {SRAM} test quality by leveraging self-timed circuits}, url = {http://ieeexplore.ieee.org/document/7459450/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7459450/
4. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJRMWBP16, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Reimer, Sven and Miyase, Kohei and Wen, Xiaoqing and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November 21-24, 2016}, crossref = {DBLP:conf/ats/2016}, doi = {10.1109/ATS.2016.63}, pages = {179--184}, title = {On Optimal Power-Aware Path Sensitization}, url = {https://doi.org/10.1109/ATS.2016.63}, year = 2016 }
  Link
  https://doi.org/10.1109/ATS.2016.63
5. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tc/SauerBP16, abteilung = {hocos}, author = {Sauer, Matthias and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TC.2015.2458869}, journal = {{IEEE} Trans. Computers}, number = 6, pages = {1869--1881}, title = {{PHAETON:} {A} SAT-Based Framework for Timing-Aware Path Sensitization}, url = {https://doi.org/10.1109/TC.2015.2458869}, volume = 65, year = 2016 }
  Link
  https://doi.org/10.1109/TC.2015.2458869
6. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/KinseherVZP16, abteilung = {hocos}, author = {Kinseher, Josef and V{\"{o}}lker, Moritz and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands, May 23-27, 2016}, crossref = {DBLP:conf/ets/2016}, doi = {10.1109/ETS.2016.7519324}, pages = {1--2}, title = {Failure mechanisms and test methods for the {SRAM} {TVC} write-assist technique}, url = {https://doi.org/10.1109/ETS.2016.7519324}, year = 2016 }
  Link
  https://doi.org/10.1109/ETS.2016.7519324
7. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wsa/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{WSA} 2016, 20th International {ITG} Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016.}, crossref = {DBLP:conf/wsa/2016}, pages = {1--8}, title = {Detection Performance of {MIMO} Unique Word {OFDM}}, url = {http://ieeexplore.ieee.org/document/7499144/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7499144/
8. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tc/SauerBP16, abteilung = {hocos}, author = {Sauer, Matthias and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TC.2015.2458869}, journal = {{IEEE} Trans. Computers}, number = 6, pages = {1869--1881}, title = {{PHAETON:} {A} SAT-Based Framework for Timing-Aware Path Sensitization}, url = {https://doi.org/10.1109/TC.2015.2458869}, volume = 65, year = 2016 }
  Link
  https://doi.org/10.1109/TC.2015.2458869
9. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wsa/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{WSA} 2016, 20th International {ITG} Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016.}, crossref = {DBLP:conf/wsa/2016}, pages = {1--8}, title = {Detection Performance of {MIMO} Unique Word {OFDM}}, url = {http://ieeexplore.ieee.org/document/7499144/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7499144/
10. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KinseherZPL16, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia and Leininger, Andreas}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016}, crossref = {DBLP:conf/date/2016}, pages = {984--989}, title = {Improving {SRAM} test quality by leveraging self-timed circuits}, url = {http://ieeexplore.ieee.org/document/7459450/}, year = 2016 }
  Link
  http://ieeexplore.ieee.org/document/7459450/
11. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dagstuhl-reports/KerenPT16, abteilung = {hocos}, author = {Keren, Osnat and Polian, Ilia and Tehranipoor, Mark M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.4230/DagRep.6.5.72}, journal = {Dagstuhl Reports}, number = 5, pages = {72--93}, title = {Hardware Security (Dagstuhl Seminar 16202)}, url = {https://doi.org/10.4230/DagRep.6.5.72}, volume = 6, year = 2016 }
  Link
  https://doi.org/10.4230/DagRep.6.5.72
12. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJRMWBP16, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Reimer, Sven and Miyase, Kohei and Wen, Xiaoqing and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November 21-24, 2016}, crossref = {DBLP:conf/ats/2016}, doi = {10.1109/ATS.2016.63}, pages = {179--184}, title = {On Optimal Power-Aware Path Sensitization}, url = {https://doi.org/10.1109/ATS.2016.63}, year = 2016 }
  Link
  https://doi.org/10.1109/ATS.2016.63
13. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/eusipco/TomashevichP16, abteilung = {hocos}, author = {Tomashevich, Victor and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th European Signal Processing Conference, {EUSIPCO} 2016, Budapest, Hungary, August 29 - September 2, 2016}, crossref = {DBLP:conf/eusipco/2016}, doi = {10.1109/EUSIPCO.2016.7760523}, pages = {1623--1627}, title = {Memory error resilient detection for massive {MIMO} systems}, url = {https://doi.org/10.1109/EUSIPCO.2016.7760523}, year = 2016 }
  Link
  https://doi.org/10.1109/EUSIPCO.2016.7760523
14. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/KinseherVZP16, abteilung = {hocos}, author = {Kinseher, Josef and V{\"{o}}lker, Moritz and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands, May 23-27, 2016}, crossref = {DBLP:conf/ets/2016}, doi = {10.1109/ETS.2016.7519324}, pages = {1--2}, title = {Failure mechanisms and test methods for the {SRAM} {TVC} write-assist technique}, url = {https://doi.org/10.1109/ETS.2016.7519324}, year = 2016 }
  Link
  https://doi.org/10.1109/ETS.2016.7519324
2015
1. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KinseherZP15, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November 22-25, 2015}, crossref = {DBLP:conf/ats/2015}, doi = {10.1109/ATS.2015.18}, pages = {61--66}, title = {On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs}, url = {https://doi.org/10.1109/ATS.2015.18}, year = 2015 }
  Link
  https://doi.org/10.1109/ATS.2015.18
2. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dac/PolianF15, abteilung = {hocos}, author = {Polian, Ilia and Fowler, Austin G.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015}, crossref = {DBLP:conf/dac/2015}, doi = {10.1145/2744769.2747921}, pages = {61:1--61:6}, title = {Design automation challenges for scalable quantum architectures}, url = {https://doi.org/10.1145/2744769.2747921}, year = 2015 }
  Link
  https://doi.org/10.1145/2744769.2747921
3. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JovanovicP15, abteilung = {hocos}, author = {Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, crossref = {DBLP:conf/date/2015}, pages = {601--604}, title = {Fault-based attacks on the Bel-T block cipher family}, url = {http://dl.acm.org/citation.cfm?id=2755889}, year = 2015 }
  Link
  http://dl.acm.org/citation.cfm?id=2755889
4. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/FeitenSSTPB15, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Tomashevich, Victor and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2015.2448687}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 8, pages = {1358--1369}, title = {Formal Vulnerability Analysis of Security Components}, url = {https://doi.org/10.1109/TCAD.2015.2448687}, volume = 34, year = 2015 }
  Link
  https://doi.org/10.1109/TCAD.2015.2448687
5. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerPND15, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Nemoto, Kae and Devitt, Simon J.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,Grenoble, France, July 16-17, 2015, Proceedings}, crossref = {DBLP:conf/rc/2015}, doi = {10.1007/978-3-319-20860-2_9}, pages = {139--154}, title = {A Fully Fault-Tolerant Representation of Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-20860-2_9}, year = 2015 }
  Link
  https://doi.org/10.1007/978-3-319-20860-2_9
6. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerPND15, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Nemoto, Kae and Devitt, Simon J.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,Grenoble, France, July 16-17, 2015, Proceedings}, crossref = {DBLP:conf/rc/2015}, doi = {10.1007/978-3-319-20860-2_9}, pages = {139--154}, title = {A Fully Fault-Tolerant Representation of Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-20860-2_9}, year = 2015 }
  Link
  https://doi.org/10.1007/978-3-319-20860-2_9
7. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KinseherZP15, abteilung = {hocos}, author = {Kinseher, Josef and Zordan, Leonardo Bonet and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November 22-25, 2015}, crossref = {DBLP:conf/ats/2015}, doi = {10.1109/ATS.2015.18}, pages = {61--66}, title = {On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs}, url = {https://doi.org/10.1109/ATS.2015.18}, year = 2015 }
  Link
  https://doi.org/10.1109/ATS.2015.18
8. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dac/PolianF15, abteilung = {hocos}, author = {Polian, Ilia and Fowler, Austin G.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015}, crossref = {DBLP:conf/dac/2015}, doi = {10.1145/2744769.2747921}, pages = {61:1--61:6}, title = {Design automation challenges for scalable quantum architectures}, url = {https://doi.org/10.1145/2744769.2747921}, year = 2015 }
  Link
  https://doi.org/10.1145/2744769.2747921
9. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/FeitenSSTPB15, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Tomashevich, Victor and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2015.2448687}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 8, pages = {1358--1369}, title = {Formal Vulnerability Analysis of Security Components}, url = {https://doi.org/10.1109/TCAD.2015.2448687}, volume = 34, year = 2015 }
  Link
  https://doi.org/10.1109/TCAD.2015.2448687
10. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JovanovicP15, abteilung = {hocos}, author = {Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, crossref = {DBLP:conf/date/2015}, pages = {601--604}, title = {Fault-based attacks on the Bel-T block cipher family}, url = {http://dl.acm.org/citation.cfm?id=2755889}, year = 2015 }
  Link
  http://dl.acm.org/citation.cfm?id=2755889
2014
1. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 783, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {http://eprint.iacr.org/2014/783}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/783
2. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/UppuUSP14, abteilung = {hocos}, author = {Uppu, Ravi Kanth and Uppu, Ravi Tej and Singh, Adit D. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.30}, pages = {133--138}, title = {Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths}, url = {https://doi.org/10.1109/VLSID.2014.30}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.30
3. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerPIMSCWB14, abteilung = {hocos}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans{-}Joachim and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847806}, pages = {1--6}, title = {Variation-aware deterministic {ATPG}}, url = {https://doi.org/10.1109/ETS.2014.6847806}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847806
4. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian14, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2013-1038}, journal = {it - Information Technology}, number = 4, pages = {192--202}, title = {Hardware security and test: Friends or enemies?}, url = {https://doi.org/10.1515/itit-2013-1038}, volume = 56, year = 2014 }
  Link
  https://doi.org/10.1515/itit-2013-1038
5. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2014, Busan, South Korea, September 23, 2014}, crossref = {DBLP:conf/fdtc/2014}, doi = {10.1109/FDTC.2014.12}, pages = {18--28}, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {https://doi.org/10.1109/FDTC.2014.12}, year = 2014 }
  Link
  https://doi.org/10.1109/FDTC.2014.12
6. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iet-cdt/PolianT14, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mark Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1049/iet-cdt.2014.0194}, journal = {{IET} Computers {\&} Digital Techniques}, number = 6, pages = {237--238}, title = {Guest Editorial}, url = {https://doi.org/10.1049/iet-cdt.2014.0194}, volume = 8, year = 2014 }
  Link
  https://doi.org/10.1049/iet-cdt.2014.0194
7. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,Kyoto, Japan, July 10-11, 2014. Proceedings}, crossref = {DBLP:conf/rc/2014}, doi = {10.1007/978-3-319-08494-7_15}, pages = {189--200}, title = {Cross-Level Validation of Topological Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-08494-7_15}, year = 2014 }
  Link
  https://doi.org/10.1007/978-3-319-08494-7_15
8. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wisee/TomashevichGWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014}, crossref = {DBLP:conf/wisee/2014}, doi = {10.1109/WiSEE.2014.6973066}, pages = {1--6}, title = {Reliability analysis of {MIMO} channel preprocessing by fault injection}, url = {https://doi.org/10.1109/WiSEE.2014.6973066}, year = 2014 }
  Link
  https://doi.org/10.1109/WiSEE.2014.6973066
9. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS} 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014}, crossref = {DBLP:conf/iolts/2014}, doi = {10.1109/IOLTS.2014.6873670}, pages = {43--48}, title = {Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis}, url = {https://doi.org/10.1109/IOLTS.2014.6873670}, year = 2014 }
  Link
  https://doi.org/10.1109/IOLTS.2014.6873670
10. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroRPB14, abteilung = {hocos}, author = {Czutro, Alexander and Reddy, Sudhakar M. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.17}, pages = {56--61}, title = {SAT-Based Test Pattern Generation with Improved Dynamic Compaction}, url = {https://doi.org/10.1109/VLSID.2014.17}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.17
11. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/TomashevichNKKP14, abteilung = {hocos}, author = {Tomashevich, Victor and Neumeier, Yaara and Kumar, Raghavan and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2014, Amsterdam, The Netherlands, October 1-3, 2014}, crossref = {DBLP:conf/dft/2014}, doi = {10.1109/DFT.2014.6962084}, pages = {40--45}, title = {Protecting cryptographic hardware against malicious attacks by nonlinear robust codes}, url = {https://doi.org/10.1109/DFT.2014.6962084}, year = 2014 }
  Link
  https://doi.org/10.1109/DFT.2014.6962084
12. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
  - BibTeX
  - Link
  BibTeX
  @book{StephGI2014, abteilung = {hocos}, address = {Berlin, Boston}, author = {Eggersglüß, Stephan and Fey, Görschwin and Polian, Ilia}, issn = {978-3-486-99073-7}, language = {DT}, owner = {haefneht}, publisher = {De Gruyter Oldenbourg}, title = {Test digitaler Schaltkreise}, url = {https://www.degruyter.com/view/product/214529}, year = 2014 }
  Link
  https://www.degruyter.com/view/product/214529
13. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/TomashevichGFWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Fesl, Christian and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April, 2014}, crossref = {DBLP:conf/ddecs/2014}, doi = {10.1109/DDECS.2014.6868800}, pages = {246--249}, title = {A new architecture for minimum mean square error sorted {QR} decomposition for {MIMO} wireless communication systems}, url = {https://doi.org/10.1109/DDECS.2014.6868800}, year = 2014 }
  Link
  https://doi.org/10.1109/DDECS.2014.6868800
14. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2014, Dresden, Germany, March 24-28, 2014}, crossref = {DBLP:conf/date/2014}, doi = {10.7873/DATE.2014.137}, pages = {1--4}, title = {Software-based Pauli tracking in fault-tolerant quantum circuits}, url = {https://doi.org/10.7873/DATE.2014.137}, year = 2014 }
  Link
  https://doi.org/10.7873/DATE.2014.137
15. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 782, title = {Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis}, url = {http://eprint.iacr.org/2014/782}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/782
16. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianJS14, abteilung = {hocos}, author = {Polian, Ilia and Jiang, Jie and Singh, Adit D.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847794}, pages = {1--6}, title = {Detection conditions for errors in self-adaptive better-than-worst-case designs}, url = {https://doi.org/10.1109/ETS.2014.6847794}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847794
17. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
  - BibTeX
  - Link
  BibTeX
  @book{StephGI2014, abteilung = {hocos}, address = {Berlin, Boston}, author = {Eggersglüß, Stephan and Fey, Görschwin and Polian, Ilia}, issn = {978-3-486-99073-7}, language = {DT}, owner = {haefneht}, publisher = {De Gruyter Oldenbourg}, title = {Test digitaler Schaltkreise}, url = {https://www.degruyter.com/view/product/214529}, year = 2014 }
  Link
  https://www.degruyter.com/view/product/214529
18. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 783, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {http://eprint.iacr.org/2014/783}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/783
19. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianJS14, abteilung = {hocos}, author = {Polian, Ilia and Jiang, Jie and Singh, Adit D.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847794}, pages = {1--6}, title = {Detection conditions for errors in self-adaptive better-than-worst-case designs}, url = {https://doi.org/10.1109/ETS.2014.6847794}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847794
20. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2014, Dresden, Germany, March 24-28, 2014}, crossref = {DBLP:conf/date/2014}, doi = {10.7873/DATE.2014.137}, pages = {1--4}, title = {Software-based Pauli tracking in fault-tolerant quantum circuits}, url = {https://doi.org/10.7873/DATE.2014.137}, year = 2014 }
  Link
  https://doi.org/10.7873/DATE.2014.137
21. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/rc/PalerDNP14, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,Kyoto, Japan, July 10-11, 2014. Proceedings}, crossref = {DBLP:conf/rc/2014}, doi = {10.1007/978-3-319-08494-7_15}, pages = {189--200}, title = {Cross-Level Validation of Topological Quantum Circuits}, url = {https://doi.org/10.1007/978-3-319-08494-7_15}, year = 2014 }
  Link
  https://doi.org/10.1007/978-3-319-08494-7_15
22. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wisee/TomashevichGWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014}, crossref = {DBLP:conf/wisee/2014}, doi = {10.1109/WiSEE.2014.6973066}, pages = {1--6}, title = {Reliability analysis of {MIMO} channel preprocessing by fault injection}, url = {https://doi.org/10.1109/WiSEE.2014.6973066}, year = 2014 }
  Link
  https://doi.org/10.1109/WiSEE.2014.6973066
23. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 782, title = {Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis}, url = {http://eprint.iacr.org/2014/782}, volume = 2014, year = 2014 }
  Link
  http://eprint.iacr.org/2014/782
24. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroRPB14, abteilung = {hocos}, author = {Czutro, Alexander and Reddy, Sudhakar M. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.17}, pages = {56--61}, title = {SAT-Based Test Pattern Generation with Improved Dynamic Compaction}, url = {https://doi.org/10.1109/VLSID.2014.17}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.17
25. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/TomashevichNKKP14, abteilung = {hocos}, author = {Tomashevich, Victor and Neumeier, Yaara and Kumar, Raghavan and Keren, Osnat and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2014, Amsterdam, The Netherlands, October 1-3, 2014}, crossref = {DBLP:conf/dft/2014}, doi = {10.1109/DFT.2014.6962084}, pages = {40--45}, title = {Protecting cryptographic hardware against malicious attacks by nonlinear robust codes}, url = {https://doi.org/10.1109/DFT.2014.6962084}, year = 2014 }
  Link
  https://doi.org/10.1109/DFT.2014.6962084
26. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/TomashevichGFWP14, abteilung = {hocos}, author = {Tomashevich, Victor and Gimmler{-}Dumont, Christina and Fesl, Christian and Wehn, Norbert and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April, 2014}, crossref = {DBLP:conf/ddecs/2014}, doi = {10.1109/DDECS.2014.6868800}, pages = {246--249}, title = {A new architecture for minimum mean square error sorted {QR} decomposition for {MIMO} wireless communication systems}, url = {https://doi.org/10.1109/DDECS.2014.6868800}, year = 2014 }
  Link
  https://doi.org/10.1109/DDECS.2014.6868800
27. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/UppuUSP14, abteilung = {hocos}, author = {Uppu, Ravi Kanth and Uppu, Ravi Tej and Singh, Adit D. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 27th International Conference on {VLSI} Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014}, crossref = {DBLP:conf/vlsid/2014}, doi = {10.1109/VLSID.2014.30}, pages = {133--138}, title = {Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths}, url = {https://doi.org/10.1109/VLSID.2014.30}, year = 2014 }
  Link
  https://doi.org/10.1109/VLSID.2014.30
28. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iet-cdt/PolianT14, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mark Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1049/iet-cdt.2014.0194}, journal = {{IET} Computers {\&} Digital Techniques}, number = 6, pages = {237--238}, title = {Guest Editorial}, url = {https://doi.org/10.1049/iet-cdt.2014.0194}, volume = 8, year = 2014 }
  Link
  https://doi.org/10.1049/iet-cdt.2014.0194
29. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian14, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1515/itit-2013-1038}, journal = {it - Information Technology}, number = 4, pages = {192--202}, title = {Hardware security and test: Friends or enemies?}, url = {https://doi.org/10.1515/itit-2013-1038}, volume = 56, year = 2014 }
  Link
  https://doi.org/10.1515/itit-2013-1038
30. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerPIMSCWB14, abteilung = {hocos}, author = {Sauer, Matthias and Polian, Ilia and Imhof, Michael E. and Mumtaz, Abdullah and Schneider, Eric and Czutro, Alexander and Wunderlich, Hans{-}Joachim and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany, May 26-30, 2014}, crossref = {DBLP:conf/ets/2014}, doi = {10.1109/ETS.2014.6847806}, pages = {1--6}, title = {Variation-aware deterministic {ATPG}}, url = {https://doi.org/10.1109/ETS.2014.6847806}, year = 2014 }
  Link
  https://doi.org/10.1109/ETS.2014.6847806
31. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/fdtc/KumarJBP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Burleson, Wayne P. and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, {FDTC} 2014, Busan, South Korea, September 23, 2014}, crossref = {DBLP:conf/fdtc/2014}, doi = {10.1109/FDTC.2014.12}, pages = {18--28}, title = {Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware}, url = {https://doi.org/10.1109/FDTC.2014.12}, year = 2014 }
  Link
  https://doi.org/10.1109/FDTC.2014.12
32. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KumarJP14, abteilung = {hocos}, author = {Kumar, Raghavan and Jovanovic, Philipp and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS} 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014}, crossref = {DBLP:conf/iolts/2014}, doi = {10.1109/IOLTS.2014.6873670}, pages = {43--48}, title = {Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis}, url = {https://doi.org/10.1109/IOLTS.2014.6873670}, year = 2014 }
  Link
  https://doi.org/10.1109/IOLTS.2014.6873670
2013
1. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Aza; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/JiangACARP13, abteilung = {hocos}, author = {Jiang, J. and Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asian Test Symposium, {ATS} 2013, Yilan County, Taiwan, November 18-21, 2013}, crossref = {DBLP:conf/ats/2013}, doi = {10.1109/ATS.2013.41}, pages = {177--182}, title = {{MIRID:} Mixed-Mode IR-Drop Induced Delay Simulator}, url = {https://doi.org/10.1109/ATS.2013.41}, year = 2013 }
  Link
  https://doi.org/10.1109/ATS.2013.41
2. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianK13, abteilung = {hocos}, author = {Polian, Ilia and Kreuzer, Martin}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2013, Karlovy Vary, Czech Republic, April 8-10, 2013}, crossref = {DBLP:conf/ddecs/2013}, doi = {10.1109/DDECS.2013.6549781}, pages = {12--17}, title = {Fault-based attacks on cryptographic hardware}, url = {https://doi.org/10.1109/DDECS.2013.6549781}, year = 2013 }
  Link
  https://doi.org/10.1109/DDECS.2013.6549781
3. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/SauerCSHPB13, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2012.2230297}, journal = {{IEEE} Design {\&} Test}, number = 4, pages = {81--88}, title = {SAT-Based Analysis of Sensitizable Paths}, url = {https://doi.org/10.1109/MDT.2012.2230297}, volume = 30, year = 2013 }
  Link
  https://doi.org/10.1109/MDT.2012.2230297
4. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianT13, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA, April 29 - May 2, 2013}, crossref = {DBLP:conf/vts/2013}, doi = {10.1109/VTS.2013.6548944}, pages = 1, title = {Special session 12A: Hot topic counterfeit {IC} identification: How can test help?}, url = {https://doi.org/10.1109/VTS.2013.6548944}, year = 2013 }
  Link
  https://doi.org/10.1109/VTS.2013.6548944
5. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Aza; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/latw/AparicioCARJPB13, abteilung = {hocos}, author = {Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Jiang, J. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina, 3-5 April, 2013}, crossref = {DBLP:conf/latw/2013}, doi = {10.1109/LATW.2013.6562657}, pages = {1--6}, title = {Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays}, url = {https://doi.org/10.1109/LATW.2013.6562657}, year = 2013 }
  Link
  https://doi.org/10.1109/LATW.2013.6562657
6. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PalerKPH13, abteilung = {hocos}, author = {Paler, Alexandru and Kinseher, Josef and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2013 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City, NY, USA, October 2-4, 2013}, crossref = {DBLP:conf/dft/2013}, doi = {10.1109/DFT.2013.6653589}, pages = {95--100}, title = {Approximate simulation of circuits with probabilistic behavior}, url = {https://doi.org/10.1109/DFT.2013.6653589}, year = 2013 }
  Link
  https://doi.org/10.1109/DFT.2013.6653589
7. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRSPB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France, March 18-22, 2013}, crossref = {DBLP:conf/date/2013}, doi = {10.7873/DATE.2013.100}, pages = {448--453}, title = {Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths}, url = {https://doi.org/10.7873/DATE.2013.100}, year = 2013 }
  Link
  https://doi.org/10.7873/DATE.2013.100
8. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/SauerRPSB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Polian, Ilia and Schubert, Tobias and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2013, Yokohama, Japan, January 22-25, 2013}, crossref = {DBLP:conf/aspdac/2013}, doi = {10.1109/ASPDAC.2013.6509651}, pages = {533--539}, title = {Provably optimal test cube generation using quantified boolean formula solving}, url = {https://doi.org/10.1109/ASPDAC.2013.6509651}, year = 2013 }
  Link
  https://doi.org/10.1109/ASPDAC.2013.6509651
9. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP13, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 778, title = {Multi-Stage Fault Attacks on Block Ciphers}, url = {http://eprint.iacr.org/2013/778}, volume = 2013, year = 2013 }
  Link
  http://eprint.iacr.org/2013/778
10. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PalerKPH13, abteilung = {hocos}, author = {Paler, Alexandru and Kinseher, Josef and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2013 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City, NY, USA, October 2-4, 2013}, crossref = {DBLP:conf/dft/2013}, doi = {10.1109/DFT.2013.6653589}, pages = {95--100}, title = {Approximate simulation of circuits with probabilistic behavior}, url = {https://doi.org/10.1109/DFT.2013.6653589}, year = 2013 }
  Link
  https://doi.org/10.1109/DFT.2013.6653589
11. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Aza; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/JiangACARP13, abteilung = {hocos}, author = {Jiang, J. and Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd Asian Test Symposium, {ATS} 2013, Yilan County, Taiwan, November 18-21, 2013}, crossref = {DBLP:conf/ats/2013}, doi = {10.1109/ATS.2013.41}, pages = {177--182}, title = {{MIRID:} Mixed-Mode IR-Drop Induced Delay Simulator}, url = {https://doi.org/10.1109/ATS.2013.41}, year = 2013 }
  Link
  https://doi.org/10.1109/ATS.2013.41
12. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianK13, abteilung = {hocos}, author = {Polian, Ilia and Kreuzer, Martin}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2013, Karlovy Vary, Czech Republic, April 8-10, 2013}, crossref = {DBLP:conf/ddecs/2013}, doi = {10.1109/DDECS.2013.6549781}, pages = {12--17}, title = {Fault-based attacks on cryptographic hardware}, url = {https://doi.org/10.1109/DDECS.2013.6549781}, year = 2013 }
  Link
  https://doi.org/10.1109/DDECS.2013.6549781
13. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/SauerRPSB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Polian, Ilia and Schubert, Tobias and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2013, Yokohama, Japan, January 22-25, 2013}, crossref = {DBLP:conf/aspdac/2013}, doi = {10.1109/ASPDAC.2013.6509651}, pages = {533--539}, title = {Provably optimal test cube generation using quantified boolean formula solving}, url = {https://doi.org/10.1109/ASPDAC.2013.6509651}, year = 2013 }
  Link
  https://doi.org/10.1109/ASPDAC.2013.6509651
14. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/SauerCSHPB13, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2012.2230297}, journal = {{IEEE} Design {\&} Test}, number = 4, pages = {81--88}, title = {SAT-Based Analysis of Sensitizable Paths}, url = {https://doi.org/10.1109/MDT.2012.2230297}, volume = 30, year = 2013 }
  Link
  https://doi.org/10.1109/MDT.2012.2230297
15. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Aza; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/latw/AparicioCARJPB13, abteilung = {hocos}, author = {Aparicio, M. and Comte, Mariane and Aza{\"{\i}}s, Florence and Renovell, Michel and Jiang, J. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina, 3-5 April, 2013}, crossref = {DBLP:conf/latw/2013}, doi = {10.1109/LATW.2013.6562657}, pages = {1--6}, title = {Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays}, url = {https://doi.org/10.1109/LATW.2013.6562657}, year = 2013 }
  Link
  https://doi.org/10.1109/LATW.2013.6562657
16. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP13, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 778, title = {Multi-Stage Fault Attacks on Block Ciphers}, url = {http://eprint.iacr.org/2013/778}, volume = 2013, year = 2013 }
  Link
  http://eprint.iacr.org/2013/778
17. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/SauerRSPB13, abteilung = {hocos}, author = {Sauer, Matthias and Reimer, Sven and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France, March 18-22, 2013}, crossref = {DBLP:conf/date/2013}, doi = {10.7873/DATE.2013.100}, pages = {448--453}, title = {Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths}, url = {https://doi.org/10.7873/DATE.2013.100}, year = 2013 }
  Link
  https://doi.org/10.7873/DATE.2013.100
18. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianT13, abteilung = {hocos}, author = {Polian, Ilia and Tehranipoor, Mohammad}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA, April 29 - May 2, 2013}, crossref = {DBLP:conf/vts/2013}, doi = {10.1109/VTS.2013.6548944}, pages = 1, title = {Special session 12A: Hot topic counterfeit {IC} identification: How can test help?}, url = {https://doi.org/10.1109/VTS.2013.6548944}, year = 2013 }
  Link
  https://doi.org/10.1109/VTS.2013.6548944
2012
1. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
  - BibTeX
  - Link
  BibTeX
  @inbook{inbook, abteilung = {hocos}, author = {Becker, Bernd and Müller, Günter and Polian, Ilia}, doi = {10.5771/9783845238098-139}, isbn = {9783845238098}, month = {01}, pages = {139-149}, title = {Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society}, url = {https://doi.org/10.5771/9783845238098-139}, year = 2012 }
  Link
  https://doi.org/10.5771/9783845238098-139
2. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
  - BibTeX
  - Link
  BibTeX
  @inbook{inbook, abteilung = {hocos}, author = {Becker, Bernd and Müller, Günter and Polian, Ilia}, doi = {10.5771/9783845238098-139}, isbn = {9783845238098}, month = {01}, pages = {139-149}, title = {Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society}, url = {https://doi.org/10.5771/9783845238098-139}, year = 2012 }
  Link
  https://doi.org/10.5771/9783845238098-139
3. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cosade/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, {COSADE} 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings}, crossref = {DBLP:conf/cosade/2012}, doi = {10.1007/978-3-642-29912-4_10}, pages = {120--134}, title = {A Fault Attack on the {LED} Block Cipher}, url = {https://doi.org/10.1007/978-3-642-29912-4_10}, year = 2012 }
  Link
  https://doi.org/10.1007/978-3-642-29912-4_10
4. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/Polian12, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.88}, pages = 49, title = {Session Summary {I:} Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking}, url = {https://doi.org/10.1109/ATS.2012.88}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.88
5. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerCBP12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233027}, pages = {1--6}, title = {On the quality of test vectors for post-silicon characterization}, url = {https://doi.org/10.1109/ETS.2012.6233027}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233027
6. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/SauerCPB12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/iccad/2012}, doi = {10.1145/2429384.2429391}, pages = {30--36}, title = {Small-delay-fault {ATPG} with waveform accuracy}, url = {https://doi.org/10.1145/2429384.2429391}, year = 2012 }
  Link
  https://doi.org/10.1145/2429384.2429391
7. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/CzutroSSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA, 23-26 April 2012}, crossref = {DBLP:conf/vts/2012}, doi = {10.1109/VTS.2012.6231098}, pages = {170--175}, title = {{SAT-ATPG} using preferences for improved detection of complex defect mechanisms}, url = {https://doi.org/10.1109/VTS.2012.6231098}, year = 2012 }
  Link
  https://doi.org/10.1109/VTS.2012.6231098
8. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/nanoarch/PalerDNP12, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6, 2012}, crossref = {DBLP:conf/nanoarch/2012}, doi = {10.1145/2765491.2765524}, pages = {181--187}, title = {Synthesis of topological quantum circuits}, url = {https://doi.org/10.1145/2765491.2765524}, year = 2012 }
  Link
  https://doi.org/10.1145/2765491.2765524
9. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JiangSCBP12, abteilung = {hocos}, author = {Jiang, Jie and Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, crossref = {DBLP:conf/date/2012}, doi = {10.1109/DATE.2012.6176507}, pages = {418--423}, title = {On the optimality of {K} longest path generation algorithm under memory constraints}, url = {https://doi.org/10.1109/DATE.2012.6176507}, year = 2012 }
  Link
  https://doi.org/10.1109/DATE.2012.6176507
10. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 400, title = {An Algebraic Fault Attack on the {LED} Block Cipher}, url = {http://eprint.iacr.org/2012/400}, volume = 2012, year = 2012 }
  Link
  http://eprint.iacr.org/2012/400
11. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/PalerPH12, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012}, crossref = {DBLP:conf/aspdac/2012}, doi = {10.1109/ASPDAC.2012.6164942}, pages = {181--186}, title = {Detection and diagnosis of faulty quantum circuits}, url = {https://doi.org/10.1109/ASPDAC.2012.6164942}, year = 2012 }
  Link
  https://doi.org/10.1109/ASPDAC.2012.6164942
12. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/FeitenSSCBPB12, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Czutro, Alexander and B{\"{o}}hl, Eberhard and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA, October 3-5, 2012}, crossref = {DBLP:conf/dft/2012}, doi = {10.1109/DFT.2012.6378198}, pages = {49--54}, title = {{\#}SAT-based vulnerability analysis of security components - {A} case study}, url = {https://doi.org/10.1109/DFT.2012.6378198}, year = 2012 }
  Link
  https://doi.org/10.1109/DFT.2012.6378198
13. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/TomashevichSFP12, abteilung = {hocos}, author = {Tomashevich, Victor and Srinivasan, Sudarshan and Foerg, Fabian and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th {IEEE} International On-Line Testing Symposium, {IOLTS} 2012, Sitges, Spain, June 27-29, 2012}, crossref = {DBLP:conf/iolts/2012}, doi = {10.1109/IOLTS.2012.6313862}, pages = {150--155}, title = {Cross-level protection of circuits against faults and malicious attacks}, url = {https://doi.org/10.1109/IOLTS.2012.6313862}, year = 2012 }
  Link
  https://doi.org/10.1109/IOLTS.2012.6313862
14. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/SauerKCPRB12, abteilung = {hocos}, author = {Sauer, Matthias and Kupferschmid, Stefan and Czutro, Alexander and Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/itc/2012}, doi = {10.1109/TEST.2012.6401550}, pages = {1--8}, title = {Functional test of small-delay faults using {SAT} and Craig interpolation}, url = {https://doi.org/10.1109/TEST.2012.6401550}, year = 2012 }
  Link
  https://doi.org/10.1109/TEST.2012.6401550
15. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroIJMSBPW12, abteilung = {hocos}, author = {Czutro, Alexander and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, Matthias and Becker, Bernd and Polian, Ilia and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.14}, pages = {344--349}, title = {Variation-Aware Fault Grading}, url = {https://doi.org/10.1109/ATS.2012.14}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.14
16. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233026}, pages = {1--6}, title = {Multi-conditional {SAT-ATPG} for power-droop testing}, url = {https://doi.org/10.1109/ETS.2012.6233026}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233026
17. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233026}, pages = {1--6}, title = {Multi-conditional {SAT-ATPG} for power-droop testing}, url = {https://doi.org/10.1109/ETS.2012.6233026}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233026
18. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/FeitenSSCBPB12, abteilung = {hocos}, author = {Feiten, Linus and Sauer, Matthias and Schubert, Tobias and Czutro, Alexander and B{\"{o}}hl, Eberhard and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA, October 3-5, 2012}, crossref = {DBLP:conf/dft/2012}, doi = {10.1109/DFT.2012.6378198}, pages = {49--54}, title = {{\#}SAT-based vulnerability analysis of security components - {A} case study}, url = {https://doi.org/10.1109/DFT.2012.6378198}, year = 2012 }
  Link
  https://doi.org/10.1109/DFT.2012.6378198
19. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/SauerKCPRB12, abteilung = {hocos}, author = {Sauer, Matthias and Kupferschmid, Stefan and Czutro, Alexander and Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/itc/2012}, doi = {10.1109/TEST.2012.6401550}, pages = {1--8}, title = {Functional test of small-delay faults using {SAT} and Craig interpolation}, url = {https://doi.org/10.1109/TEST.2012.6401550}, year = 2012 }
  Link
  https://doi.org/10.1109/TEST.2012.6401550
20. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/cosade/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, {COSADE} 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings}, crossref = {DBLP:conf/cosade/2012}, doi = {10.1007/978-3-642-29912-4_10}, pages = {120--134}, title = {A Fault Attack on the {LED} Block Cipher}, url = {https://doi.org/10.1007/978-3-642-29912-4_10}, year = 2012 }
  Link
  https://doi.org/10.1007/978-3-642-29912-4_10
21. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/iacr/JovanovicKP12, abteilung = {hocos}, author = {Jovanovic, Philipp and Kreuzer, Martin and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, journal = {{IACR} Cryptology ePrint Archive}, pages = 400, title = {An Algebraic Fault Attack on the {LED} Block Cipher}, url = {http://eprint.iacr.org/2012/400}, volume = 2012, year = 2012 }
  Link
  http://eprint.iacr.org/2012/400
22. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/nanoarch/PalerDNP12, abteilung = {hocos}, author = {Paler, Alexandru and Devitt, Simon J. and Nemoto, Kae and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6, 2012}, crossref = {DBLP:conf/nanoarch/2012}, doi = {10.1145/2765491.2765524}, pages = {181--187}, title = {Synthesis of topological quantum circuits}, url = {https://doi.org/10.1145/2765491.2765524}, year = 2012 }
  Link
  https://doi.org/10.1145/2765491.2765524
23. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/aspdac/PalerPH12, abteilung = {hocos}, author = {Paler, Alexandru and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012}, crossref = {DBLP:conf/aspdac/2012}, doi = {10.1109/ASPDAC.2012.6164942}, pages = {181--186}, title = {Detection and diagnosis of faulty quantum circuits}, url = {https://doi.org/10.1109/ASPDAC.2012.6164942}, year = 2012 }
  Link
  https://doi.org/10.1109/ASPDAC.2012.6164942
24. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroIJMSBPW12, abteilung = {hocos}, author = {Czutro, Alexander and Imhof, Michael E. and Jiang, J. and Mumtaz, Abdullah and Sauer, Matthias and Becker, Bernd and Polian, Ilia and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.14}, pages = {344--349}, title = {Variation-Aware Fault Grading}, url = {https://doi.org/10.1109/ATS.2012.14}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.14
25. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/JiangSCBP12, abteilung = {hocos}, author = {Jiang, Jie and Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, crossref = {DBLP:conf/date/2012}, doi = {10.1109/DATE.2012.6176507}, pages = {418--423}, title = {On the optimality of {K} longest path generation algorithm under memory constraints}, url = {https://doi.org/10.1109/DATE.2012.6176507}, year = 2012 }
  Link
  https://doi.org/10.1109/DATE.2012.6176507
26. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/SauerCBP12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Becker, Bernd and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May 28 - June 1 2012}, crossref = {DBLP:conf/ets/2012}, doi = {10.1109/ETS.2012.6233027}, pages = {1--6}, title = {On the quality of test vectors for post-silicon characterization}, url = {https://doi.org/10.1109/ETS.2012.6233027}, year = 2012 }
  Link
  https://doi.org/10.1109/ETS.2012.6233027
27. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/Polian12, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21st {IEEE} Asian Test Symposium, {ATS} 2012, Niigata, Japan, November 19-22, 2012}, crossref = {DBLP:conf/ats/2012}, doi = {10.1109/ATS.2012.88}, pages = 49, title = {Session Summary {I:} Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking}, url = {https://doi.org/10.1109/ATS.2012.88}, year = 2012 }
  Link
  https://doi.org/10.1109/ATS.2012.88
28. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccad/SauerCPB12, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012}, crossref = {DBLP:conf/iccad/2012}, doi = {10.1145/2429384.2429391}, pages = {30--36}, title = {Small-delay-fault {ATPG} with waveform accuracy}, url = {https://doi.org/10.1145/2429384.2429391}, year = 2012 }
  Link
  https://doi.org/10.1145/2429384.2429391
29. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/CzutroSSPB12, abteilung = {hocos}, author = {Czutro, Alexander and Sauer, Matthias and Schubert, Tobias and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA, 23-26 April 2012}, crossref = {DBLP:conf/vts/2012}, doi = {10.1109/VTS.2012.6231098}, pages = {170--175}, title = {{SAT-ATPG} using preferences for improved detection of complex defect mechanisms}, url = {https://doi.org/10.1109/VTS.2012.6231098}, year = 2012 }
  Link
  https://doi.org/10.1109/VTS.2012.6231098
30. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/TomashevichSFP12, abteilung = {hocos}, author = {Tomashevich, Victor and Srinivasan, Sudarshan and Foerg, Fabian and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {18th {IEEE} International On-Line Testing Symposium, {IOLTS} 2012, Sitges, Spain, June 27-29, 2012}, crossref = {DBLP:conf/iolts/2012}, doi = {10.1109/IOLTS.2012.6313862}, pages = {150--155}, title = {Cross-level protection of circuits against faults and malicious attacks}, url = {https://doi.org/10.1109/IOLTS.2012.6313862}, year = 2012 }
  Link
  https://doi.org/10.1109/IOLTS.2012.6313862
2011
1. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KrauseP11, abteilung = {hocos}, author = {Krause, Philipp Klaus and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, crossref = {DBLP:conf/date/2011}, doi = {10.1109/DATE.2011.5763153}, pages = {944--949}, title = {Adaptive voltage over-scaling for resilient applications}, url = {https://doi.org/10.1109/DATE.2011.5763153}, year = 2011 }
  Link
  https://doi.org/10.1109/DATE.2011.5763153
2. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianBHWM11, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans{-}Joachim and Maxwell, Peter C.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.51}, pages = {219--225}, title = {Towards Variation-Aware Test Methods}, url = {https://doi.org/10.1109/ETS.2011.51}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.51
3. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/SauerCSHPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15, 2011}, crossref = {DBLP:conf/ddecs/2011}, doi = {10.1109/DDECS.2011.5783055}, pages = {93--98}, title = {SAT-based analysis of sensitisable paths}, url = {https://doi.org/10.1109/DDECS.2011.5783055}, year = 2011 }
  Link
  https://doi.org/10.1109/DDECS.2011.5783055
4. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993819}, pages = {104--110}, title = {Estimation of component criticality in early design steps}, url = {https://doi.org/10.1109/IOLTS.2011.5993819}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993819
5. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianH11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2010.120}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {54--63}, title = {Selective Hardening: Toward Cost-Effective Error Tolerance}, url = {https://doi.org/10.1109/MDT.2010.120}, volume = 28, year = 2011 }
  Link
  https://doi.org/10.1109/MDT.2010.120
6. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/chinaf/HopschBHPSVW11, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s11432-011-4367-8}, journal = {{SCIENCE} {CHINA} Information Sciences}, number = 9, pages = {1813--1826}, title = {Variation-aware fault modeling}, url = {https://doi.org/10.1007/s11432-011-4367-8}, volume = 54, year = 2011 }
  Link
  https://doi.org/10.1007/s11432-011-4367-8
7. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, crossref = {DBLP:conf/ats/2011}, doi = {10.1109/ATS.2011.43}, pages = {108--113}, title = {Efficient SAT-Based Search for Longest Sensitisable Paths}, url = {https://doi.org/10.1109/ATS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ATS.2011.43
8. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tdsc/PolianHRB11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TDSC.2010.26}, journal = {{IEEE} Trans. Dependable Sec. Comput.}, number = 4, pages = {537--547}, title = {Modeling and Mitigating Transient Errors in Logic Circuits}, url = {https://doi.org/10.1109/TDSC.2010.26}, volume = 8, year = 2011 }
  Link
  https://doi.org/10.1109/TDSC.2010.26
9. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerTMLSPBB11, abteilung = {hocos}, author = {Sauer, Matthias and Tomashevich, Victor and M{\"{u}}ller, J{\"{o}}rg and Lewis, Matthew D. T. and Spilla, Andreas and Polian, Ilia and Becker, Bernd and Burgard, Wolfram}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993836}, pages = {182--185}, title = {An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors}, url = {https://doi.org/10.1109/IOLTS.2011.5993836}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993836
10. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PalerAPH11, abteilung = {hocos}, author = {Paler, Alexandru and Alaghi, Armin and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.43}, pages = {63--68}, title = {Tomographic Testing and Validation of Probabilistic Circuits}, url = {https://doi.org/10.1109/ETS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.43
11. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tdsc/PolianHRB11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TDSC.2010.26}, journal = {{IEEE} Trans. Dependable Sec. Comput.}, number = 4, pages = {537--547}, title = {Modeling and Mitigating Transient Errors in Logic Circuits}, url = {https://doi.org/10.1109/TDSC.2010.26}, volume = 8, year = 2011 }
  Link
  https://doi.org/10.1109/TDSC.2010.26
12. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianH11, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2010.120}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {54--63}, title = {Selective Hardening: Toward Cost-Effective Error Tolerance}, url = {https://doi.org/10.1109/MDT.2010.120}, volume = 28, year = 2011 }
  Link
  https://doi.org/10.1109/MDT.2010.120
13. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerTMLSPBB11, abteilung = {hocos}, author = {Sauer, Matthias and Tomashevich, Victor and M{\"{u}}ller, J{\"{o}}rg and Lewis, Matthew D. T. and Spilla, Andreas and Polian, Ilia and Becker, Bernd and Burgard, Wolfram}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993836}, pages = {182--185}, title = {An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors}, url = {https://doi.org/10.1109/IOLTS.2011.5993836}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993836
14. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/SauerCSHPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alexander and Schubert, Tobias and Hillebrecht, Stefan and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15, 2011}, crossref = {DBLP:conf/ddecs/2011}, doi = {10.1109/DDECS.2011.5783055}, pages = {93--98}, title = {SAT-based analysis of sensitisable paths}, url = {https://doi.org/10.1109/DDECS.2011.5783055}, year = 2011 }
  Link
  https://doi.org/10.1109/DDECS.2011.5783055
15. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/KrauseP11, abteilung = {hocos}, author = {Krause, Philipp Klaus and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, crossref = {DBLP:conf/date/2011}, doi = {10.1109/DATE.2011.5763153}, pages = {944--949}, title = {Adaptive voltage over-scaling for resilient applications}, url = {https://doi.org/10.1109/DATE.2011.5763153}, year = 2011 }
  Link
  https://doi.org/10.1109/DATE.2011.5763153
16. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PolianBHWM11, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans{-}Joachim and Maxwell, Peter C.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.51}, pages = {219--225}, title = {Towards Variation-Aware Test Methods}, url = {https://doi.org/10.1109/ETS.2011.51}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.51
17. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/SauerJCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Jiang, Jie and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, crossref = {DBLP:conf/ats/2011}, doi = {10.1109/ATS.2011.43}, pages = {108--113}, title = {Efficient SAT-Based Search for Longest Sensitisable Paths}, url = {https://doi.org/10.1109/ATS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ATS.2011.43
18. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/SauerCPB11, abteilung = {hocos}, author = {Sauer, Matthias and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {17th {IEEE} International On-Line Testing Symposium {(IOLTS} 2011), 13-15 July, 2011, Athens, Greece}, crossref = {DBLP:conf/iolts/2011}, doi = {10.1109/IOLTS.2011.5993819}, pages = {104--110}, title = {Estimation of component criticality in early design steps}, url = {https://doi.org/10.1109/IOLTS.2011.5993819}, year = 2011 }
  Link
  https://doi.org/10.1109/IOLTS.2011.5993819
19. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/chinaf/HopschBHPSVW11, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s11432-011-4367-8}, journal = {{SCIENCE} {CHINA} Information Sciences}, number = 9, pages = {1813--1826}, title = {Variation-aware fault modeling}, url = {https://doi.org/10.1007/s11432-011-4367-8}, volume = 54, year = 2011 }
  Link
  https://doi.org/10.1007/s11432-011-4367-8
20. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/PalerAPH11, abteilung = {hocos}, author = {Paler, Alexandru and Alaghi, Armin and Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27, 2011}, crossref = {DBLP:conf/ets/2011}, doi = {10.1109/ETS.2011.43}, pages = {63--68}, title = {Tomographic Testing and Validation of Probabilistic Circuits}, url = {https://doi.org/10.1109/ETS.2011.43}, year = 2011 }
  Link
  https://doi.org/10.1109/ETS.2011.43
2010
1. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/BeckerHPSVW10, abteilung = {hocos}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE/IFIP} International Conference on Dependable Systems and Networks Workshops {(DSN-W} 2010), Chicago, Illinois, USA, June 28 - July 1, 2010.}, crossref = {DBLP:conf/dsn/2010w}, doi = {10.1109/DSNW.2010.5542612}, pages = {95--100}, title = {Massive statistical process variations: {A} grand challenge for testing nanoelectronic circuits}, url = {https://doi.org/10.1109/DSNW.2010.5542612}, year = 2010 }
  Link
  https://doi.org/10.1109/DSNW.2010.5542612
2. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jolpe/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1166/jolpe.2010.1075}, journal = {J. Low Power Electronics}, number = 2, pages = {326--338}, title = {Power Supply Noise: Causes, Effects, and Testing}, url = {https://doi.org/10.1166/jolpe.2010.1075}, volume = 6, year = 2010 }
  Link
  https://doi.org/10.1166/jolpe.2010.1075
3. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2010}, doi = {10.1109/VTS.2010.5469594}, pages = 130, title = {Special session 4B: Panel low-power test and noise-aware test: Foes or friends?}, url = {https://doi.org/10.1109/VTS.2010.5469594}, year = 2010 }
  Link
  https://doi.org/10.1109/VTS.2010.5469594
4. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewdts/PolianH10, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2010 East-West Design {\&} Test Symposium, {EWDTS} 2010, St. Petersburg, Russia, September 17-20, 2010}, crossref = {DBLP:conf/ewdts/2010}, doi = {10.1109/EWDTS.2010.5742135}, pages = {376--381}, title = {Advanced modeling of faults in Reversible circuits}, url = {https://doi.org/10.1109/EWDTS.2010.5742135}, year = 2010 }
  Link
  https://doi.org/10.1109/EWDTS.2010.5742135
5. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/PolianB10, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.2010.0590}, journal = {it - Information Technology}, number = 4, pages = {189--194}, title = {Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen f{\"{u}}r Nanoscale-Technologien)}, url = {https://doi.org/10.1524/itit.2010.0590}, volume = 52, year = 2010 }
  Link
  https://doi.org/10.1524/itit.2010.0590
6. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/ijpp/CzutroPLERB10, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10766-009-0124-7}, journal = {International Journal of Parallel Programming}, number = {3-4}, pages = {185--202}, title = {Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis}, url = {https://doi.org/10.1007/s10766-009-0124-7}, volume = 38, year = 2010 }
  Link
  https://doi.org/10.1007/s10766-009-0124-7
7. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HopschBHPSVW10, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, crossref = {DBLP:conf/ats/2010}, doi = {10.1109/ATS.2010.24}, pages = {87--93}, title = {Variation-Aware Fault Modeling}, url = {https://doi.org/10.1109/ATS.2010.24}, year = 2010 }
  Link
  https://doi.org/10.1109/ATS.2010.24
8. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
  Abstract
  Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.
  BibTeX
  @incollection{BeckeP2010, abstract = {Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.}, abteilung = {hocos}, address = {Dordrecht}, author = {Becker, Bernd and Polian, Ilia}, booktitle = {Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault}, doi = {10.1007/978-90-481-3282-9_4}, issn = {978-90-481-3282-9}, owner = {haefneht}, pages = {105--131}, publisher = {Springer Netherlands}, refid = {Becker2010}, title = {Fault Modeling for Simulation and ATPG}, url = {https://doi.org/10.1007/978-90-481-3282-9_4}, year = 2010 }
  Link
  https://doi.org/10.1007/978-90-481-3282-9_4
9. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
  Abstract
  Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.
  BibTeX
  @incollection{BeckeP2010, abstract = {Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.}, abteilung = {hocos}, address = {Dordrecht}, author = {Becker, Bernd and Polian, Ilia}, booktitle = {Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault}, doi = {10.1007/978-90-481-3282-9_4}, issn = {978-90-481-3282-9}, owner = {haefneht}, pages = {105--131}, publisher = {Springer Netherlands}, refid = {Becker2010}, title = {Fault Modeling for Simulation and ATPG}, url = {https://doi.org/10.1007/978-90-481-3282-9_4}, year = 2010 }
  Link
  https://doi.org/10.1007/978-90-481-3282-9_4
10. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2010}, doi = {10.1109/VTS.2010.5469594}, pages = 130, title = {Special session 4B: Panel low-power test and noise-aware test: Foes or friends?}, url = {https://doi.org/10.1109/VTS.2010.5469594}, year = 2010 }
  Link
  https://doi.org/10.1109/VTS.2010.5469594
11. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/BeckerHPSVW10, abteilung = {hocos}, author = {Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE/IFIP} International Conference on Dependable Systems and Networks Workshops {(DSN-W} 2010), Chicago, Illinois, USA, June 28 - July 1, 2010.}, crossref = {DBLP:conf/dsn/2010w}, doi = {10.1109/DSNW.2010.5542612}, pages = {95--100}, title = {Massive statistical process variations: {A} grand challenge for testing nanoelectronic circuits}, url = {https://doi.org/10.1109/DSNW.2010.5542612}, year = 2010 }
  Link
  https://doi.org/10.1109/DSNW.2010.5542612
12. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/jolpe/Polian10, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1166/jolpe.2010.1075}, journal = {J. Low Power Electronics}, number = 2, pages = {326--338}, title = {Power Supply Noise: Causes, Effects, and Testing}, url = {https://doi.org/10.1166/jolpe.2010.1075}, volume = 6, year = 2010 }
  Link
  https://doi.org/10.1166/jolpe.2010.1075
13. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ewdts/PolianH10, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2010 East-West Design {\&} Test Symposium, {EWDTS} 2010, St. Petersburg, Russia, September 17-20, 2010}, crossref = {DBLP:conf/ewdts/2010}, doi = {10.1109/EWDTS.2010.5742135}, pages = {376--381}, title = {Advanced modeling of faults in Reversible circuits}, url = {https://doi.org/10.1109/EWDTS.2010.5742135}, year = 2010 }
  Link
  https://doi.org/10.1109/EWDTS.2010.5742135
14. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HopschBHPSVW10, abteilung = {hocos}, author = {Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans{-}Joachim}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4 December 2010, Shanghai, China}, crossref = {DBLP:conf/ats/2010}, doi = {10.1109/ATS.2010.24}, pages = {87--93}, title = {Variation-Aware Fault Modeling}, url = {https://doi.org/10.1109/ATS.2010.24}, year = 2010 }
  Link
  https://doi.org/10.1109/ATS.2010.24
15. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/PolianB10, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.2010.0590}, journal = {it - Information Technology}, number = 4, pages = {189--194}, title = {Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen f{\"{u}}r Nanoscale-Technologien)}, url = {https://doi.org/10.1524/itit.2010.0590}, volume = 52, year = 2010 }
  Link
  https://doi.org/10.1524/itit.2010.0590
16. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/ijpp/CzutroPLERB10, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10766-009-0124-7}, journal = {International Journal of Parallel Programming}, number = {3-4}, pages = {185--202}, title = {Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis}, url = {https://doi.org/10.1007/s10766-009-0124-7}, volume = 38, year = 2010 }
  Link
  https://doi.org/10.1007/s10766-009-0124-7
2009
1. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/HungerHCPB09, abteilung = {hocos}, author = {Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal}, crossref = {DBLP:conf/iolts/2009}, doi = {10.1109/IOLTS.2009.5196027}, pages = {269--274}, title = {ATPG-based grading of strong fault-secureness}, url = {https://doi.org/10.1109/IOLTS.2009.5196027}, year = 2009 }
  Link
  https://doi.org/10.1109/IOLTS.2009.5196027
2. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/glvlsi/GaneshpurePKB09, abteilung = {hocos}, author = {Ganeshpure, Kunal P. and Polian, Ilia and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009, Boston Area, MA, USA, May 10-12 2009}, crossref = {DBLP:conf/glvlsi/2009}, doi = {10.1145/1531542.1531560}, pages = {63--68}, title = {Reducing temperature variability by routing heat pipes}, url = {https://doi.org/10.1145/1531542.1531560}, year = 2009 }
  Link
  https://doi.org/10.1145/1531542.1531560
3. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroPLERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on {VLSI} Design, New Delhi, India, 5-9 January 2009}, crossref = {DBLP:conf/vlsid/2009}, doi = {10.1109/VLSI.Design.2009.20}, pages = {227--232}, title = {{TIGUAN:} Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis}, url = {https://doi.org/10.1109/VLSI.Design.2009.20}, year = 2009 }
  Link
  https://doi.org/10.1109/VLSI.Design.2009.20
4. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroPERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26 November 2009, Taichung, Taiwan}, crossref = {DBLP:conf/ats/2009}, doi = {10.1109/ATS.2009.31}, pages = {187--190}, title = {Dynamic Compaction in SAT-Based {ATPG}}, url = {https://doi.org/10.1109/ATS.2009.31}, year = 2009 }
  Link
  https://doi.org/10.1109/ATS.2009.31
5. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/IzosimovPPEP09, abteilung = {hocos}, author = {Izosimov, Viacheslav and Polian, Ilia and Pop, Paul and Eles, Petru and Peng, Zebo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France, April 20-24, 2009}, crossref = {DBLP:conf/date/2009}, doi = {10.1109/DATE.2009.5090752}, pages = {682--687}, title = {Analysis and optimization of fault-tolerant embedded systems with hardened processors}, url = {https://doi.org/10.1109/DATE.2009.5090752}, year = 2009 }
  Link
  https://doi.org/10.1109/DATE.2009.5090752
6. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HouarcheCRCEPB09, abteilung = {hocos}, author = {Houarche, Nicolas and Comte, Mariane and Renovell, Michel and Czutro, Alejandro and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2009}, doi = {10.1109/VTS.2009.57}, pages = {21--26}, title = {An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects}, url = {https://doi.org/10.1109/VTS.2009.57}, year = 2009 }
  Link
  https://doi.org/10.1109/VTS.2009.57
7. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/todaes/EngelkeBRSBP09, abteilung = {hocos}, author = {Engelke, Piet and Becker, Bernd and Renovell, Michel and Schl{\"{o}}ffel, J{\"{u}}rgen and Braitling, Bettina and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/1562514.1596831}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, number = 4, pages = {56:1--56:21}, title = {{SUPERB:} Simulator utilizing parallel evaluation of resistive bridges}, url = {https://doi.org/10.1145/1562514.1596831}, volume = 14, year = 2009 }
  Link
  https://doi.org/10.1145/1562514.1596831
8. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/todaes/EngelkeBRSBP09, abteilung = {hocos}, author = {Engelke, Piet and Becker, Bernd and Renovell, Michel and Schl{\"{o}}ffel, J{\"{u}}rgen and Braitling, Bettina and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1145/1562514.1596831}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, number = 4, pages = {56:1--56:21}, title = {{SUPERB:} Simulator utilizing parallel evaluation of resistive bridges}, url = {https://doi.org/10.1145/1562514.1596831}, volume = 14, year = 2009 }
  Link
  https://doi.org/10.1145/1562514.1596831
9. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/HungerHCPB09, abteilung = {hocos}, author = {Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal}, crossref = {DBLP:conf/iolts/2009}, doi = {10.1109/IOLTS.2009.5196027}, pages = {269--274}, title = {ATPG-based grading of strong fault-secureness}, url = {https://doi.org/10.1109/IOLTS.2009.5196027}, year = 2009 }
  Link
  https://doi.org/10.1109/IOLTS.2009.5196027
10. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/IzosimovPPEP09, abteilung = {hocos}, author = {Izosimov, Viacheslav and Polian, Ilia and Pop, Paul and Eles, Petru and Peng, Zebo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France, April 20-24, 2009}, crossref = {DBLP:conf/date/2009}, doi = {10.1109/DATE.2009.5090752}, pages = {682--687}, title = {Analysis and optimization of fault-tolerant embedded systems with hardened processors}, url = {https://doi.org/10.1109/DATE.2009.5090752}, year = 2009 }
  Link
  https://doi.org/10.1109/DATE.2009.5090752
11. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/CzutroPERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26 November 2009, Taichung, Taiwan}, crossref = {DBLP:conf/ats/2009}, doi = {10.1109/ATS.2009.31}, pages = {187--190}, title = {Dynamic Compaction in SAT-Based {ATPG}}, url = {https://doi.org/10.1109/ATS.2009.31}, year = 2009 }
  Link
  https://doi.org/10.1109/ATS.2009.31
12. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/glvlsi/GaneshpurePKB09, abteilung = {hocos}, author = {Ganeshpure, Kunal P. and Polian, Ilia and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009, Boston Area, MA, USA, May 10-12 2009}, crossref = {DBLP:conf/glvlsi/2009}, doi = {10.1145/1531542.1531560}, pages = {63--68}, title = {Reducing temperature variability by routing heat pipes}, url = {https://doi.org/10.1145/1531542.1531560}, year = 2009 }
  Link
  https://doi.org/10.1145/1531542.1531560
13. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vlsid/CzutroPLERB09, abteilung = {hocos}, author = {Czutro, Alejandro and Polian, Ilia and Lewis, Matthew D. T. and Engelke, Piet and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on {VLSI} Design, New Delhi, India, 5-9 January 2009}, crossref = {DBLP:conf/vlsid/2009}, doi = {10.1109/VLSI.Design.2009.20}, pages = {227--232}, title = {{TIGUAN:} Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis}, url = {https://doi.org/10.1109/VLSI.Design.2009.20}, year = 2009 }
  Link
  https://doi.org/10.1109/VLSI.Design.2009.20
14. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HouarcheCRCEPB09, abteilung = {hocos}, author = {Houarche, Nicolas and Comte, Mariane and Renovell, Michel and Czutro, Alejandro and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa Cruz, California, {USA}}, crossref = {DBLP:conf/vts/2009}, doi = {10.1109/VTS.2009.57}, pages = {21--26}, title = {An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects}, url = {https://doi.org/10.1109/VTS.2009.57}, year = 2009 }
  Link
  https://doi.org/10.1109/VTS.2009.57
2008
1. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/SpinnerPEBKC08, abteilung = {hocos}, author = {Spinner, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1, 2008, San Diego, California, {USA}}, crossref = {DBLP:conf/vts/2008}, doi = {10.1109/VTS.2008.30}, pages = {181--186}, title = {Automatic Test Pattern Generation for Interconnect Open Defects}, url = {https://doi.org/10.1109/VTS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/VTS.2008.30
2. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/HillebrechtPEBKC08, abteilung = {hocos}, author = {Hillebrecht, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara, California, USA, October 26-31, 2008}, crossref = {DBLP:conf/itc/2008}, doi = {10.1109/TEST.2008.4700642}, pages = {1--10}, title = {Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model}, url = {https://doi.org/10.1109/TEST.2008.4700642}, year = 2008 }
  Link
  https://doi.org/10.1109/TEST.2008.4700642
3. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/EngelkePSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Schl{\"{o}}ffel, J{\"{u}}rgen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, crossref = {DBLP:conf/date/2008}, doi = {10.1109/DATE.2008.4484747}, pages = {628--633}, title = {Resistive Bridging Fault Simulation of Industrial Circuits}, url = {https://doi.org/10.1109/DATE.2008.4484747}, year = 2008 }
  Link
  https://doi.org/10.1109/DATE.2008.4484747
4. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianMNKEBSW08, abteilung = {hocos}, author = {Polian, Ilia and Miyase, Kohei and Nakamura, Yusuke and Kajihara, Seiji and Engelke, Piet and Becker, Bernd and Spinner, Stefan and Wen, Xiaoqing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava, Slovakia, April 16-18, 2008}, crossref = {DBLP:conf/ddecs/2008}, doi = {10.1109/DDECS.2008.4538798}, pages = {263--266}, title = {Diagnosis of Realistic Defects Based on the X-Fault Model}, url = {https://doi.org/10.1109/DDECS.2008.4538798}, year = 2008 }
  Link
  https://doi.org/10.1109/DDECS.2008.4538798
5. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/ZoellinWPB08, abteilung = {hocos}, author = {Zoellin, Christian G. and Wunderlich, Hans{-}Joachim and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.30}, pages = {185--190}, title = {Selective Hardening in Early Design Steps}, url = {https://doi.org/10.1109/ETS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.30
6. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianRPTB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Pomeranz, Irith and Tang, Xun and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.20}, pages = {245--253}, title = {On Reducing Circuit Malfunctions Caused by Soft Errors}, url = {https://doi.org/10.1109/DFT.2008.20}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.20
7. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianR08, abteilung = {hocos}, author = {Polian, Ilia and Rao, Wenjing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.26}, pages = {263--271}, title = {Selective Hardening of NanoPLA Circuits}, url = {https://doi.org/10.1109/DFT.2008.26}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.26
8. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroHEPCRB08, abteilung = {hocos}, author = {Czutro, Alejandro and Houarche, Nicolas and Engelke, Piet and Polian, Ilia and Comte, Mariane and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.19}, pages = {113--118}, title = {A Simulator of Small-Delay Faults Caused by Resistive-Open Defects}, url = {https://doi.org/10.1109/ETS.2008.19}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.19
9. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRKSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Kundu, Sandip and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2007.913382}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 2, pages = {327--338}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/TCAD.2007.913382}, volume = 27, year = 2008 }
  Link
  https://doi.org/10.1109/TCAD.2007.913382
10. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/isvlsi/PolianRB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9 April 2008, Montpellier, France}, crossref = {DBLP:conf/isvlsi/2008}, doi = {10.1109/ISVLSI.2008.22}, pages = {257--262}, title = {Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors}, url = {https://doi.org/10.1109/ISVLSI.2008.22}, year = 2008 }
  Link
  https://doi.org/10.1109/ISVLSI.2008.22
11. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/NowrothPB08, abteilung = {hocos}, author = {Nowroth, Damian and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {The 38th Annual {IEEE/IFIP} International Conference on Dependable Systems and Networks, {DSN} 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings}, crossref = {DBLP:conf/dsn/2008}, doi = {10.1109/DSN.2008.4630068}, pages = {32--41}, title = {A study of cognitive resilience in a {JPEG} compressor}, url = {https://doi.org/10.1109/DSN.2008.4630068}, year = 2008 }
  Link
  https://doi.org/10.1109/DSN.2008.4630068
12. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/CzutroHEPCRB08, abteilung = {hocos}, author = {Czutro, Alejandro and Houarche, Nicolas and Engelke, Piet and Polian, Ilia and Comte, Mariane and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.19}, pages = {113--118}, title = {A Simulator of Small-Delay Faults Caused by Resistive-Open Defects}, url = {https://doi.org/10.1109/ETS.2008.19}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.19
13. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/PolianMNKEBSW08, abteilung = {hocos}, author = {Polian, Ilia and Miyase, Kohei and Nakamura, Yusuke and Kajihara, Seiji and Engelke, Piet and Becker, Bernd and Spinner, Stefan and Wen, Xiaoqing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava, Slovakia, April 16-18, 2008}, crossref = {DBLP:conf/ddecs/2008}, doi = {10.1109/DDECS.2008.4538798}, pages = {263--266}, title = {Diagnosis of Realistic Defects Based on the X-Fault Model}, url = {https://doi.org/10.1109/DDECS.2008.4538798}, year = 2008 }
  Link
  https://doi.org/10.1109/DDECS.2008.4538798
14. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/SpinnerPEBKC08, abteilung = {hocos}, author = {Spinner, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1, 2008, San Diego, California, {USA}}, crossref = {DBLP:conf/vts/2008}, doi = {10.1109/VTS.2008.30}, pages = {181--186}, title = {Automatic Test Pattern Generation for Interconnect Open Defects}, url = {https://doi.org/10.1109/VTS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/VTS.2008.30
15. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRKSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Kundu, Sandip and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2007.913382}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 2, pages = {327--338}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/TCAD.2007.913382}, volume = 27, year = 2008 }
  Link
  https://doi.org/10.1109/TCAD.2007.913382
16. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianRPTB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Pomeranz, Irith and Tang, Xun and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.20}, pages = {245--253}, title = {On Reducing Circuit Malfunctions Caused by Soft Errors}, url = {https://doi.org/10.1109/DFT.2008.20}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.20
17. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/isvlsi/PolianRB08, abteilung = {hocos}, author = {Polian, Ilia and Reddy, Sudhakar M. and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9 April 2008, Montpellier, France}, crossref = {DBLP:conf/isvlsi/2008}, doi = {10.1109/ISVLSI.2008.22}, pages = {257--262}, title = {Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors}, url = {https://doi.org/10.1109/ISVLSI.2008.22}, year = 2008 }
  Link
  https://doi.org/10.1109/ISVLSI.2008.22
18. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianR08, abteilung = {hocos}, author = {Polian, Ilia and Rao, Wenjing}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}}, crossref = {DBLP:conf/dft/2008}, doi = {10.1109/DFT.2008.26}, pages = {263--271}, title = {Selective Hardening of NanoPLA Circuits}, url = {https://doi.org/10.1109/DFT.2008.26}, year = 2008 }
  Link
  https://doi.org/10.1109/DFT.2008.26
19. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/HillebrechtPEBKC08, abteilung = {hocos}, author = {Hillebrecht, Stefan and Polian, Ilia and Engelke, Piet and Becker, Bernd and Keim, Martin and Cheng, Wu{-}Tung}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara, California, USA, October 26-31, 2008}, crossref = {DBLP:conf/itc/2008}, doi = {10.1109/TEST.2008.4700642}, pages = {1--10}, title = {Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model}, url = {https://doi.org/10.1109/TEST.2008.4700642}, year = 2008 }
  Link
  https://doi.org/10.1109/TEST.2008.4700642
20. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/EngelkePSB08, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Schl{\"{o}}ffel, J{\"{u}}rgen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, crossref = {DBLP:conf/date/2008}, doi = {10.1109/DATE.2008.4484747}, pages = {628--633}, title = {Resistive Bridging Fault Simulation of Industrial Circuits}, url = {https://doi.org/10.1109/DATE.2008.4484747}, year = 2008 }
  Link
  https://doi.org/10.1109/DATE.2008.4484747
21. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/ZoellinWPB08, abteilung = {hocos}, author = {Zoellin, Christian G. and Wunderlich, Hans{-}Joachim and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29, 2008}, crossref = {DBLP:conf/ets/2008}, doi = {10.1109/ETS.2008.30}, pages = {185--190}, title = {Selective Hardening in Early Design Steps}, url = {https://doi.org/10.1109/ETS.2008.30}, year = 2008 }
  Link
  https://doi.org/10.1109/ETS.2008.30
22. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dsn/NowrothPB08, abteilung = {hocos}, author = {Nowroth, Damian and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {The 38th Annual {IEEE/IFIP} International Conference on Dependable Systems and Networks, {DSN} 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings}, crossref = {DBLP:conf/dsn/2008}, doi = {10.1109/DSN.2008.4630068}, pages = {32--41}, title = {A study of cognitive resilience in a {JPEG} compressor}, url = {https://doi.org/10.1109/DSN.2008.4630068}, year = 2008 }
  Link
  https://doi.org/10.1109/DSN.2008.4630068
2007
1. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/corr/abs-0710-4670, abteilung = {hocos}, archiveprefix = {arXiv}, author = {Polian, Ilia and Czutro, Alejandro and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, eprint = {0710.4670}, journal = {CoRR}, title = {Evolutionary Optimization in Code-Based Test Compression}, url = {http://arxiv.org/abs/0710.4670}, volume = {abs/0710.4670}, year = 2007 }
  Link
  http://arxiv.org/abs/0710.4670
2. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianCKB07, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2007.77}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {276--284}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/MDT.2007.77}, volume = 24, year = 2007 }
  Link
  https://doi.org/10.1109/MDT.2007.77
3. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianNB07, abteilung = {hocos}, author = {Polian, Ilia and Nowroth, Damian and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th {IEEE} International On-Line Testing Symposium {(IOLTS} 2007), 8-11 July 2007, Heraklion, Crete, Greece}, crossref = {DBLP:conf/iolts/2007}, doi = {10.1109/IOLTS.2007.38}, pages = {201--202}, title = {Identification of Critical Errors in Imaging Applications}, url = {https://doi.org/10.1109/IOLTS.2007.38}, year = 2007 }
  Link
  https://doi.org/10.1109/IOLTS.2007.38
4. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HayesPB07, abteilung = {hocos}, author = {Hayes, John P. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley, California, {USA}}, crossref = {DBLP:conf/vts/2007}, doi = {10.1109/VTS.2007.13}, pages = {249--255}, title = {An Analysis Framework for Transient-Error Tolerance}, url = {https://doi.org/10.1109/VTS.2007.13}, year = 2007 }
  Link
  https://doi.org/10.1109/VTS.2007.13
5. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianF07, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-007-5013-7}, journal = {J. Electronic Testing}, number = 5, pages = {445--455}, title = {Functional Constraints vs. Test Compression in Scan-Based Delay Testing}, url = {https://doi.org/10.1007/s10836-007-5013-7}, volume = 23, year = 2007 }
  Link
  https://doi.org/10.1007/s10836-007-5013-7
6. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/corr/abs-0711-3289, abteilung = {hocos}, archiveprefix = {arXiv}, author = {Spinner, Stefan and Bartholomeyczik, J. and Becker, Bernd and Doelle, M. and Paul, Oliver and Polian, Ilia and Roth, R. and Seitz, K. and Ruther, Patrick}, bibsource = {dblp computer science bibliography, https://dblp.org}, eprint = {0711.3289}, journal = {CoRR}, title = {Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors}, url = {http://arxiv.org/abs/0711.3289}, volume = {abs/0711.3289}, year = 2007 }
  Link
  http://arxiv.org/abs/0711.3289
7. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/dt/PolianCKB07, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/MDT.2007.77}, journal = {{IEEE} Design {\&} Test of Computers}, number = 3, pages = {276--284}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/MDT.2007.77}, volume = 24, year = 2007 }
  Link
  https://doi.org/10.1109/MDT.2007.77
8. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/corr/abs-0711-3289, abteilung = {hocos}, archiveprefix = {arXiv}, author = {Spinner, Stefan and Bartholomeyczik, J. and Becker, Bernd and Doelle, M. and Paul, Oliver and Polian, Ilia and Roth, R. and Seitz, K. and Ruther, Patrick}, bibsource = {dblp computer science bibliography, https://dblp.org}, eprint = {0711.3289}, journal = {CoRR}, title = {Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors}, url = {http://arxiv.org/abs/0711.3289}, volume = {abs/0711.3289}, year = 2007 }
  Link
  http://arxiv.org/abs/0711.3289
9. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/HayesPB07, abteilung = {hocos}, author = {Hayes, John P. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley, California, {USA}}, crossref = {DBLP:conf/vts/2007}, doi = {10.1109/VTS.2007.13}, pages = {249--255}, title = {An Analysis Framework for Transient-Error Tolerance}, url = {https://doi.org/10.1109/VTS.2007.13}, year = 2007 }
  Link
  https://doi.org/10.1109/VTS.2007.13
10. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianF07, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-007-5013-7}, journal = {J. Electronic Testing}, number = 5, pages = {445--455}, title = {Functional Constraints vs. Test Compression in Scan-Based Delay Testing}, url = {https://doi.org/10.1007/s10836-007-5013-7}, volume = 23, year = 2007 }
  Link
  https://doi.org/10.1007/s10836-007-5013-7
11. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/corr/abs-0710-4670, abteilung = {hocos}, archiveprefix = {arXiv}, author = {Polian, Ilia and Czutro, Alejandro and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, eprint = {0710.4670}, journal = {CoRR}, title = {Evolutionary Optimization in Code-Based Test Compression}, url = {http://arxiv.org/abs/0710.4670}, volume = {abs/0710.4670}, year = 2007 }
  Link
  http://arxiv.org/abs/0710.4670
12. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianNB07, abteilung = {hocos}, author = {Polian, Ilia and Nowroth, Damian and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th {IEEE} International On-Line Testing Symposium {(IOLTS} 2007), 8-11 July 2007, Heraklion, Crete, Greece}, crossref = {DBLP:conf/iolts/2007}, doi = {10.1109/IOLTS.2007.38}, pages = {201--202}, title = {Identification of Critical Errors in Imaging Applications}, url = {https://doi.org/10.1109/IOLTS.2007.38}, year = 2007 }
  Link
  https://doi.org/10.1109/IOLTS.2007.38
2006
1. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccd/PolianCKB06, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th International Conference on Computer Design {(ICCD} 2006), 1-4 October 2006, San Jose, CA, {USA}}, crossref = {DBLP:conf/iccd/2006}, doi = {10.1109/ICCD.2006.4380824}, pages = {243--250}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/ICCD.2006.4380824}, year = 2006 }
  Link
  https://doi.org/10.1109/ICCD.2006.4380824
2. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianF06, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, crossref = {DBLP:conf/date/2006p}, doi = {10.1109/DATE.2006.243927}, pages = {1039--1044}, title = {Functional constraints vs. test compression in scan-based delay testing}, url = {https://doi.org/10.1109/DATE.2006.243927}, year = 2006 }
  Link
  https://doi.org/10.1109/DATE.2006.243927
3. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianBNOF06, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Nakasato, Masato and Ohtake, Satoshi and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2006), 4-6 October 2006, Arlington, Virginia, {USA}}, crossref = {DBLP:conf/dft/2006}, doi = {10.1109/DFT.2006.40}, pages = {274--279}, title = {Low-Cost Hardening of Image Processing Applications Against Soft Errors}, url = {https://doi.org/10.1109/DFT.2006.40}, year = 2006 }
  Link
  https://doi.org/10.1109/DFT.2006.40
4. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wcet/ReinekeWTWPEB06, abteilung = {hocos}, author = {Reineke, Jan and Wachter, Bj{\"{o}}rn and Thesing, Stephan and Wilhelm, Reinhard and Polian, Ilia and Eisinger, Jochen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {6th Intl. Workshop on Worst-Case Execution Time {(WCET)} Analysis, July 4, 2006, Dresden, Germany}, crossref = {DBLP:conf/wcet/2006}, title = {A Definition and Classification of Timing Anomalies}, url = {http://drops.dagstuhl.de/opus/volltexte/2006/671}, year = 2006 }
  Link
  http://drops.dagstuhl.de/opus/volltexte/2006/671
5. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KunduP06, abteilung = {hocos}, author = {Kundu, Sandip and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th {IEEE} International On-Line Testing Symposium {(IOLTS} 2006), 10-12 July 2006, Como, Italy}, crossref = {DBLP:conf/iolts/2006}, doi = {10.1109/IOLTS.2006.10}, pages = {105--110}, title = {An Improved Technique for Reducing False Alarms Due to Soft Errors}, url = {https://doi.org/10.1109/IOLTS.2006.10}, year = 2006 }
  Link
  https://doi.org/10.1109/IOLTS.2006.10
6. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tvlsi/TangWEPBSHW06, abteilung = {hocos}, author = {Tang, Yuyi and Wunderlich, Hans{-}Joachim and Engelke, Piet and Polian, Ilia and Becker, Bernd and Schl{\"{o}}ffel, J{\"{u}}rgen and Hapke, Friedrich and Wittke, Michael}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TVLSI.2005.863742}, journal = {{IEEE} Trans. {VLSI} Syst.}, number = 2, pages = {193--202}, title = {X-masking during logic {BIST} and its impact on defect coverage}, url = {https://doi.org/10.1109/TVLSI.2005.863742}, volume = 14, year = 2006 }
  Link
  https://doi.org/10.1109/TVLSI.2005.863742
7. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/EngelkePRB06, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-006-6392-x}, journal = {J. Electronic Testing}, number = 1, pages = {61--69}, title = {Automatic Test Pattern Generation for Resistive Bridging Faults}, url = {https://doi.org/10.1007/s10836-006-6392-x}, volume = 22, year = 2006 }
  Link
  https://doi.org/10.1007/s10836-006-6392-x
8. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRB06, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2006.871626}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 10, pages = {2181--2192}, title = {Simulating Resistive-Bridging and Stuck-At Faults}, url = {https://doi.org/10.1109/TCAD.2006.871626}, volume = 25, year = 2006 }
  Link
  https://doi.org/10.1109/TCAD.2006.871626
9. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/EisingerPBMTW06, abteilung = {hocos}, author = {Eisinger, Jochen and Polian, Ilia and Becker, Bernd and Metzner, Alexander and Thesing, Stephan and Wilhelm, Reinhard}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 9th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2006), Prague, Czech Republic, April 18-21, 2006}, crossref = {DBLP:conf/ddecs/2006}, doi = {10.1109/DDECS.2006.1649563}, pages = {15--20}, title = {Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis}, url = {https://doi.org/10.1109/DDECS.2006.1649563}, year = 2006 }
  Link
  https://doi.org/10.1109/DDECS.2006.1649563
10. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iccd/PolianCKB06, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {24th International Conference on Computer Design {(ICCD} 2006), 1-4 October 2006, San Jose, CA, {USA}}, crossref = {DBLP:conf/iccd/2006}, doi = {10.1109/ICCD.2006.4380824}, pages = {243--250}, title = {Power Droop Testing}, url = {https://doi.org/10.1109/ICCD.2006.4380824}, year = 2006 }
  Link
  https://doi.org/10.1109/ICCD.2006.4380824
11. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tcad/EngelkePRB06, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TCAD.2006.871626}, journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems}, number = 10, pages = {2181--2192}, title = {Simulating Resistive-Bridging and Stuck-At Faults}, url = {https://doi.org/10.1109/TCAD.2006.871626}, volume = 25, year = 2006 }
  Link
  https://doi.org/10.1109/TCAD.2006.871626
12. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/tvlsi/TangWEPBSHW06, abteilung = {hocos}, author = {Tang, Yuyi and Wunderlich, Hans{-}Joachim and Engelke, Piet and Polian, Ilia and Becker, Bernd and Schl{\"{o}}ffel, J{\"{u}}rgen and Hapke, Friedrich and Wittke, Michael}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1109/TVLSI.2005.863742}, journal = {{IEEE} Trans. {VLSI} Syst.}, number = 2, pages = {193--202}, title = {X-masking during logic {BIST} and its impact on defect coverage}, url = {https://doi.org/10.1109/TVLSI.2005.863742}, volume = 14, year = 2006 }
  Link
  https://doi.org/10.1109/TVLSI.2005.863742
13. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ddecs/EisingerPBMTW06, abteilung = {hocos}, author = {Eisinger, Jochen and Polian, Ilia and Becker, Bernd and Metzner, Alexander and Thesing, Stephan and Wilhelm, Reinhard}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the 9th {IEEE} Workshop on Design {\&} Diagnostics of Electronic Circuits {\&} Systems {(DDECS} 2006), Prague, Czech Republic, April 18-21, 2006}, crossref = {DBLP:conf/ddecs/2006}, doi = {10.1109/DDECS.2006.1649563}, pages = {15--20}, title = {Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis}, url = {https://doi.org/10.1109/DDECS.2006.1649563}, year = 2006 }
  Link
  https://doi.org/10.1109/DDECS.2006.1649563
14. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianF06, abteilung = {hocos}, author = {Polian, Ilia and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, crossref = {DBLP:conf/date/2006p}, doi = {10.1109/DATE.2006.243927}, pages = {1039--1044}, title = {Functional constraints vs. test compression in scan-based delay testing}, url = {https://doi.org/10.1109/DATE.2006.243927}, year = 2006 }
  Link
  https://doi.org/10.1109/DATE.2006.243927
15. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/wcet/ReinekeWTWPEB06, abteilung = {hocos}, author = {Reineke, Jan and Wachter, Bj{\"{o}}rn and Thesing, Stephan and Wilhelm, Reinhard and Polian, Ilia and Eisinger, Jochen and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {6th Intl. Workshop on Worst-Case Execution Time {(WCET)} Analysis, July 4, 2006, Dresden, Germany}, crossref = {DBLP:conf/wcet/2006}, title = {A Definition and Classification of Timing Anomalies}, url = {http://drops.dagstuhl.de/opus/volltexte/2006/671}, year = 2006 }
  Link
  http://drops.dagstuhl.de/opus/volltexte/2006/671
16. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/dft/PolianBNOF06, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Nakasato, Masato and Ohtake, Satoshi and Fujiwara, Hideo}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {21th {IEEE} International Symposium on Defect and Fault-Tolerance in {VLSI} Systems {(DFT} 2006), 4-6 October 2006, Arlington, Virginia, {USA}}, crossref = {DBLP:conf/dft/2006}, doi = {10.1109/DFT.2006.40}, pages = {274--279}, title = {Low-Cost Hardening of Image Processing Applications Against Soft Errors}, url = {https://doi.org/10.1109/DFT.2006.40}, year = 2006 }
  Link
  https://doi.org/10.1109/DFT.2006.40
17. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/KunduP06, abteilung = {hocos}, author = {Kundu, Sandip and Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {12th {IEEE} International On-Line Testing Symposium {(IOLTS} 2006), 10-12 July 2006, Como, Italy}, crossref = {DBLP:conf/iolts/2006}, doi = {10.1109/IOLTS.2006.10}, pages = {105--110}, title = {An Improved Technique for Reducing False Alarms Due to Soft Errors}, url = {https://doi.org/10.1109/IOLTS.2006.10}, year = 2006 }
  Link
  https://doi.org/10.1109/IOLTS.2006.10
18. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/EngelkePRB06, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-006-6392-x}, journal = {J. Electronic Testing}, number = 1, pages = {61--69}, title = {Automatic Test Pattern Generation for Resistive Bridging Faults}, url = {https://doi.org/10.1007/s10836-006-6392-x}, volume = 22, year = 2006 }
  Link
  https://doi.org/10.1007/s10836-006-6392-x
2005
1. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KunduEPB05, abteilung = {hocos}, author = {Kundu, Sandip and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, crossref = {DBLP:conf/ats/2005}, doi = {10.1109/ATS.2005.83}, pages = {266--271}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/ATS.2005.83}, year = 2005 }
  Link
  https://doi.org/10.1109/ATS.2005.83
2. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/PolianHKB05, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005, Austin, TX, USA, November 8-10, 2005}, crossref = {DBLP:conf/itc/2005}, doi = {10.1109/TEST.2005.1584070}, pages = 10, title = {Transient fault characterization in dynamic noisy environments}, url = {https://doi.org/10.1109/TEST.2005.1584070}, year = 2005 }
  Link
  https://doi.org/10.1109/TEST.2005.1584070
3. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianCB05, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2005), 7-11 March 2005, Munich, Germany}, crossref = {DBLP:conf/date/2005}, doi = {10.1109/DATE.2005.144}, pages = {1124--1129}, title = {Evolutionary Optimization in Code-Based Test Compression}, url = {https://doi.org/10.1109/DATE.2005.144}, year = 2005 }
  Link
  https://doi.org/10.1109/DATE.2005.144
4. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian05, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.47.3.172.65613}, journal = {it - Information Technology}, number = 3, pages = {172--174}, title = {Nichtstandardfehlermodelle f{\"{u}}r digitale Logikschaltkreise: Simulation, pr{\"{u}}fgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications)}, url = {https://doi.org/10.1524/itit.47.3.172.65613}, volume = 47, year = 2005 }
  Link
  https://doi.org/10.1524/itit.47.3.172.65613
5. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PolianFBH05, abteilung = {hocos}, author = {Polian, Ilia and Fiehn, Thomas and Becker, Bernd and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, crossref = {DBLP:conf/ats/2005}, doi = {10.1109/ATS.2005.9}, pages = {422--427}, title = {A Family of Logical Fault Models for Reversible Circuits}, url = {https://doi.org/10.1109/ATS.2005.9}, year = 2005 }
  Link
  https://doi.org/10.1109/ATS.2005.9
6. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianKGERB05, abteilung = {hocos}, author = {Polian, Ilia and Kundu, Sandip and Galli{\`{e}}re, Jean Marc and Engelke, Piet and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm Springs, CA, {USA}}, crossref = {DBLP:conf/vts/2005}, doi = {10.1109/VTS.2005.72}, pages = {343--348}, title = {Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies}, url = {https://doi.org/10.1109/VTS.2005.72}, year = 2005 }
  Link
  https://doi.org/10.1109/VTS.2005.72
7. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianERB05, abteilung = {hocos}, author = {Polian, Ilia and Engelke, Piet and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-005-5287-6}, journal = {J. Electronic Testing}, number = 1, pages = {57--69}, title = {Modeling Feedback Bridging Faults with Non-Zero Resistance}, url = {https://doi.org/10.1007/s10836-005-5287-6}, volume = 21, year = 2005 }
  Link
  https://doi.org/10.1007/s10836-005-5287-6
8. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianERB05, abteilung = {hocos}, author = {Polian, Ilia and Engelke, Piet and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1007/s10836-005-5287-6}, journal = {J. Electronic Testing}, number = 1, pages = {57--69}, title = {Modeling Feedback Bridging Faults with Non-Zero Resistance}, url = {https://doi.org/10.1007/s10836-005-5287-6}, volume = 21, year = 2005 }
  Link
  https://doi.org/10.1007/s10836-005-5287-6
9. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PolianFBH05, abteilung = {hocos}, author = {Polian, Ilia and Fiehn, Thomas and Becker, Bernd and Hayes, John P.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, crossref = {DBLP:conf/ats/2005}, doi = {10.1109/ATS.2005.9}, pages = {422--427}, title = {A Family of Logical Fault Models for Reversible Circuits}, url = {https://doi.org/10.1109/ATS.2005.9}, year = 2005 }
  Link
  https://doi.org/10.1109/ATS.2005.9
10. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianCB05, abteilung = {hocos}, author = {Polian, Ilia and Czutro, Alejandro and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2005), 7-11 March 2005, Munich, Germany}, crossref = {DBLP:conf/date/2005}, doi = {10.1109/DATE.2005.144}, pages = {1124--1129}, title = {Evolutionary Optimization in Code-Based Test Compression}, url = {https://doi.org/10.1109/DATE.2005.144}, year = 2005 }
  Link
  https://doi.org/10.1109/DATE.2005.144
11. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/it/Polian05, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1524/itit.47.3.172.65613}, journal = {it - Information Technology}, number = 3, pages = {172--174}, title = {Nichtstandardfehlermodelle f{\"{u}}r digitale Logikschaltkreise: Simulation, pr{\"{u}}fgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications)}, url = {https://doi.org/10.1524/itit.47.3.172.65613}, volume = 47, year = 2005 }
  Link
  https://doi.org/10.1524/itit.47.3.172.65613
12. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianKGERB05, abteilung = {hocos}, author = {Polian, Ilia and Kundu, Sandip and Galli{\`{e}}re, Jean Marc and Engelke, Piet and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm Springs, CA, {USA}}, crossref = {DBLP:conf/vts/2005}, doi = {10.1109/VTS.2005.72}, pages = {343--348}, title = {Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies}, url = {https://doi.org/10.1109/VTS.2005.72}, year = 2005 }
  Link
  https://doi.org/10.1109/VTS.2005.72
13. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/KunduEPB05, abteilung = {hocos}, author = {Kundu, Sandip and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta, India}, crossref = {DBLP:conf/ats/2005}, doi = {10.1109/ATS.2005.83}, pages = {266--271}, title = {On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing}, url = {https://doi.org/10.1109/ATS.2005.83}, year = 2005 }
  Link
  https://doi.org/10.1109/ATS.2005.83
14. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/PolianHKB05, abteilung = {hocos}, author = {Polian, Ilia and Hayes, John P. and Kundu, Sandip and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005, Austin, TX, USA, November 8-10, 2005}, crossref = {DBLP:conf/itc/2005}, doi = {10.1109/TEST.2005.1584070}, pages = 10, title = {Transient fault characterization in dynamic noisy environments}, url = {https://doi.org/10.1109/TEST.2005.1584070}, year = 2005 }
  Link
  https://doi.org/10.1109/TEST.2005.1584070
2004
1. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
  - BibTeX
  BibTeX
  @inbook{ilia2004nonstandard, abteilung = {hocos}, address = {Düsseldorf}, author = {Ilia, Polian}, isbn = {3-18-337720-9}, month = mar, number = 377, pages = 218, publisher = {VDI-Verlag}, series = {VDI Fortschritt-Berichte}, title = {On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications.}, volume = 20, year = 2004 }
2. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
  - BibTeX
  BibTeX
  @inbook{ilia2004nonstandard, abteilung = {hocos}, address = {Düsseldorf}, author = {Ilia, Polian}, isbn = {3-18-337720-9}, month = mar, number = 377, pages = 218, publisher = {VDI-Verlag}, series = {VDI Fortschritt-Berichte}, title = {On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications.}, volume = 20, year = 2004 }
3. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/TangWVHWEPB04, abteilung = {hocos}, author = {Tang, Yuyi and Wunderlich, Hans{-}Joachim and Vranken, Harald P. E. and Hapke, Friedrich and Wittke, Michael and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October 26-28, 2004, Charlotte, NC, {USA}}, crossref = {DBLP:conf/itc/2004}, doi = {10.1109/TEST.2004.1386980}, pages = {442--451}, title = {X-Masking During Logic {BIST} and Its Impact on Defect Coverage}, url = {https://doi.org/10.1109/TEST.2004.1386980}, year = 2004 }
  Link
  https://doi.org/10.1109/TEST.2004.1386980
4. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HayesPB04, abteilung = {hocos}, author = {Hayes, John P. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting, Taiwan}, crossref = {DBLP:conf/ats/2004}, doi = {10.1109/ATS.2004.84}, pages = {100--105}, title = {Testing for Missing-Gate Faults in Reversible Circuits}, url = {https://doi.org/10.1109/ATS.2004.84}, year = 2004 }
  Link
  https://doi.org/10.1109/ATS.2004.84
5. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/EngelkePRB04, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {9th European Test Symposium, {ETS} 2004, Ajaccio, France, May 23-26, 2004}, crossref = {DBLP:conf/ets/2004}, doi = {10.1109/ETSYM.2004.1347652}, pages = {160--165}, title = {Automatic test pattern generation for resistive bridging faults}, url = {https://doi.org/10.1109/ETSYM.2004.1347652}, year = 2004 }
  Link
  https://doi.org/10.1109/ETSYM.2004.1347652
6. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianB04, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/B:JETT.0000023681.25483.59}, journal = {J. Electronic Testing}, number = 2, pages = {181--197}, title = {Scalable Delay Fault {BIST} for Use with Low-Cost {ATE}}, url = {https://doi.org/10.1023/B:JETT.0000023681.25483.59}, volume = 20, year = 2004 }
  Link
  https://doi.org/10.1023/B:JETT.0000023681.25483.59
7. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/EngelkePRSB04, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} {VLSI} Test Symposium {(VTS} 2004), 25-29 April 2004, Napa Valley, CA, {USA}}, crossref = {DBLP:conf/vts/2004}, doi = {10.1109/VTEST.2004.1299240}, pages = {171--178}, title = {The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults}, url = {https://doi.org/10.1109/VTEST.2004.1299240}, year = 2004 }
  Link
  https://doi.org/10.1109/VTEST.2004.1299240
8. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/BeckerBEFHHHKNPW04, abteilung = {hocos}, author = {Becker, Bernd and Behle, Markus and Eisenbrand, Friedrich and Fr{\"{a}}nzle, Martin and Herbstritt, Marc and Herde, Christian and Hoffmann, J{\"{o}}rg and Kr{\"{o}}ning, Daniel and Nebel, Bernhard and Polian, Ilia and Wimmer, Ralf}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004}, crossref = {DBLP:conf/mbmv/2004}, pages = {65--75}, title = {Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems}, year = 2004 }
9. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/BeckerBEFHHHKNPW04, abteilung = {hocos}, author = {Becker, Bernd and Behle, Markus and Eisenbrand, Friedrich and Fr{\"{a}}nzle, Martin and Herbstritt, Marc and Herde, Christian and Hoffmann, J{\"{o}}rg and Kr{\"{o}}ning, Daniel and Nebel, Bernhard and Polian, Ilia and Wimmer, Ralf}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004}, crossref = {DBLP:conf/mbmv/2004}, pages = {65--75}, title = {Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems}, year = 2004 }
10. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianB04, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/B:JETT.0000023681.25483.59}, journal = {J. Electronic Testing}, number = 2, pages = {181--197}, title = {Scalable Delay Fault {BIST} for Use with Low-Cost {ATE}}, url = {https://doi.org/10.1023/B:JETT.0000023681.25483.59}, volume = 20, year = 2004 }
  Link
  https://doi.org/10.1023/B:JETT.0000023681.25483.59
11. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ets/EngelkePRB04, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {9th European Test Symposium, {ETS} 2004, Ajaccio, France, May 23-26, 2004}, crossref = {DBLP:conf/ets/2004}, doi = {10.1109/ETSYM.2004.1347652}, pages = {160--165}, title = {Automatic test pattern generation for resistive bridging faults}, url = {https://doi.org/10.1109/ETSYM.2004.1347652}, year = 2004 }
  Link
  https://doi.org/10.1109/ETSYM.2004.1347652
12. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/TangWVHWEPB04, abteilung = {hocos}, author = {Tang, Yuyi and Wunderlich, Hans{-}Joachim and Vranken, Harald P. E. and Hapke, Friedrich and Wittke, Michael and Engelke, Piet and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October 26-28, 2004, Charlotte, NC, {USA}}, crossref = {DBLP:conf/itc/2004}, doi = {10.1109/TEST.2004.1386980}, pages = {442--451}, title = {X-Masking During Logic {BIST} and Its Impact on Defect Coverage}, url = {https://doi.org/10.1109/TEST.2004.1386980}, year = 2004 }
  Link
  https://doi.org/10.1109/TEST.2004.1386980
13. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/EngelkePRSB04, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Seshadri, Bharath and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {22nd {IEEE} {VLSI} Test Symposium {(VTS} 2004), 25-29 April 2004, Napa Valley, CA, {USA}}, crossref = {DBLP:conf/vts/2004}, doi = {10.1109/VTEST.2004.1299240}, pages = {171--178}, title = {The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults}, url = {https://doi.org/10.1109/VTEST.2004.1299240}, year = 2004 }
  Link
  https://doi.org/10.1109/VTEST.2004.1299240
14. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/HayesPB04, abteilung = {hocos}, author = {Hayes, John P. and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting, Taiwan}, crossref = {DBLP:conf/ats/2004}, doi = {10.1109/ATS.2004.84}, pages = {100--105}, title = {Testing for Missing-Gate Faults in Reversible Circuits}, url = {https://doi.org/10.1109/ATS.2004.84}, year = 2004 }
  Link
  https://doi.org/10.1109/ATS.2004.84
2003
1. Reducing ATE Cost in System-on-Chip Test. Ilia Polian and Bernd Becker. In IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 2003, pp. 337--342.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/vlsi/PolianB03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003}, crossref = {DBLP:conf/vlsi/2003soc}, pages = {337--342}, title = {Reducing {ATE} Cost in System-on-Chip Test}, year = 2003 }
2. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, 2003, pp. 11184--11185. DOI: https://doi.org/10.1109/DATE.2003.10051
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianBR03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Reddy, Sudhakar M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2003), 3-7 March 2003, Munich, Germany}, crossref = {DBLP:conf/date/2003}, doi = {10.1109/DATE.2003.10051}, pages = {11184--11185}, title = {Evolutionary Optimization of Markov Sources for Pseudo Random Scan {BIST}}, url = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10051}, year = 2003 }
  Link
  http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10051
3. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. Jonathan Bradford; Hartmut Delong; Ilia Polian and Bernd Becker. J. Electronic Testing 19, 4 (2003), pp. 387--395. DOI: https://doi.org/10.1023/A:1024635824944
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/BradfordDPB03, abteilung = {hocos}, author = {Bradford, Jonathan and Delong, Hartmut and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/A:1024635824944}, journal = {J. Electronic Testing}, number = 4, pages = {387--395}, title = {Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting}, url = {https://doi.org/10.1023/A:1024635824944}, volume = 19, year = 2003 }
  Link
  https://doi.org/10.1023/A:1024635824944
4. On non-standard fault models for logic digital circuits. Ilia Polian. In Ausgezeichnete Informatikdissertationen 2003, 2003, pp. 169--178.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/gi/Polian03, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Ausgezeichnete Informatikdissertationen 2003}, crossref = {DBLP:conf/gi/2003diss}, pages = {169--178}, title = {On non-standard fault models for logic digital circuits}, url = {http://subs.emis.de/LNI/Dissertation/Dissertation4/article21.html}, year = 2003 }
  Link
  http://subs.emis.de/LNI/Dissertation/Dissertation4/article21.html
5. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianB03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/A:1021991828423}, journal = {J. Electronic Testing}, number = 1, pages = {37--48}, title = {Multiple Scan Chain Design for Two-Pattern Testing}, url = {https://doi.org/10.1023/A:1021991828423}, volume = 19, year = 2003 }
  Link
  https://doi.org/10.1023/A:1021991828423
6. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25--44. DOI: https://doi.org/10.1016/S0167-9260(03)00003-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/integration/PolianGB03, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/S0167-9260(03)00003-8}, journal = {Integration}, number = 1, pages = {25--44}, title = {Pattern-based verification of connections to intellectual property cores}, url = {https://doi.org/10.1016/S0167-9260(03)00003-8}, volume = 35, year = 2003 }
  Link
  https://doi.org/10.1016/S0167-9260(03)00003-8
7. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/PolianGB03, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003}, crossref = {DBLP:conf/mbmv/2003}, pages = {164--173}, title = {The Case for 2-POF}, year = 2003 }
8. Simulating Resistive Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 1051--1059. DOI: https://doi.org/10.1109/TEST.2003.1271093
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/EngelkePRB03, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, {USA}}, crossref = {DBLP:conf/itc/2003}, doi = {10.1109/TEST.2003.1271093}, pages = {1051--1059}, title = {Simulating Resistive Bridging and Stuck-At Faults}, url = {https://doi.org/10.1109/TEST.2003.1271093}, year = 2003 }
  Link
  https://doi.org/10.1109/TEST.2003.1271093
9. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25--44. DOI: https://doi.org/10.1016/S0167-9260(03)00003-8
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/integration/PolianGB03, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1016/S0167-9260(03)00003-8}, journal = {Integration}, number = 1, pages = {25--44}, title = {Pattern-based verification of connections to intellectual property cores}, url = {https://doi.org/10.1016/S0167-9260(03)00003-8}, volume = 35, year = 2003 }
  Link
  https://doi.org/10.1016/S0167-9260(03)00003-8
10. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/PolianGB03, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003}, crossref = {DBLP:conf/mbmv/2003}, pages = {164--173}, title = {The Case for 2-POF}, year = 2003 }
11. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, 2003, pp. 11184--11185. DOI: https://doi.org/10.1109/DATE.2003.10051
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/date/PolianBR03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd and Reddy, Sudhakar M.}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2003), 3-7 March 2003, Munich, Germany}, crossref = {DBLP:conf/date/2003}, doi = {10.1109/DATE.2003.10051}, pages = {11184--11185}, title = {Evolutionary Optimization of Markov Sources for Pseudo Random Scan {BIST}}, url = {http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10051}, year = 2003 }
  Link
  http://doi.ieeecomputersociety.org/10.1109/DATE.2003.10051
12. Reducing ATE Cost in System-on-Chip Test. Ilia Polian and Bernd Becker. In IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 2003, pp. 337--342.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/vlsi/PolianB03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003}, crossref = {DBLP:conf/vlsi/2003soc}, pages = {337--342}, title = {Reducing {ATE} Cost in System-on-Chip Test}, year = 2003 }
13. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. Jonathan Bradford; Hartmut Delong; Ilia Polian and Bernd Becker. J. Electronic Testing 19, 4 (2003), pp. 387--395. DOI: https://doi.org/10.1023/A:1024635824944
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/BradfordDPB03, abteilung = {hocos}, author = {Bradford, Jonathan and Delong, Hartmut and Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/A:1024635824944}, journal = {J. Electronic Testing}, number = 4, pages = {387--395}, title = {Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting}, url = {https://doi.org/10.1023/A:1024635824944}, volume = 19, year = 2003 }
  Link
  https://doi.org/10.1023/A:1024635824944
14. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423
  - BibTeX
  - Link
  BibTeX
  @article{DBLP:journals/et/PolianB03, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, doi = {10.1023/A:1021991828423}, journal = {J. Electronic Testing}, number = 1, pages = {37--48}, title = {Multiple Scan Chain Design for Two-Pattern Testing}, url = {https://doi.org/10.1023/A:1021991828423}, volume = 19, year = 2003 }
  Link
  https://doi.org/10.1023/A:1021991828423
15. Simulating Resistive Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 1051--1059. DOI: https://doi.org/10.1109/TEST.2003.1271093
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/itc/EngelkePRB03, abteilung = {hocos}, author = {Engelke, Piet and Polian, Ilia and Renovell, Michel and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, {USA}}, crossref = {DBLP:conf/itc/2003}, doi = {10.1109/TEST.2003.1271093}, pages = {1051--1059}, title = {Simulating Resistive Bridging and Stuck-At Faults}, url = {https://doi.org/10.1109/TEST.2003.1271093}, year = 2003 }
  Link
  https://doi.org/10.1109/TEST.2003.1271093
16. On non-standard fault models for logic digital circuits. Ilia Polian. In Ausgezeichnete Informatikdissertationen 2003, 2003, pp. 169--178.
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/gi/Polian03, abteilung = {hocos}, author = {Polian, Ilia}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Ausgezeichnete Informatikdissertationen 2003}, crossref = {DBLP:conf/gi/2003diss}, pages = {169--178}, title = {On non-standard fault models for logic digital circuits}, url = {http://subs.emis.de/LNI/Dissertation/Dissertation4/article21.html}, year = 2003 }
  Link
  http://subs.emis.de/LNI/Dissertation/Dissertation4/article21.html
2002
1. Stop & Go BIST. Ilia Polian and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 147--151. DOI: https://doi.org/10.1109/OLT.2002.1030198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianB02, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002), 8-10 July 2002, Isle of Bendor, France}, crossref = {DBLP:conf/iolts/2002}, doi = {10.1109/OLT.2002.1030198}, pages = {147--151}, title = {Stop {\&} Go {BIST}}, url = {https://doi.org/10.1109/OLT.2002.1030198}, year = 2002 }
  Link
  https://doi.org/10.1109/OLT.2002.1030198
2. Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. Ilia Polian; Piet Engelke and Bernd Becker. In 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, 2002, pp. 216--223. DOI: https://doi.org/10.1109/ISMVL.2002.1011092
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ismvl/PolianEB02, abteilung = {hocos}, author = {Polian, Ilia and Engelke, Piet and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL} 2002), May 15-18, 2002, Boston, Massachusetts, {USA}}, crossref = {DBLP:conf/ismvl/2002}, doi = {10.1109/ISMVL.2002.1011092}, pages = {216--223}, title = {Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics}, url = {https://doi.org/10.1109/ISMVL.2002.1011092}, year = 2002 }
  Link
  https://doi.org/10.1109/ISMVL.2002.1011092
3. Sequential n -Detection Criteria: Keep It Simple. Ilia Polian; Martin Keim; Nicolai Mallig and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 189. DOI: https://doi.org/10.1109/OLT.2002.1030213
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianKMB02, abteilung = {hocos}, author = {Polian, Ilia and Keim, Martin and Mallig, Nicolai and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002), 8-10 July 2002, Isle of Bendor, France}, crossref = {DBLP:conf/iolts/2002}, doi = {10.1109/OLT.2002.1030213}, pages = 189, title = {Sequential n -Detection Criteria: Keep It Simple}, url = {https://doi.org/10.1109/OLT.2002.1030213}, year = 2002 }
  Link
  https://doi.org/10.1109/OLT.2002.1030213
4. Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Ilia Polian; Irith Pomeranz and Bernd Becker. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002, pp. 2--14. DOI: https://doi.org/10.1109/ATS.2002.1181677
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PolianPB02, abteilung = {hocos}, author = {Polian, Ilia and Pomeranz, Irith and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam, {USA}}, crossref = {DBLP:conf/ats/2002}, doi = {10.1109/ATS.2002.1181677}, pages = {2--14}, title = {Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests}, url = {https://doi.org/10.1109/ATS.2002.1181677}, year = 2002 }
  Link
  https://doi.org/10.1109/ATS.2002.1181677
5. Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Ilia Polian; Irith Pomeranz and Bernd Becker. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002, pp. 2--14. DOI: https://doi.org/10.1109/ATS.2002.1181677
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PolianPB02, abteilung = {hocos}, author = {Polian, Ilia and Pomeranz, Irith and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam, {USA}}, crossref = {DBLP:conf/ats/2002}, doi = {10.1109/ATS.2002.1181677}, pages = {2--14}, title = {Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests}, url = {https://doi.org/10.1109/ATS.2002.1181677}, year = 2002 }
  Link
  https://doi.org/10.1109/ATS.2002.1181677
6. Sequential n -Detection Criteria: Keep It Simple. Ilia Polian; Martin Keim; Nicolai Mallig and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 189. DOI: https://doi.org/10.1109/OLT.2002.1030213
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianKMB02, abteilung = {hocos}, author = {Polian, Ilia and Keim, Martin and Mallig, Nicolai and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002), 8-10 July 2002, Isle of Bendor, France}, crossref = {DBLP:conf/iolts/2002}, doi = {10.1109/OLT.2002.1030213}, pages = 189, title = {Sequential n -Detection Criteria: Keep It Simple}, url = {https://doi.org/10.1109/OLT.2002.1030213}, year = 2002 }
  Link
  https://doi.org/10.1109/OLT.2002.1030213
7. Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. Ilia Polian; Piet Engelke and Bernd Becker. In 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, 2002, pp. 216--223. DOI: https://doi.org/10.1109/ISMVL.2002.1011092
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ismvl/PolianEB02, abteilung = {hocos}, author = {Polian, Ilia and Engelke, Piet and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL} 2002), May 15-18, 2002, Boston, Massachusetts, {USA}}, crossref = {DBLP:conf/ismvl/2002}, doi = {10.1109/ISMVL.2002.1011092}, pages = {216--223}, title = {Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics}, url = {https://doi.org/10.1109/ISMVL.2002.1011092}, year = 2002 }
  Link
  https://doi.org/10.1109/ISMVL.2002.1011092
8. Stop & Go BIST. Ilia Polian and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 147--151. DOI: https://doi.org/10.1109/OLT.2002.1030198
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/iolts/PolianB02, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002), 8-10 July 2002, Isle of Bendor, France}, crossref = {DBLP:conf/iolts/2002}, doi = {10.1109/OLT.2002.1030198}, pages = {147--151}, title = {Stop {\&} Go {BIST}}, url = {https://doi.org/10.1109/OLT.2002.1030198}, year = 2002 }
  Link
  https://doi.org/10.1109/OLT.2002.1030198
2001
1. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, 2001, pp. 88--93. DOI: https://doi.org/10.1109/VTS.2001.923423
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianB01, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, {USA}}, crossref = {DBLP:conf/vts/2001}, doi = {10.1109/VTS.2001.923423}, pages = {88--93}, title = {Multiple Scan Chain Design for Two-Pattern Testing}, url = {https://doi.org/10.1109/VTS.2001.923423}, year = 2001 }
  Link
  https://doi.org/10.1109/VTS.2001.923423
2. Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Meißen, Germany, February 19-21, 2001, 2001, pp. 111--120.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/PolianGB01, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Mei{\ss}en, Germany, February 19-21, 2001}, crossref = {DBLP:conf/mbmv/2001}, pages = {111--120}, title = {Efficient Pattern-Based Verification of Connections to Intellectual Property Cores}, year = 2001 }
3. Efficient Pattern-Based Verification of Connections to IP Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001, pp. 443--448. DOI: https://doi.org/10.1109/ATS.2001.990324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PoliaGB01, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto, Japan}, crossref = {DBLP:conf/ats/2001}, doi = {10.1109/ATS.2001.990324}, pages = {443--448}, title = {Efficient Pattern-Based Verification of Connections to {IP} Cores}, url = {https://doi.org/10.1109/ATS.2001.990324}, year = 2001 }
  Link
  https://doi.org/10.1109/ATS.2001.990324
4. Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Meißen, Germany, February 19-21, 2001, 2001, pp. 111--120.
  - BibTeX
  BibTeX
  @inproceedings{DBLP:conf/mbmv/PolianGB01, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Mei{\ss}en, Germany, February 19-21, 2001}, crossref = {DBLP:conf/mbmv/2001}, pages = {111--120}, title = {Efficient Pattern-Based Verification of Connections to Intellectual Property Cores}, year = 2001 }
5. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, 2001, pp. 88--93. DOI: https://doi.org/10.1109/VTS.2001.923423
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/vts/PolianB01, abteilung = {hocos}, author = {Polian, Ilia and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, {USA}}, crossref = {DBLP:conf/vts/2001}, doi = {10.1109/VTS.2001.923423}, pages = {88--93}, title = {Multiple Scan Chain Design for Two-Pattern Testing}, url = {https://doi.org/10.1109/VTS.2001.923423}, year = 2001 }
  Link
  https://doi.org/10.1109/VTS.2001.923423
6. Efficient Pattern-Based Verification of Connections to IP Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001, pp. 443--448. DOI: https://doi.org/10.1109/ATS.2001.990324
  - BibTeX
  - Link
  BibTeX
  @inproceedings{DBLP:conf/ats/PoliaGB01, abteilung = {hocos}, author = {Polian, Ilia and G{\"{u}}nther, Wolfgang and Becker, Bernd}, bibsource = {dblp computer science bibliography, https://dblp.org}, booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto, Japan}, crossref = {DBLP:conf/ats/2001}, doi = {10.1109/ATS.2001.990324}, pages = {443--448}, title = {Efficient Pattern-Based Verification of Connections to {IP} Cores}, url = {https://doi.org/10.1109/ATS.2001.990324}, year = 2001 }
  Link
  https://doi.org/10.1109/ATS.2001.990324

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