Publications

Abstract

Quantum algorithms promise quadratic or exponential speedups for applications in cryptography, chemistry and material sciences. The topologies of today's quantum computers offer limited connectivity, leading to significant overheads for implementing such quantum algorithms. One-dimensional topology displacements that remedy these limits have been recently demonstrated for architectures based on Rydberg atoms, and they are possible in principle in photonic and ion trap architectures. We present the first optimal quantum circuit-to-architecture mapping algorithm that exploits such one-dimensional topology displacements. We benchmark our method on quantum circuits with up to 15 qubits and investigate the improvements compared with conventional mapping based on inserting swap gates into the quantum circuits. Depending on underlying technology parameters, our approach can decrease the quantum circuit depth by up to 58\% and increase the fidelity by up to 29\%. We also study runtime and fidelity requirements on one-dimensional displacements and swap gates to derive conditions under which one-dimensional topology displacements provide benefits.

Abstract

While scalable, fully error corrected quantum computing is years or even decades away, there is considerable interest in noisy intermediate-scale quantum computing (NISQ). In this paper, we introduce the ArsoNISQ framework that determines the tolerable error rate of a given quantum algorithm computation, i.e. quantum circuits, and the success probability of the computation given a success criterion and a NISQ computer. ArsoNISQ is based on simulations of quantum circuits subject to errors according to the Pauli error model. ArsoNISQ was evaluated on a set of quantum algorithms that can incur a quantum speedup or are otherwise relevant to NISQ computing. Despite optimistic expectations in recent literature, we did not observe quantum algorithms with intrinsic robustness, i.e. algorithms that tolerate one error on average, in this evaluation. The evaluation demonstrated, however, that the quantum circuit size sets an upper bound for its tolerable error rate and quantified the difference in tolerate error rates for quantum circuits of similar sizes. Thus, the framework can assist quantum algorithm developers in improving their implementation and selecting a suitable NISQ computing platform. Extrapolating the results into the quantum advantage regime suggests that the error rate of larger quantum computers must decrease substantially or active quantum error correction will need to be deployed for most of the evaluated algorithms

Abstract

First quantum computers very recently have demonstrated “quantum supremacy” or “quantum advantage”: Executing a computation that would have been impossible on a classical machine. Today’s quantum computers follow the NISQ paradigm: They exhibit error rates that are much higher than in conventional electronics and have insufficient quantum resources to support powerful error correction protocols. This raises questions which relevant computations are within the reach of NISQ architectures. Several “NISQ-era algorithms” are assumed to match the specifics of such computers; for instance, variational optimisers are based on intertwining relatively short quantum and classical computations, thus maximizing the chances of success. This paper will critically assess the promise and challenge of NISQ computing. What has this field achieved so far, what are we likely to achieve soon, where do we have to be skeptical and wait for the advent of larger-scale fully error-corrected architectures?

Abstract

Artificial intelligence (AI) algorithms achieve outstanding results in many application domains such as computer vision and natural language processing. The performance of AI models is the outcome of complex and costly model architecture design and training processes. Hence, it is paramount for model owners to protect their AI models from piracy – model cloning, illegitimate distribution and use. IP protection mechanisms have been applied to AI models, and in particular to deep neural networks, to verify the model ownership. State-of-the-art AI model ownership protection techniques have been surveyed. The pros and cons of AI model ownership protection have been reported. The majority of previous works are focused on watermarking, while more advanced methods such fingerprinting and attestation are promising but not yet explored in depth. This study has been concluded by discussing possible research directions in the area.

Abstract

Stochastic computing (SC) is a promising computation technique for applications with huge numbers of individually simple operations. One of the main application targets for SC is the design of convolutional neural networks (CNNs) due to their heavy reliance on multiply-accumulate operations that have compact and power-efficient SC realizations. We present a training optimization method that can improve the accuracy of SC-based CNNs significantly. Using regularization techniques in combination with a newly developed retraining algorithm, we enforce sparsity, reduce the number of required MUX-based additions, and thus minimize undesired downscaling. Our results show that the proposed regularized training procedure (RTP) can reduce the computation time of SC-based NNs by a factor of four without sacrificing classification accuracy while also reducing area in hardware implementations. These findings suggest that SC can be successfully applied to more powerful CNNs than previously thought possible, thus extending the range of potential uses of SC.

Abstract

Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.

Abstract

Today’s electronic systems must simultaneously fulfill strict requirements on security and reliability. In particular, their cryptographic modules are exposed to faults, which can be due to natural failures (e.g., radiation or electromagnetic noise) or malicious fault-injection attacks. We present an architecture based on a new class of error-detecting codes that combine robustness properties with a minimal distance. The new architecture guarantees (with some probability) the detection of faults injected by an intelligent and strategic adversary who can precisely control the disturbance. At the same time it supports automatic correction of low-multiplicity faults. To this end, we discuss an efficient technique to correct single nibble/byte errors while avoiding full syndrome analysis. We also examine a Compact Protection Code (CPC)-based system level fault manager that considers this code an inner code (and the CPC as its outer code). We report experimental results obtained by physical fault injection on the SAKURA-G FPGA board. The experimental results reconfirm the assumption that faults may cause an arbitrary number of bit flips. They indicate that a combined inner–outer coding scheme can significantly reduce the number of fault events that go undetected due to erroneous corrections of the inner code.

Abstract

Cryptographic hardware becomes increasingly vulnerable to physical attacks--both passive side-channel analysis and active fault injections--performed by skillful and well-equipped adversaries. In this paper, we introduce a technique that provides very high security against both types of attacks. It combines inner product masking (IPM), which offers higher-order side-channel attack resistance on word level and on bit level, with nonlinear security-oriented error-detection codes that provide robustness, i.e., strong detection guarantees for arbitrary faults. We prove that our scheme has the same security against side-channel attacks that an earlier, non-robust IPM-based solution has and in addition preserves robustness during addition and multiplication (and therefore arbitrary computations). Moreover, we prove that the information leakage from the checker is small and that the attack will be detected far before the attacker will gain significant information.

Abstract

On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.

Abstract

Modern electronic systems become evermore complex, yet remain modular, with integrated circuits (ICs) acting as versatile hardware components at their heart. Electronic design automation (EDA) for ICs has focused traditionally on power, performance, and area. However, given the rise of hardware-centric security threats, we believe that EDA must also adopt related notions like secure by design and secure composition of hardware. Despite various promising studies, we argue that some aspects still require more efforts, for example: effective means for compilation of assumptions and constraints for security schemes, all the way from the system level down to the "bare metal"; modeling, evaluation, and consideration of security-relevant metrics; or automated and holistic synthesis of various countermeasures, without inducing negative cross-effects.In this paper, we first introduce hardware security for the EDA community. Next we review prior (academic) art for EDA-driven security evaluation and implementation of countermeasures. We then discuss strategies and challenges for advancing research and development toward secure composition of circuits and systems.

Abstract

Image steganography can have legitimate uses, for example, augmenting an image with a watermark for copyright reasons, but can also be utilized for malicious purposes. We investigate the detection of malicious steganography using neural networkbased classification when images are transmitted through a noisy channel. Noise makes detection harder because the classifier must not only detect perturbations in the image but also decide whether they are due to the malicious steganographic modifications or due to natural noise. Our results show that reliable detection is possible even for state-of-the-art steganographic algorithms that insert stego bits not affecting an image’s visual quality. The detection accuracy is high (above 85%) if the payload, or the amount of the steganographic content in an image, exceeds a certain threshold. At the same time, noise critically affects the steganographic information being transmitted, both through desynchronization (destruction of information which bits of the image contain steganographic information) and by flipping these bits themselves. This will force the adversary to use a redundant encoding with a substantial number of error-correction bits for reliable transmission, making detection feasible even for small payloads.

Abstract

The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

Abstract

Fault attacks are an essential threat to security of cryptographic functions. This chapter focuses on underlying concepts of fault attacks on cryptographic circuit implementations. Rather than targeting a specific cipher, the presented approach aims at an automatic construction of fault attacks from the circuit description. A Boolean formula that describes the circuit operation and the fault injection is generated and handed over to a SAT solver; an adversary can deduce protected information, e.g., the secret key, from the solution. The chapter also includes a comparison of the described methodology with other existing fault attack frameworks that are not specifically targeted towards circuit implementations.

Abstract

Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.

Abstract

Fault simulation and ATPG are core algorithms in the context of digital hardware test. Their deployment for resistive fault models is challenging as the behavior of the defective circuit depends on the defect resistance and the number of possible resistances is infinite. In this chapter, we show that efficient fault simulation and ATPG algorithms are feasible for resistive bridging faults. Application of the algorithms to multi-million gate industrial circuits without sacrificing accuracy is demonstrated. We cover in detail the abstraction mechanisms required for the algorithms, the algorithms themselves and their optimizations. We also indicate how a resistive bridging fault framework can be employed for problems outside the classical test development.