HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing

This project aims to find novel abstraction and algorithm mapping methods to allow highly accurate timing and NFP-aware simulation of multi-million gate circuits on data-parallel architectures such as graphics processing units (GPUs). The expected dramatic speedup compared to the existing state-of-the-art allows fault simulation of millions of faults and thousands of patterns. The increased accuracy of the simulation results allow to optimize test patterns w.r.t. test power and small delay defect coverage in presence of power noise, clock skew or even circuit variations.

01.2015 - 12.2016, DAAD/JSPS PPP Japan Project: #57155440

The project in detail:

Variations and imperfections during manufacturing can result in small delay defects, which can point to underlying hardware marginalities that may degrade into early life failures. The detection of such small delay defects in conventional test schemes is highly difficult since the slack along sensitized paths is typically much larger than the defect size. In typical manufacturing tests the majority of small delay defects remains undetected, resulting in low quality and reliability for such mission-critical applications as implanted medical devices, aeronautic control units, car electronics, etc. Their detection can be facilitated by increasing the test clock frequency, called faster-than-at-speed test (FAST). However, operating the circuit at a frequency much higher than the nominal frequency increases power consumption and noise in the power and clock network. This threatens reliable fault detection and also causes over-testing of the circuit. To ensure the quality of a given test pattern set, it is not sufficient to simulate the circuit behavior at gate level. Instead, it is required to simulate timing models at lower abstraction level that reflect filtering, glitches and their impact on the stability of power supply. However, low-level approaches such as SPICE-simulation are inapplicable for large circuits and high number of patterns/faults due to the increasing runtime complexity.

In this work, innovative parallelized algorithms for simulation on graphics processing units (GPUs) shall be developed. By utilizing the many-core programming paradigm and exploiting multiple dimensions of parallelism found in circuit simulation, evaluation with full waveform granularity and support for highly accurate delay models will be enabled, therefore allowing for fast and accurate simulation of small delay faults.

Goals

The development of parallelized delay simulation methods that support non-functional properties (NFPs) with influence on the detection of small delay faults is the first objective of this proposal. The set of NFPs to be covered includes power noise, clock noise and skew, temperature and spatial model/layout dependencies of the chip. The second objective is the investigation of the correlation between layout structures and parasitic non-functional effects in a circuit, which requires the identification of critical structures that cause excessive delay variation during testing. In order to allow for an accurate simulation for larger circuits within reasonable time, evaluation has to be performed at different levels of abstraction. The third objective is the accurate simulation of faults and faulty circuit instances to assess the small delay fault coverage of a test pattern set. The proper and accurate modeling of fault mechanisms on a low abstraction level is crucial to represent realistic small delay defects. For this sequential behavior induced by resistive interconnect defects has to be considered. Moreover, the accuracy of scalar coverage metrics, which do not consider such accurate timing models or non-functional properties, is substantially increased. The high accuracy of such efficient fault simulation allows to assess the coverage of faster-than-at-speed tests considering NPFs for large circuit instances. As a fourth objective, this information will be used to improve the robustness of FAST patterns such that false positive and false negative test results are reduced or completely avoided.

Additional Information

This project is part of the German Academic Exchange Service (DAAD) exchange program "PPP Japan" in collaboration with the Japan Society for the Promotion of Science (JSPS).

Project title (German): "Hochbeschleunigte Simulation für akkuraten Verzögerungsfehlertest"
Grant: #57155440 (PPP Japan 2j ab 15)

Publications

  1. 2017

    1. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    2. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’17), Fort Worth, Texas, USA, 2017, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2017.8242055
  2. 2016

    1. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
  3. 2015

    1. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
Hans-Joachim Wunderlich (i.R.)
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Heading the Research Group Computer Architecture

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