ITI - Completed Research Projects

Completed Research Projects of all Chairs of the Institute

CA - Completed Projects

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration. In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.

10.2014 - 12.2018, DFG-Project: WU 245/16-1

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This project aims to find novel abstraction and algorithm mapping methods to allow highly accurate timing and NFP-aware simulation of multi-million gate circuits on data-parallel architectures such as graphics processing units (GPUs). The expected dramatic speedup compared to the existing state-of-the-art allows fault simulation of millions of faults and thousands of patterns. The increased accuracy of the simulation results allow to optimize test patterns w.r.t. test power and small delay defect coverage in presence of power noise, clock skew or even circuit variations.

01.2015 - 12.2016, DAAD/JSPS PPP Japan Project: #57155440

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Dynamically reconfigurable architectures enable a major acceleration of diverse applications by changing and optimizing the structure of the system at runtime. Permanent and transient faults threaten the correct operation of such an architecture. This project aims to increase dependability of runtime reconfigurable systems by a novel system-level strategy for online tests and online adaptation to an impaired state. This will be achieved by (a) scheduling such that tests for reconfigurable resources are executed with minimal performance impact, (b) resource management such that partially faulty resources are used for components which do not require the faulty elements, and (c) online monitoring and error checking. To ensure reliable runtime reconfiguration, each reconfiguration process is thoroughly tested by a novel and efficient combination of online structural and functional tests. Compared to existing fault-tolerance approaches, our proposal avoids the large hardware overhead of structural redundancy schemes. The saved resources are available for further application acceleration. Still, the proposed scheme covers faults in the fabric, in the reconfigured application logic and errors in the process of reconfiguration.

10.2010 - 06.2017, DFG-Project: WU 245/10-1, 10-2, 10-3

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Since the beginning of the DFG Cluster of Excellence "Simulation Technology" (SimTech) at the University of Stuttgart in 2008, the Institute of Computer Architecture and Computer Engineering (ITI, RA) is an active part of the research within the Stuttgart Research Center for Simulation Technology (SRC SimTech). The institute's research includes the development of fault tolerant simulation algorithms for new, tightly-coupled many-core computer architectures like GPUs, the acceleration of existing simulations on such architectures, as well as the mapping of complex simulation applications to innovative reconfigurable heterogeneous computer architectures.

Within the research cluster, Hans-Joachim Wunderlich acts as a principal investigator (PI) and he co-coordinates the research activities of the SimTech Project Network PN2 "High-Performance Simulation across Computer Architectures". This project network is unique in terms of its interdisciplinary nature and its interfaces between the participating researchers and projects. Scientists from computer science, chemistry, physics and chemical engineering work together to develop and provide new solutions for some of the major challenges in simulation technology. The classes of computational problems treated within project network PN2 comprise quantum mechanics, molecular mechanics, electronic structure methods, molecular dynamics, Markov-chain Monte-Carlo simulations and polarizable force fields.

06.2008 - 10.2017, SimTech Cluster of Excellence

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The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

07.2012 - 06.2015, DFG-Project: WU 245/13-1

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The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

08.2011 - 12.2015, DFG-Project: WU 245/12-1

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Microelectronic circuits suffer from life-time limiting aging. In this project, online in-field methods to assess circuit performance and remaining life-time will be developed to predict failures due to aging processes. Sensors and monitoring infrastructure are used to analyze both operating conditions as well as aging indicators so that a system failure can be early indicated and prevented by technical measures. Novel maintenance concepts based on failure prediction allow for a substantial simplification of established structural fault tolerance measures (e.g. redundancy concepts) even in safety-critical applications since specific counter measures can be applied before an actual aging induced failure. With the aid of such an on-line monitoring the effective life-time of a microelectronic product can be significantly increased at low cost.

03.2011 - 12.2014, DFG-Project: WU 245/11-1

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Functionality in embedded systems is more and more realized by integrated hardware / software systems. Typically, these systems are strongly coupled with technical processes, as for instance the control of a vehicle, which show time-dependent, discrete-continuous dynamics. Testing for the correct functionality of their according design as well as of the final product contributes large sums to the production costs due to its complexity. An efficient method is required for the integrated test of hardware and software in these systems, which respects all the aspects of validation, debug, test and diadnosis. Model-based development and test gains importance in research and also in industrial practice, as they support the systematic, stepwise refinement of requirements down to the implementation. By using models to describe the functionality of integrated hard- and software systems a higher efficiency of their test can be achieved. The central goal of this project is the generation of tests for the functionality and structure of an embedded hardware / software system from its system model along with an automatic evaluation and failure diagnosis.

10.2010 - 09.2013, DFG-Project: WU 245/9-1

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In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.

01.2006 - 07.2013, DFG-Project: WU 245/5-1, 5-2

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Together, AUDI AG, Continental AG, Infineon Technologies AG and ZMD AG are researching ways to improve the analytic and diagnostic capabilities of electronic control units (ECU) in motor vehicles. Through to 2013, the four partners, headed by Infineon, will work on ways to make error detection more precise and faults easier to rectify for automakers and repair shops. The project partners will be assisted by several research organizations and universities: the Fraunhofer Institute for Integrated Circuits in Dresden, the University of the Federal Armed Forces in Munich, and the Universities of Cottbus, Erlangen-Nuremberg, and Stuttgart.

07.2010 - 07.2013, BMBF - Project

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CA - Completed Projects (before 2010)

Embedded Systems - Completed Projects

POWERBLOCK+ project investigates new technologies for high voltage generators in X-ray applications performing power integration density that can not be reached with convetional power electronic components and design techniques. The results of the research activites will be presented using a prototype.

To achive this goal new simulation methods for whole system development considering high integration density are necessary. It drive to concipate development tools and technologies able to be applied to a large spectrum of systems in medical imaging applications.

The Stuttgart University contributes to the specifilation, modeling und efficient simulation of virtual Prototypes representing the X-ray system behavior. It make posible to evaluate and improve this tecnology considering the whole X-ray system and their medical applications.

The implementation of well refined low cost prototypes will allow shorter development cycles and a better consideration different product variants.

The developed design tools and technologies can be exploted in other technical areas.

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

Configurable Network-on-Chip Multi-Processor Systems-on-a-Chip (NoC-MPSoCs) are an emerging architecture for simulation applications. In this project we study the interactions between simulation software and such hardware structures, providing a software interface that allows configuring the on-chip hardware resources, and enabling the development of a meta-model for a wide range of configurable NoC-MPSoCs. The model shall provide performance assessment even under the occurrence and handling of faults, and be suitable for simulation, thus forming a virtual prototype that enables the investigation of prospective NoC-MPSoC architectures for given simulation applications long before the hardware gets available. This eases the Hardware / Software Co-Design for simulation applications and allows to anticipate and estimate the impact of future hardware architectures on the simulation performance.

In NATSIM we develop formalisms, novel modeling techniques and efficient simulation mechanisms for complex embedded hardware-software systems. Traditionally, TLM languages, methodologies and simulation environments have focused on systems with fixed component functionality and static communication architectures. In NATSIM we deal with run-time reconfigurable and self-adaptive embedded systems. Additionally, existing TLM simulation environments are purely sequential. NATSIM aims at enabling parallel TLM simulation environments with multi-core simulation hosts and clusters.

ROBUST researches new methods and procedures for designing robust nano-electronic systems. The project abstracts and defines quantitative measures of robustness, which are then employed for guiding and assessing static and dynamic optimization of robustness. The results of ROBUST are methods and prototype tools that enable early consideration of robustness in the context of a top-down system design flow. Our contribution to ROBUST lies in assessing robustness on system level based on directed and randomized fault injection with SystemC.

In this project we set up an environment that supports the development of embedded systems consisting of an ARM microprocessor running embedded software and application-specific hardware, both interacting via a common bus system. Further components such as memories and standard peripherals may be connected to the bus. The prototyping environment shall support the modelling and simulation of the system based on transaction level SystemC (covering the bus systems and all attached hardware excluding the ARM) and the ARM instruction set simulator "Armulator". Based on commercial EDA software and compilers, a design flow will be set up that allows to implement a prototype on a NEC SoClite+ prototyping board which includes an ARM7TDMI-S microprocessor core, an FGPA for application-specific logic, and several types of memory and peripheral components.

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