Projects

Current Research Projects

HOCOS - Current Research Projects

Algebraic Fault Attacks

Cryptographic circuits are employed in mobile and embedded systems to protect sensitive information from unauthorized access and manipulation. Fault attacks circumvent the protection by injecting faults into the hardware implementation of the cryptographic function, thus manipulating the calculation in a controlled manner and allowing the attacker to derive protected data such as secret keys.

The Algebraic Fault Attacks project focuses on the class of algebraic fault attacks, where the information used for cryptanalysis is represented by systems of polynomials.

Benchmarks for algebraic fault attacks

We are working on creating a comprehensive set of benchmarks for algebraic fault attacks. These will be published here as soon as they are available.

Fault Attack Benchmarks for Small Scale AES

Description

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Project is maintained by University of Passau

Near-sensor Computing Using Low-cost Stochastic Circuits

This project aims at developing methods to realize low-cost and power-efficient hardware circuits for near-sensor computing following the Stochastic Computing paradigm. Stochastic computing provides extremely compact, error-tolerant and low-power implementations of complex functions, but at the expense of longer computation times and some degree of inaccuracy. This makes stochastic circuits (SCs) especially attractive for near-sensor computing, where the processed sensor data are inaccurate anyway and computations tend to occur infrequently. A special focus of this project will be the SC realization of neural networks (NNs) used for classification tasks, from lightweight NNs to fully-fledged convolutional NNs for deep learning.

please visit project page

P1: Systematic Analysis of System-Level Test Fails (GS-IMTR)

Test quality, defined as the absence of test escapes (defective circuits that had passed post-manufacturing test), is the ultimate target of testing. Customers apply system-level test (SLT) to circuits that already have been tested post-fabrication and reportedly identify test escapes. The objective of this project is to understand the nature of such hard-to-detect failures. Establishing a better understanding of SLT and making it more effective and efficient could drastically improve the economy of circuit design and manufacturing.

Please visit gs-imtr project site

P5: Automated Generation of System-Level Test Programs for Characterization of Parametric Device Properties (GS-IMTR)

Contact

Ilia Polian
Prof. Dr. rer. nat. habil.

Ilia Polian

Head of Institute and Chair of Hardware Oriented Computer Science

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