Towards Secure Electroforming-free Memristive Cryptographic Implementations

Project title: Towards Secure Electroforming-free Memristive Cryptographic Implementations

Acronym: MemCrypto

This project is part of the DFG Priority Program “Nano Security. From Nano-Electronics to Secure Systems“ (SPP 2253).

Principal Investigators:

Project Abstract: Memristive devices offer enormous advantages for non-volatile memories and neuromorphic computing, but there is a rising interest in using memristive technologies for security applications. Project MemCrypto aims at development and investigation of memristive cryptographic implementations, assessment and improvement of their security against physical attacks. This work focuses on combinational and sequential realizations of complete cryptographic circuits and complements earlier research on memristive physical unclonable functions and random number generators.

Within MemCrypto, simplified cryptographic circuits will be physically built out of novel electroforming-free memristive devices fabricated as wire-bonded line arrays using pulsed laser deposition. Physical attacks (side-channel analysis and fault injections) against memristive circuits will be studied, with a focus on identifying and characterizing novel attack mechanisms that do not exist in conventional CMOS technology. For instance, side-channel analysis could utilize effects of memristance and nonvolatility, and fault injections can target both memristive devices and their control logic. Three representative memristive logic families will be explored and low-level protections for information leakage reduction will be developed for all of them, as well as the development of combination of these low-level protections with higher-level masking. We will also perform an experimental comparative study with commercially available memristive devices (with requirement of an electroforming step) and with a CMOS implementation on an FPGA.

A further objective of MemCrypto is to develop electrical simulation models and simulation procedures suitable for security analysis before physical realization of a circuit. On the one hand, we will improve the accuracy of existing Spice-level simulation models by better reflecting switching performances in endurance and retention. On the other hand, we will devise mixed-level simulation procedures that balance between accuracy and simulation speed and are meant for evaluation of physical attacks in medium-size memristive circuits. Using such procedures, we will extend the findings gathered on reduced-scale physical implementations to fully-fledged cryptographic circuits.

MemCrypto is a tandem project that will strongly benefit from interdisciplinary collaboration of both applicants. Ilia Polian will provide competencies in hardware-oriented security, design of complex electronic circuits and mixed-level simulation algorithms. Nan Du, as a co-inventor of the electroforming free BiFeO3 based memristive device family exploited in MemCrypto, will contribute her knowledge in fabrication, characterization, optimization, modeling and simulation of memristive devices. Together, the applicants are a team that includes complementary abilities to holistically address all relevant security aspects of using memristive technologies for cryptographic circuits.

Selected Publications

  1. 2023

    1. On Side-Channel Analysis of Memristive Cryptographic Circuits. Li-Wei Chen; Ziang Chen; Werner Schindler; Xianyue Zhao; Heidemarie Schmidt; Nan Du and Ilia Polian. IEEE Transactions on Information Forensics and Security 18, (2023), pp. 463–476. DOI:
  2. 2021

    1. Low-power emerging memristive designs towards secure hardware systems for applications in internet of things. Nan Du; Heidemarie Schmidt and Ilia Polian. Nano Materials Science 3, 2 (2021), pp. 186–204.


This image shows Ilia Polian

Ilia Polian

Prof. Dr. rer. nat. habil.

Head of Institute and Chair of Hardware Oriented Computer Science

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