Projects

Hardware Oriented Computer Science - Research Projects

(DFG Project; since October 2015)

Cryptographic circuits are employed in mobile and embedded systems to protect sensitive information from unauthorized access and manipulation. Fault attacks circumvent the protection by injecting faults into the hardware implementation of the cryptographic function, thus manipulating the calculation in a controlled manner and allowing the attacker to derive protected data such as secret keys. A large number of fault attacks and counter-measures against such attacks were suggested in the last years. However, isolated techniques for each individual attack are no longer sufficient; a generic protective strategy is lacking.

The Algebraic Fault Attacks project focuses on the class of algebraic fault attacks, where the information used for cryptanalysis is represented by systems of polynomials. In order to understand the scope of such attacks and develop suitable counter-measures, techniques to conduct algebraic fault attacks will be developed.

Project is maintained by University of Passau

This project aims at developing methods to realize low-cost and power-efficient hardware circuits for near-sensor computing following the Stochastic Computing paradigm. Stochastic computing provides extremely compact, error-tolerant and low-power implementations of complex functions, but at the expense of longer computation times and some degree of inaccuracy. This makes stochastic circuits (SCs) especially attractive for near-sensor computing, where the processed sensor data are inaccurate anyway and computations tend to occur infrequently. A special focus of this project will be the SC realization of neural networks (NNs) used for classification tasks, from lightweight NNs to fully-fledged convolutional NNs for deep learning.

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Computer Architecture - Research Projects

An important problem in modern technology nodes in nano-electronics are early life failures, which often cause recalls of shipped products and incur high costs. An important root cause of such failures are marginal circuit structures, which pass a conventional manufacturing test, but are not able to cope with the later workload and stress in the field. Such structures can be identified on the basis of non-functional indicators, in particular by testing the timing behavior. For an effective and cost-efficient test of these indicators, the FAST project investigates novel scan designs and built-in self-test strategies for circuits, which can operate at frequencies beyond the functional specification to detect small deviations of the nominal timing behavior and thus potential early life failures

Projectpage

RSNs were initially brought up to manage the extensive amount of instrumentation in modern systems-on-chip to facilitate cost-efficient bring-up and debug, test, diagnosis and maintenance. Recently, the reuse of RSNs at system runtime for online fault classification and fault management moved into the center of research activities. Reasons are not only the increased complexity and dependability requirements in new technologies, but also the emerging application paradigms of self-aware and autonomous systems. Especially in safety-critical applications, online test, system monitoring and fault tolerance at low cost become mandatory. For example, the standard ISO 26262 specifies critical faults to be detected within certain test intervals at runtime and allows only a maximum fault reaction time until the system has to be transferred into a safe state. The periodic test is usually structure oriented and targets stuck-at, transition and delay faults.

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Embedded Systems - Research Projects

In many application fields firmware turns out to be a critical design factor. The variety of tasks and rising requirements to the firmware are leading to high design complexity and rising costs. Consequently, the firmware has to be flexible in order to deal with different use-cases and application scenarios. At the same time, it has to be adjustable to changing hardware parameters as well as altering configurations of system and architecture.

In this context, CONFIRM investigates key aspects for the realization of a seamless and automated firmware generation process in close cooperation with the involved industry partners. This includes model-based firmware specification with the ability of automated firmware composition from software libraries while real-time ability and power consumption are optimized with respect to given application scenarios and the hardware and memory architecture at hand.

The University of Stuttgart contributes to CONFIRM with firmware generation methods for an optimized memory management. For this, static and dynamic optimization concepts are being investigated that minimize the power consumption of the memory subsystem under the consideration of timing budgets and peak power constraints. In order to implement obtained optimization results, automated firmware generation methods for memory management are being researched.

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Contact

Ilia Polian
Prof. Dr. rer. nat. habil.

Ilia Polian

Head of Institute and Chair of Hardware Oriented Computer Science

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