Hardware Oriented Computer Science - Research Projects

(DFG Project; since October 2015)

Cryptographic circuits are employed in mobile and embedded systems to protect sensitive information from unauthorized access and manipulation. Fault attacks circumvent the protection by injecting faults into the hardware implementation of the cryptographic function, thus manipulating the calculation in a controlled manner and allowing the attacker to derive protected data such as secret keys. A large number of fault attacks and counter-measures against such attacks were suggested in the last years. However, isolated techniques for each individual attack are no longer sufficient; a generic protective strategy is lacking.

The Algebraic Fault Attacks project focuses on the class of algebraic fault attacks, where the information used for cryptanalysis is represented by systems of polynomials. In order to understand the scope of such attacks and develop suitable counter-measures, techniques to conduct algebraic fault attacks will be developed.

Project is maintained by University of Passau

This project aims at developing methods to realize low-cost and power-efficient hardware circuits for near-sensor computing following the Stochastic Computing paradigm. Stochastic computing provides extremely compact, error-tolerant and low-power implementations of complex functions, but at the expense of longer computation times and some degree of inaccuracy. This makes stochastic circuits (SCs) especially attractive for near-sensor computing, where the processed sensor data are inaccurate anyway and computations tend to occur infrequently. A special focus of this project will be the SC realization of neural networks (NNs) used for classification tasks, from lightweight NNs to fully-fledged convolutional NNs for deep learning.

please visit project page

Computer Architecture - Research Projects

An important problem in modern technology nodes in nano-electronics are early life failures, which often cause recalls of shipped products and incur high costs. An important root cause of such failures are marginal circuit structures, which pass a conventional manufacturing test, but are not able to cope with the later workload and stress in the field. Such structures can be identified on the basis of non-functional indicators, in particular by testing the timing behavior. For an effective and cost-efficient test of these indicators, the FAST project investigates novel scan designs and built-in self-test strategies for circuits, which can operate at frequencies beyond the functional specification to detect small deviations of the nominal timing behavior and thus potential early life failures


VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Due to the increasing complexity, however, the embedded infrastructure and flexible access mechanisms such as Reconfigurable Scan Networks (RSNs) themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE P1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals.


Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration.

In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.


Embedded Systems - Research Projects

In many application fields firmware turns out to be a critical design factor. The variety of tasks and rising requirements to the firmware are leading to high design complexity and rising costs. Consequently, the firmware has to be flexible in order to deal with different use-cases and application scenarios. At the same time, it has to be adjustable to changing hardware parameters as well as altering configurations of system and architecture.

In this context, CONFIRM investigates key aspects for the realization of a seamless and automated firmware generation process in close cooperation with the involved industry partners. This includes model-based firmware specification with the ability of automated firmware composition from software libraries while real-time ability and power consumption are optimized with respect to given application scenarios and the hardware and memory architecture at hand.

The University of Stuttgart contributes to CONFIRM with firmware generation methods for an optimized memory management. For this, static and dynamic optimization concepts are being investigated that minimize the power consumption of the memory subsystem under the consideration of timing budgets and peak power constraints. In order to implement obtained optimization results, automated firmware generation methods for memory management are being researched.



Ilia Polian
Prof. Dr. rer. nat. habil.

Ilia Polian

Head of Institute and Chair of Hardware Oriented Computer Science

To the top of the page