AZTEKE

AZTEKE: Extended Deterministic Logic Built-In Self-Test

Project Description

The focus of this project is on highly efficient design for test (DFT) and built-in self test technologies for systems on a chip (SoCs). Together with academic and industrial partners we develop methods and tools that replace test functions that run on test machines by on-chip test functions. The main objective is a "low cost" test in combination with a high fault coverage also for dynamic fault effects. The goal of this project is to develop new ideas and approaches to enhance the performance and the versatility of the Deterministic Logic Self-Test. The topics addressed here include issues like the optimization of the Deterministic Logic Built-In Self-Test (DLBIST), the development of a new architecture called External Deterministic Self-Test or Built-Out Self-Test (BOST), the defect coverage evaluation of a pseudo-random test sequence in which deterministic patterns have been embedded, the synthesis of X-Masking Logic (XML) and its impact on unmodeled fault coverage, and the enlargement of the covered fault model space towards delay faults.

03.2002 - 02.2005, BMBF - Project: 01M3063C

Journals and Conference Proceedings

  1. 2005

    1. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
    2. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.

Workshop Contributions

    Hans-Joachim Wunderlich (i.R.)
    Prof. Dr. rer. nat. habil.

    Hans-Joachim Wunderlich (i.R.)

    Heading the Research Group Computer Architecture

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