ES - Current Research Projects
NoC-Performability: Integrated Performance and Reliability Evaluation of Fault-Tolerant Networks-on-Chip
Technology scaling makes it possible to implement systems with hundreds of processing cores, and thousands in the future, on a single chip. The communication in such systems is enabled by Networks-on-Chips (NoCs). A downside of technology scaling is the increased susceptibility to failures emerging in NoC resources during operation. Ensuring reliable operation despite such failures degrades NoC performance and may even invalidate the performance benefits expected from scaling. Thus, it is not enough to analyze performance and reliability in isolation, as usually done. Instead, we research how both aspects can be treated together using the concept of performability and its analysis with Markov reward models. In addition to developing modelling and analysis techniques, we exemplify our methodology through application to compare various NoC topologies and fault-tolerant routing algorithms. We investigate how performability develops with scaling towards larger NoCs and explore the limits of scaling by determining the break-even failure rates under which scaling can achieve net performability increase.
ES - Completed Projects
In many application fields firmware turns out to be a critical design factor. The variety of tasks and rising requirements to the firmware are leading to high design complexity and rising costs. Consequently, the firmware has to be flexible in order to deal with different use-cases and application scenarios. At the same time, it has to be adjustable to changing hardware parameters as well as altering configurations of system and architecture.
In this context, CONFIRM investigates key aspects for the realization of a seamless and automated firmware generation process in close cooperation with the involved industry partners. This includes model-based firmware specification with the ability of automated firmware composition from software libraries while real-time ability and power consumption are optimized with respect to given application scenarios and the hardware and memory architecture at hand.
The University of Stuttgart contributes to CONFIRM with firmware generation methods for an optimized memory management. For this, static and dynamic optimization concepts are being investigated that minimize the power consumption of the memory subsystem under the consideration of timing budgets and peak power constraints. In order to implement obtained optimization results, automated firmware generation methods for memory management are being researched.
Please visit the home page of CONFIRM
POWERBLOCK+ project investigates new technologies for high voltage generators in X-ray applications performing power integration density that can not be reached with convetional power electronic components and design techniques. The results of the research activites will be presented using a prototype.
To achive this goal new simulation methods for whole system development considering high integration density are necessary. It drive to concipate development tools and technologies able to be applied to a large spectrum of systems in medical imaging applications.
The Stuttgart University contributes to the specifilation, modeling und efficient simulation of virtual Prototypes representing the X-ray system behavior. It make posible to evaluate and improve this tecnology considering the whole X-ray system and their medical applications.
The implementation of well refined low cost prototypes will allow shorter development cycles and a better consideration different product variants.
The developed design tools and technologies can be exploted in other technical areas.
The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.
Configurable Network-on-Chip Multi-Processor Systems-on-a-Chip (NoC-MPSoCs) are an emerging architecture for simulation applications. In this project we study the interactions between simulation software and such hardware structures, providing a software interface that allows configuring the on-chip hardware resources, and enabling the development of a meta-model for a wide range of configurable NoC-MPSoCs. The model shall provide performance assessment even under the occurrence and handling of faults, and be suitable for simulation, thus forming a virtual prototype that enables the investigation of prospective NoC-MPSoC architectures for given simulation applications long before the hardware gets available. This eases the Hardware / Software Co-Design for simulation applications and allows to anticipate and estimate the impact of future hardware architectures on the simulation performance.
In NATSIM we develop formalisms, novel modeling techniques and efficient simulation mechanisms for complex embedded hardware-software systems. Traditionally, TLM languages, methodologies and simulation environments have focused on systems with fixed component functionality and static communication architectures. In NATSIM we deal with run-time reconfigurable and self-adaptive embedded systems. Additionally, existing TLM simulation environments are purely sequential. NATSIM aims at enabling parallel TLM simulation environments with multi-core simulation hosts and clusters.
ROBUST researches new methods and procedures for designing robust nano-electronic systems. The project abstracts and defines quantitative measures of robustness, which are then employed for guiding and assessing static and dynamic optimization of robustness. The results of ROBUST are methods and prototype tools that enable early consideration of robustness in the context of a top-down system design flow. Our contribution to ROBUST lies in assessing robustness on system level based on directed and randomized fault injection with SystemC.
In this project we set up an environment that supports the development of embedded systems consisting of an ARM microprocessor running embedded software and application-specific hardware, both interacting via a common bus system. Further components such as memories and standard peripherals may be connected to the bus. The prototyping environment shall support the modelling and simulation of the system based on transaction level SystemC (covering the bus systems and all attached hardware excluding the ARM) and the ARM instruction set simulator "Armulator". Based on commercial EDA software and compilers, a design flow will be set up that allows to implement a prototype on a NEC SoClite+ prototyping board which includes an ARM7TDMI-S microprocessor core, an FGPA for application-specific logic, and several types of memory and peripheral components.