Publikationen

Publikationen des Instituts

Publikationen

  1. 2021

    1. Reliability-Aware Quantization for Anti-Aging NPUs. Sami Salamin; Georgios Zervakis; Ourania Spantidi; Iraklis Anagnostopoulos; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
    2. Approximate Computing for ML: State-of-the-art, Challenges and  Visions. Georgios Zervakis; Hassaan Saadat; Hussam Amrouch; Andreas Gerstlauer; Sri Parameswaran and Joerg Henkel. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    3. Cross-layer Design for Computing-in-Memory: From Devices,  Circuits, to Architectures and Applications. Hussam Amrouch; Xiaobo Sharon Hu; Mohsen Imani; Ann Franchesca Laguna; Michael Niemier; Simon Thomann; Xunzhao Yin and Cheng Zhuo. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    4. FeFET and NCFET for Future DNNs: Visions and Opportunities. Yayla Mikail; Kuan-Hsun Chen; Christian Hakert; Georgios Zervakis; Jian-Jia Chen; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
  2. 2020

    1. Security Preserving Integration and Re-Synthesis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Chih-Hao Wang and Hans-Joachim Wunderlich. In to appear in Proceedings of the IEEE International Test Conference (ITC’20), Washington DC, USA, 2020.
    2. Logic Fault Diagnosis of Hidden Delay Defects. Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich and Xiaoqing Wen. In to appear in Proceedings of the IEEE International Test Conference (ITC’20), Washington DC, USA, 2020.
    3. Machine learning and hardware security: challenges and opportunities. Francesco Regazzoni; Shivam Bhasin; Amir Ali Pour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natal; Paul Franzon; David Hely; Naofumi Homma; Akira Ito; Dirmanto Jap; Priyank Kashyap; Ilia Polian; Seetal Potluri; Rei Ueno; Elena Ioana Vatajelu and Ville Yli-Mayry. In to appear in Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD’20), 2020.
    4. Modeling Emerging Technologies using Machine Learning:  Challenges and Opportunities. Florian Klemme; Jannik Prinz; Victor M. van Santen; Joerg Henkel and Hussam Amrouch. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’20), 2020.
    5. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In to appear in Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
    6. Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. Florian Klemme; Yogesh Chauhan; Joerg Henkel and Hussam Amrouch. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’20), 2020.
    7. Hardware-based fast real-time image classification with  stochastic computing. Ponana Kelettira Muthappa; Florian Neugebauer; Ilia Polian and John P. Hayes. In to appear in Proceedings of the 38th IEEE International Conference on Computer Design (ICCD’20), 2020.
    8. Side Channel Attacks vs Approximated Computing. Francesco Regazzoni and Ilia Polian. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), 2020, pp. 321–326. DOI: https://doi.org/10.1145/3386263.3407592
    9. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
    10. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
    11. Error control scheme for malicious and natural faults in cryptographic modules. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (2020). DOI: https://doi.org/10.1007/s13389-020-00234-7
    12. IPM-RED: combining higher-order masking with robust error detection. Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (2020). DOI: https://doi.org/10.1007/s13389-020-00229-4
    13. Variation-Aware Defect Characterization at Cell Level. Zahra Najafi Haghi; Marzieh Hashemipour Nazari and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE European Test Symposium (ETS’20), Tallinn, Estonia, 2020, pp. 1--6. DOI: https://doi.org/10.1109/ETS48528.2020.9131600
    14. Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the  IEEE VLSI TestSymposium (VTS’20), San Diego, US, 2020, pp. 1--6. DOI: https://doi.org/10.1109/VTS48691.2020.9107642
    15. BTI and HCI Degradation in a Complete 32X64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity. Victor van Santen; Simon Thomann; C. Pasupuleti; P. Genssler; N. Gangwar; U. Sharma; J. Henkel; S. Mahapatra and H. Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    16. GPU-accelerated Time Simulation of  Systems with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116256
    17. Using Programmable Delay Monitors for  Wear-Out and Early Life Failure Prediction. Chang Liu; Eric Schneider and Hans-Joachim. Wunderlich. In Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116284
    18. Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116525
    19. Impact of NBTI Aging on Self-Heating in Nanowire FET. Om Prakash; S. Manhas; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’20), Grenoble, France, 2020.
    20. Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont and Ilia Polian. In 2020 Design, Automation  Test in Europe Conference  Exhibition (DATE), 2020, pp. 508–513. DOI: https://doi.org/10.23919/DATE48585.2020.9116483
    21. Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET. Om Prakash; Aniket Gupta; Girish Pahwa; Jörg Henkel; Yogesh Chauhan and Hussam Amrouch. In IEEE Electron Devices Technology & Manufacturing Conference (EDTM’20), 2020.
    22. Energy Optimization in NCFET-based Processors. Sami Salamin; Martin Rapp; Hussam Amrouch; Andreas Gerstlauer and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’20), Grenoble, France, 2020.
    23. Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. Electronic Imaging 2020, 4 (2020), pp. 76-1-76–7. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
    24. Machine Learning Based Online Full-Chip Heatmap Estimation. Sheriff Sadiqbatcha; Yue Zhao; Jinwei Zhang; Hussam Amrouch; Jörg Henkel and Sheldon Tan. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20), 2020.
    25. Impact of Self-Heating On Performance, Power and Reliability in FinFET Technology. Victor M. van Santen; Paul R. Genssler; Om Prakash; S. Thomann; Jörg Henkel and Hussam Amrouch. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20, 2020.
    26. NCFET to Rescue Technology Scaling: Opportunities and Challenges. Hussam Amrouch; Victor M. van Santen; Girish Pahwa; Yogesh Chauhan and Jörg Henkel. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20), 2020.
    27. Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems. Hussam Amrouch; Martin Rapp; Sami Salamin and Jörg Henkel. In A Journey of Embedded and Cyber-Physical Systems. Springer, Cham, 2020, pp. 107.
    28. Information leakage from robust codes protecting cryptographic primitives. Osnat Keren and Ilia Polian. In Frontiers in Hardware Security and Trust: Theory, design and practice, C.H. Chang and Y Cao (eds.). The Institution of Engineering and Technology, 2020.
    29. Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging. V. Surabhi; P. Krishnamurthy; H. Amrouch; R. Henkel J. Karri and F. Khorrami. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    30. Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). J. Knechtel; S. Patnaik; M. Nabeel; M. Ashraf; Y. Chauhan; J. Henkel; O. Sinanoglu and H. Amrouch. IEEE Micro Magazine (MICRO’20) (2020).
    31. Dynamic Power and Energy Management for NCFET-based Processors. Sami Salamin; Martin Rapp; Andreas Gerstlauer; Joerg Henkel and Hussam Amrouch. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    32. Impact of Extrinsic Variation Sources on the Device-to-Device Variation in Ferroelectric FET. Kai Ni; Aniket Gupta; Om Prakash; Simon Thomann; X. Sharon Hu and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    33. Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy. G. Zervakis; H. Amrouch and J. Henkel. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2020).
    34. Massively Parallel Circuit Setup in GPU-SPICE. V. van Santen; F. Florian Diep; J. Henkel and H. Amrouch. IEEE Transactions on Computers (TC’20) (2020).
    35. Analysis of Digital Logic Circuit Degradation. Subrat Misra; Thirunavukkarasu Vignesh; Jerin Joe; Hussam Amrouch; Jörg Henkel and Souvik Mahapatra. In Recent Advances in Negative Bias Temperature Instability, Souvik Mahapatra (ed.). Springer International Publishing, 2020.
    36. Machine Learning for CAD. Marilyn Wolf; Jörg Henkel and Hussam Amrouch (Eds.). . Springer International Publishing, 2020.
    37. Weight-Oriented Approximation for Energy-Efficient Neural  Network Inference Accelerators. Zois-Gerasimos Tasoulas; Georgios Zervakis; Iraklis Anagnostopoulos; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers  (TCAS-I) (2020).
    38. Impact of Interface Traps on Negative Capacitance Transistor:  Device and Circuit Reliability. Om Prakash; Anekit Gupta; Girish Pahwa; Joerg Henkel; Yogesh S. Chauhan and Hussam Amrouch. IEEE Journal of the Electron Devices Society (JEDS’20) (2020).
    39. Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET. Aniket Gupta; Kai Ni; Om Prakash; X. Sharon Hu and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    40. Impact of Radiation on Negative Capacitance FinFET. Govind Bajpai; Aniket Gupta; Om Prakash; Girish Pahwa; Jörg Henkel; Yogesh Chauhan and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    41. Power-Efficient Heterogeneous Many-Core Design with NCFET Technology. S. Salamin; M. Rapp; A. Pathania; A. Maity; J. Henkel; T. Mitra and H. Amrouch. IEEE Transactions on Computers (TC’20) (2020).
    42. Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology. H. Amrouch; G. Pahwa; A. Gaidhane; F. Klemme; O. Prakash; C. Dabhi and Y. Chauhan. IEEE Transactions on Circuits and Systems I: Regular Paper  (TCAS-I’20), 2020 (2020).
    43. NPU Thermal Management. Hussam Amrouch; Georgios Zervakis; Kattan; Hammam; Iraklis Anagnostopoulos and Joerg Henkel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    44. Aging Compensation with Dynamic Computation Approximation. H. Kim; J. Kim; H. Amrouch; Jörg Henkel; A. Gerstlauer; K. Choi and P. Hanmin. IEEE Transactions on Circuits and Systems I: Regular Paper  (TCAS-I’20) (2020).
    45. Towards a New Thermal Monitoring Based Framework for Embedded CPS Device Security. N. Patel; P. Krishnamurthy; H. Amrouch; J. Henkel; M. Shamouilian; R. Karri and Khorrami. R. IEEE Transactions on Dependable and Secure Computing  (TDSC’20) (2020).
    46. Post-Silicon Hot-Spot Identification and Machine-LearningBased Thermal Modeling Using Infrared Thermal Imaging. S. M Sheriff; Z. Jinwei; Z. Hengyang; Amrouch; H.; Jörg Henkel and S. Tan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20) (2020).
    47. Hardware Trojan Detection Using Controlled Circuit Aging. V. Surabhi; P. Krishnamurthy; H. Amrouch; K. Basu; R. Henkel J. Karri and F. Khorrami. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2020).
  3. 2019

    1. Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000114
    2. Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000143
    3. Combined MPSoC Task Mapping and Memory Optimization for Low-Power. Manuel Strobel; Gereon Führ; Martin Radetzki and Rainer Leupers. In Proc. IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Bangkok, Thailand, 2019.
    4. The Impact of Emerging Technologies on Architectures and System-level Management. Jörg Henkel; Hussam Amrouch; Martin Rapp; Sami Salamin; Dayane Reis; Di Gao; Xunzhao Yin; Michael Niemier; Cheng Zhuo; Hu X. Sharon; Hsiang-Yun Cheng and Chia-Lin Yang. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’19), 2019.
    5. Design-Time Memory Subsystem Optimization for Low- Power Multi-Core Embedded Systems. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded(MCSoC), Singapore, 2019. DOI: https://doi.org/10.1109/MCSoC.2019.00056
    6. A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. Jie Hou; Q. Han and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, 2019.
    7. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems (TCAD) 38, 10 (2019), pp. 1956–1968. DOI: https://doi.org/10.1109/TCAD.2018.2864255
    8. A Methodology to Compute Long-Term Fault Resilience of NoCs under Fault-Tolerant Routing Algorithms. Jie Hou and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages(FDL), Southampton, UK, 2019.
    9. A Backend Tool for the Integration of Memory Optimizations into Embedded Software. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages (FDL), Southampton, UK, 2019. DOI: https://doi.org/10.1109/FDL.2019.8876895
    10. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Mael Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019, pp. 25–32. DOI: https://doi.org/10.1109/FDTC.2019.00012
    11. NCFET-Aware Voltage Scaling. Sami Salamin; Martin Rapp; Hussam Amrouch; Girish Pahwa; Yogesh S. Chauhan and Jörg Henkel. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’19), 2019.
    12. Automated Sensor Firmware Development - Generation, Optimization, and Analysis. Jens Rudolf; Manuel Strobel; Joscha Benz; Cristian Haubelt; Martin Radetzki and Oliver Bringmann. In MBMV 2019; 22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019, pp. 1–12.
    13. On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’19), Florence, Italy, 2019, pp. 1016--1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
    14. Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (2019), pp. 78--91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
    15. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
    16. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
    17. Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation. Frank Sill Torres; Hussam Amrouch; Jörg Henkel and Rolf Drechsler. In Proceedings of the IEEE 56th International Reliability Physics Symposium  (IRPS’19), Las Vegas, USA, 2019.
    18. New Worst-Case Timing for Standard Cells Under Aging Effects. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Device and Materials Reliability (T-DMR’19) 19, 1 (2019), pp. 149--158.
    19. Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal Imaging. Sheriff Sadiqbatcha; Hengyang Zhao; Hussam Amrouch; Jörg Henkel and Sheldon Tan. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’19), Florence, Italy, 2019.
    20. Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’19) (2019).
    21. Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395--416. DOI: https://doi.org/10.1049/PBPC022E_ch16
    22. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    23. Power-Mode-Aware Memory Subsystem Optimization for Low-Power System-on-Chip Design. Manuel Strobel and Martin Radetzki. ACM Transactions on Embedded Computing Systems(TECS) (2019). DOI: https://doi.org/10.1145/3356583
    24. On the Workload Dependence of Self-Heating in FinFET Circuits. Victor M van Santen; Hussam Amrouch; Pooja Sharma and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’19) (2019).
    25. A Cross-layer Gate-Level-to-Application Co-simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders. Guilherme Paim; Leandro M. G. Rocha; Hussam Amrouch; A. C. da Costa Eduardo; Sergio Bampi and Jörg Henkel. IEEE Transactions on Circuits and Systems for Video Technology  (TCSVT’19) (2019).
    26. Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits. A Thirunavukkarasu; Hussam Amrouch; Jerin Joe; Nilesh Goel; Narendra Parihar; Subrat Mishra; Chetan K Dabhi; Yogesh S Chauhan; Jörg Henkel and Souvik Mahapatra. IEEE Transactions on Electron Devices (T-ED’19) 66, 1 (2019), pp. 316--323.
    27. Unveiling the Impact of IR-drop on Performance Gain in NCFET-based Processors. Hussam Amrouch; Sami Salamin; Girish Pahwa; Amol D Gaidhane; Jörg Henkel and Yogesh S Chauhan. IEEE Transactions on Electron Devices (T-ED’19) (2019).
    28. A simulation study of NBTI impact on 14-nm node FinFET technology for logic applications: Device degradation to circuit-level interaction. Subrat Mishra; Hussam Amrouch; Jerin Joe; Chetan K Dabhi; Karansingh Thakor; Yogesh S Chauhan; Jörg Henkel and Souvik Mahapatra. IEEE Transactions on Electron Devices (T-ED’19) 66, 1 (2019), pp. 271--278.
    29. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
    30. Rebirth-FTL: Lifetime optimization via Approximate Storage for NAND Flash. Lei Han; Hussam Amrouch; Zili Shao and Jörg Henkel. In IEEE Non-Volatile Memory Systems and Applications Symposium  (NVMSA’19), Hangzhou, China, 2019.
    31. Reliability Challenges with Self-Heating in FinFET Technology. H. Amrouch; V. M. van Santen; O. Prakash; H. Kattan; S. Salamin; S. Thomann and J. Henkel. In IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS’19), 2019.
    32. Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. Martin Rapp; Sami Salamin; Hussam Amrouch; Girish Pahwa; Yogesh S. Chauhan and Jörg Henkel. In Proceedings of the 56th Annual Design Automation Conference (DAC’19), Las Vegas, USA, 2019.
    33. A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives. Osnat Keren and Ilia Polian. In Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019, pp. 49--63. DOI: https://doi.org/10.29007/r2sc
    34. Aging Effects: From Physics to CAD. Hussam Amrouch; Heba Khdr and Jörg Henkel. In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach, William Fornaciari and Dimitrios Soudris (eds.). Springer International Publishing, 2019, pp. 43--69. DOI: https://doi.org/10.1007/978-3-319-91962-1_3
    35. Estimating and Mitigating Aging Effects in Routing Network of FPGAs. Behnam Khaleghi; Behzad Omidi; Hussam Amrouch; Jörg Henkel and Hossein Asadi. IEEE Transactions on Very Large Scale Integration Systems (TVLSI’19) 27, 3 (2019), pp. 651--664.
    36. On the Efficiency of Voltage Overscaling under Temperature and Aging Effects. Hussam Amrouch; Borna Ehsani; Andreas Gerstlauer and Jörg Henkel. IEEE Transactions on Computers (TC’19) (2019).
    37. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    38. Dynamic guardband selection: Thermal-aware optimization for unreliable multi-core systems. Heba Khdr; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Computers (TC’19) 68, 1 (2019), pp. 53--66.
    39. Aging Gracefully with Approximation. Jongho Kim; Heesu Kim; Hussam Amrouch; Jörg Henkel; Andreas Gerstlauer and Kiyoung Choi. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’19), Las Vegas, USA, 2019.
    40. Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. Sami Salamin; Victor M van Santen; Hussam Amrouch; Narendra Parihar; Souvik Mahapatra and Jörg Henkel. IEEE Transactions on Very Large Scale Integration Systems (TVLSI’19) (2019).
    41. Selecting the Optimal Energy Point in Near-Threshold Computing. Sami Salamin; Hussam Amrouch and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’19), Florence, Italy, 2019.

Frühere Publikationen

  1. 2021

    1. Reliability-Aware Quantization for Anti-Aging NPUs. Sami Salamin; Georgios Zervakis; Ourania Spantidi; Iraklis Anagnostopoulos; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
    2. Approximate Computing for ML: State-of-the-art, Challenges and  Visions. Georgios Zervakis; Hassaan Saadat; Hussam Amrouch; Andreas Gerstlauer; Sri Parameswaran and Joerg Henkel. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    3. Cross-layer Design for Computing-in-Memory: From Devices,  Circuits, to Architectures and Applications. Hussam Amrouch; Xiaobo Sharon Hu; Mohsen Imani; Ann Franchesca Laguna; Michael Niemier; Simon Thomann; Xunzhao Yin and Cheng Zhuo. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    4. FeFET and NCFET for Future DNNs: Visions and Opportunities. Yayla Mikail; Kuan-Hsun Chen; Christian Hakert; Georgios Zervakis; Jian-Jia Chen; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
  2. 2018

    1. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
    2. Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures  in Low-Power Scan Testing. Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 149--154. DOI: https://doi.org/10.1109/ATS.2018.00037
    3. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (2018), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    4. Detecting and Resolving Security Violations in Reconfigurable Scan Networks. Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the 24th IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’18), Platja d’Aro, Spain, 2018, pp. 91--96. DOI: https://doi.org/10.1109/IOLTS.2018.8474188
    5. Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, 3 (2018), pp. 5--6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
    6. Design-Time Optimization Techniques for Low-Power Embedded Memory Subsystems. Manuel Strobel and Martin Radetzki. In Proc. of the 1st International Workshop on Embedded Software for Industrial IOT (ESIIT), Dresden, Germany, 2018.
    7. Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, 1 (2018), pp. 1--1. DOI: https://doi.org/10.1109/LES.2018.2789942
    8. Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2018.8400685
    9. Device aging: A reliability and security concern. Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit Singh; Hans-Joachim Wunderlich and Naghmeh Karimi. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2018.8400702
    10. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
    11. Recent Advances in EM and BTI Induced Reliability Modeling, Analysis and Optimization. Sheldon X.-D. Tan; Hussam Amrouch; Taeyoung Kim; Zeyu Sun; Chase Cook and Jrg Henkel. Integration VLSI Journal (IVLSI’18) 60, C (2018), pp. 132--152.
    12. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    13. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    14. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    15. Trading Off Temperature Guardbands via Adaptive Approximations. B. Boroujerdian; H. Amrouch; J. Henkel and A. Gerstlauer. In 2018 IEEE 36th International Conference on Computer Design (ICCD’18), 2018, pp. 202–209.
    16. Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. Jie Hou and Martin Radetzki. In 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2018, Cambridge, United Kingdom, March 21-23, 2018, 2018, pp. 609--616. DOI: https://doi.org/10.1109/PDP2018.2018.00102
    17. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
    18. Voltage Adaptation Under Temperature Variation. H. Amrouch; B. Khaleghi and J. Henkel. In 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD’18), 2018, pp. 57–60.
    19. Aging-Aware Boosting. H. Khdr; H. Amrouch and J. Henkel. IEEE Transactions on Computers (TC’18) 67, 9 (2018), pp. 1217–1230.
    20. Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV. V. M. van Santen; J. Martin-Martinez; H. Amrouch; M. M. Nafria and J. Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’18) 65, 1 (2018), pp. 293–306.
    21. Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. V. M. van Santen; J. Diaz-Fortuny; H. Amrouch; J. Martin-Martinez; R. Rodriguez; R. Castro-Lopez; E. Roca; F. V. Fernandez; J. Henkel and M. Nafria. In IEEE International Reliability Physics Symposium (IRPS’18), 2018, pp. P-CR.6-1-P-CR.6-6.
    22. Aging-constrained Performance Optimization for Multi Cores. Heba Khdr; Hussam Amrouch and Jürg Henkel. In Proceedings of the 55th Annual Design Automation Conference (DAC’18), San Francisco, California, 2018, pp. 63:1--63:6.
    23. Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE. V. M. van Santen; H. Amrouch and J. Henkel. In IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS’18), 2018, pp. 143–146.
    24. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    25. Estimating and Optimizing BTI Aging Effects: From Physics to CAD. Hussam Amrouch; Victor M. van Santen and Jörg Henkel. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18), San Diego, California, 2018, pp. 125:1--125:6.
    26. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    27. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    28. Dynamic Resource Management for Heterogeneous Many-cores. Jörg Henkel; Jürgen Teich; Stefan Wildermann and Hussam Amrouch. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18), San Diego, California, 2018, pp. 60:1--60:6.
    29. Modeling and Evaluating the Gate Length Dependence of BTI. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’18) (2018).
    30. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    31. Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance. Hussam Amrouch; Girish Pahwa; Amol D Gaidhane; Jörg Henkel and Yogesh Singh Chauhan. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access’18) 6, (2018), pp. 52754--52765.
  3. 2017

    1. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
    2. Hardware and software innovations in energy-efficient system-reliability monitoring. V. Tenentes; C. Leech; G. M. Bragg; G. Merrett; B. M. Al-Hashimi; H. Amrouch; J. Henkel and S. Das. In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’17), 2017, pp. 1–5.
    3. Trustworthy Reconfigurable Access to On-Chip Infrastructure. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 1st International Test Conference in Asia (ITC-Asia’17), Taipei, Taiwan, 2017, pp. 119--124. DOI: https://doi.org/10.1109/ITC-ASIA.2017.8097125
    4. Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’17), Thessaloniki, Greece, 2017, pp. 237--239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
    5. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, 6 (2017), pp. 957--970. DOI: https://doi.org/10.1109/TC.2016.2616405
    6. Towards aging-induced approximations. H. Amrouch; B. Khaleghi; A. Gerstlauer and J. Henkel. In 54th ACM/EDAC/IEEE Design Automation Conference (DAC’17), 2017, pp. 1–6.
    7. Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
    8. Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968247
    9. Probabilistic Sensitization Analysis for Variation-Aware Path Delay Fault Test Evaluation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968226
    10. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    11. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    12. Special Session on Early Life Failures. Jyotirmoy Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017. DOI: https://doi.org/10.1109/VTS.2017.7928933
    13. Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1--6. DOI: https://doi.org/10.1109/VTS.2017.7928921
    14. Impact of BTI on dynamic and static power: From the physical to circuit level. H. Amrouch; S. Mishra; V. van Santen; S. Mahapatra and J. Henkel. In 017 IEEE International Reliability Physics Symposium (IRPS’17), 2017, pp. CR-3.1-CR-3.6.
    15. Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). J. Henkel; S. Pagani; H. Amrouch; L. Bauer and F. Samie. In Design, Automation Test in Europe Conference Exhibition (DATE’17), 2017, pp. 954–959.
    16. Containing guardbands. H. Amrouch and J. Henkel. In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC’17), 2017, pp. 537–542.
    17. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’17), Fort Worth, Texas, USA, 2017, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2017.8242055
    18. Optimizing Temperature Guardbands. Hussam Amrouch; Behnam Khaleghi and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’17), Lausanne, Switzerland, 2017, pp. 175--180.
    19. Interdependencies of Degradation Effects and Their Impact on Computing. H. Amrouch; V. M. van Santen and J. Henkel. IEEE Design and Test Magazine (DNT’17) 34, 3 (2017), pp. 59–67.
    20. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
    21. Special session: emerging (Un-)reliability based security threats and mitigations for embedded systems. H. Amrouch; P. Krishnamurthy; N. Patel; J. Henkel; R. Karri and F. Khorrami. In International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES’17), 2017, pp. 1–10.
    22. Semi-symbolic operational computation for robust control system design. Leandro Gil and Martin Radetzki. In 22nd International Conference on Methods and Models in Automation and Robotics, MMAR 2017, Miedzyzdroje, Poland, August 28-31, 2017, 2017, pp. 779--784. DOI: https://doi.org/10.1109/MMAR.2017.8046927
    23. Low power memory allocation and mapping for area-constrained systems-on-chips. Manuel Strobel; Marcus Eggenberger and Martin Radetzki. EURASIP J. Emb. Sys. 2017, (2017), pp. 2. DOI: https://doi.org/10.1186/s13639-016-0039-5
    24. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    25. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    26. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    27. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    28. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    29. Evaluating and Mitigating Degradation Effects in Multimedia Circuits. Hussam Amrouch and Jörg Henkel. In Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia’17), Seoul, Republic of Korea, 2017, pp. 61--67.
    30. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    31. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    32. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    33. Hybrid instruction set simulation for fast and accurate memory access profiling. Manuel Strobel and Martin Radetzki. In 13th Workshop on Intelligent Solutions in Embedded Systems, WISES 2017, Hamburg, Germany, June 12-13, 2017, 2017, pp. 23--28. DOI: https://doi.org/10.1109/WISES.2017.7986927
  4. 2016

    1. Designing reliable, yet energy-efficient guardbands. J. Henkel and H. Amrouch. In IEEE International Conference on Electronics, Circuits and Systems (ICECS’16), 2016, pp. 540–543.
    2. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    3. A Neural-Network-Based Fault Classifier. Laura Rodríguez Gómez and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 144--149. DOI: https://doi.org/10.1109/ATS.2016.46
    4. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    5. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
    6. Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 246--251. DOI: https://doi.org/10.1109/ATS.2016.18
    7. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
    8. Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
    9. Power and thermal management in massive multicore chips: Theoretical foundation meets architectural innovation and resource allocation. P. Bogdan; P. P. Pande; H. Amrouch; M. Shafique and J. Henkel. In 2016 International Conference on Compliers, Architectures, and Sythesis  of Embedded Systems (CASES’16), 2016, pp. 1–2.
    10. Applying Efficient Fault Tolerance to Enable the Preconditioned  Conjugate Gradient Solver on Approximate Computing Hardware. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance  in VLSI and Nanotechnology Systems (DFT’16), University of Connecticut, USA, 2016, pp. 21–26. DOI: https://doi.org/10.1109/DFT.2016.7684063
    11. Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. B. Khaleghi; B. Omidi; H. Amrouch; J. Henkel and H. Asadi. In 26th International Conference on Field Programmable Logic and Applications (FPL’16), 2016, pp. 1–8.
    12. Pushing the Limits: How Fault Tolerance Extends the Scope of Approximate  Computing. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’16), Sant Feliu de Guixols, Catalunya, Spain, 2016, pp. 133--136. DOI: https://doi.org/10.1109/IOLTS.2016.7604686
    13. Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS’16), Amsterdam, The Netherlands, 2016, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
    14. SHIVA: Sichere Hardware in der Informationsverarbeitung. Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 2016.
    15. Fault Tolerance of Approximate Compute Algorithms. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 34th VLSI Test Symposium (VTS’16), Caesars Palace, Las Vegas, Nevada, USA, 2016. DOI: https://doi.org/10.1109/VTS.2016.7477307
    16. Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS’16), Foz do Iguaçu, Brazil, 2016, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
    17. Aging-aware voltage scaling. V. M. van Santen; H. Amrouch; N. Parihar; S. Mahapatra and J. Henkel. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE’16), 2016, pp. 576–581.
    18. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    19. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16), Toulouse, France, 2016, pp. 251--262. DOI: https://doi.org/10.1109/DSN.2016.31
    20. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    21. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    22. Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Gert Schley; Ibrahim Ahmed; Muhammad Afzal and Martin Radetzki. Computers & Electrical Engineering 51, (2016), pp. 195--206. DOI: https://doi.org/10.1016/j.compeleceng.2016.02.013
    23. Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. Marcus Eggenberger; Manuel Strobel and Martin Radetzki. In 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, 2016, pp. 763--770. DOI: https://doi.org/10.1109/PDP.2016.118
    24. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    25. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    26. Reliability-aware design to suppress aging. H. Amrouch; B. Khaleghi; A. Gerstlauer and J. Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), 2016, pp. 1–6, redHiPEAC Paper Award.
    27. Designing guardbands for instantaneous aging effects. V. M. van Santen; H. Amrouch; J. Martin-Martinez; M. Nafria and J. Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), 2016, pp. 1–6, redHiPEAC Paper Award.
    28. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    29. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    30. Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. Leandro Gil and Martin Radetzki. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 499--504.
    31. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
    32. Improving Mobile Gaming Performance Through Cooperative CPU-GPU Thermal Management. Alok Prakash; Hussam Amrouch; Muhammad Shafique; Tulika Mitra and Jörg Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), Austin, Texas, 2016, pp. 47:1--47:6.
  5. 2015

    1. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    2. Reliability degradation in the scope of aging -- From physical to system level. H. Amrouch and J. Henkel. In 10th International Design Test Symposium (IDT’15), 2015, pp. 9–12.
    3. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    4. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    5. Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. Michael Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omana; Cecilia Metra and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 157–162. DOI: https://doi.org/10.1109/ATS.2015.34
    6. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD’15), Austin, Texas, USA, 2015, pp. 38–45.
    7. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
    8. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI  and Nanotechnology Systems (DFT’15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
    9. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate  Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 95--100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
    10. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    11. Lucid infrared thermography of thermally-constrained processors. H. Amrouch and J. Henkel. In 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’15), 2015, pp. 347–352.
    12. Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, 3 (2015), pp. 149--158. DOI: https://doi.org/10.1515/itit-2014-1082
    13. High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 3 (2015), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2714564
    14. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    15. Connecting the physical and application level towards grasping aging effects. H. Amrouch; J. Martin-Martinez; V. M. van Santen; M. Moras; R. Rodriguez; M. Nafria and J. Henkel. In IEEE International Reliability Physics Symposium (IRPS’15), 2015, pp. 3D.1.1-3D.1.8.
    16. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    17. On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 589--592. DOI: https://doi.org/10.7873/DATE.2015.0940
    18. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    19. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    20. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
    21. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    22. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    23. Optimal memory selection for low power embedded systems. Marcus Eggenberger and Martin Radetzki. In 12th International Workshop on Intelligent Solutions in Embedded Systems, WISES 2015, Ancona, Italy, October 29-30, 2015, 2015, pp. 11--16.
    24. Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. Gert Schley and Martin Radetzki. In 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, 2015, pp. 379--386. DOI: https://doi.org/10.1109/PDP.2015.36
    25. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    26. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, 2015, pp. 5:1--5:8. DOI: https://doi.org/10.1145/2786572.2788708
    27. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    28. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
  6. 2014

    1. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    2. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    3. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    4. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23. DOI: https://doi.org/10.1109/ICCAD.2014.7001324
    5. Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine(BIBM’14), Belfast, United Kingdom, 2014, pp. 424--431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
    6. Towards interdependencies of aging mechanisms. H. Amrouch; V. M. van Santen; T. Ebi; V. Wenzel and J. Henkel. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’14), 2014, pp. 478–485.
    7. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2014.7035360
    8. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2014.7035350
    9. Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 5 (2014), pp. 527--540. DOI: https://doi.org/10.1007/s10836-014-5477-1
    10. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 4 (2014), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2647955
    11. SAT-Based ATPG beyond Stuck-at Fault Testing. Sybille Hellebrand and Hans-Joachim Wunderlich. it - Information Technology 56, 4 (2014), pp. 165--172. DOI: https://doi.org/10.1515/itit-2013-1043
    12. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
    13. A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’14), Atlanta, Georgia, USA, 2014, pp. 443--454. DOI: https://doi.org/10.1109/DSN.2014.48
    14. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 4 (2014), pp. 401--413. DOI: https://doi.org/10.1007/s10836-014-5459-3
    15. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--6. DOI: https://doi.org/10.1145/2593069.2593146
    16. Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Ulrich Abelein and Piet Engelke. In Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--9. DOI: https://doi.org/10.1145/2593069.2602971
    17. Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 3 (2014), pp. 28:1--28:17. DOI: https://doi.org/10.1145/2611760
    18. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
    19. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
    20. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
    21. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE’14 Conference, Dresden, Germany, 2014.
    22. Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures. Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.373
    23. Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
    24. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    25. hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding. D. Palomino; M. Shafique; H. Amrouch; A. Susin and J. Henkel. In Design, Automation Test in Europe Conference Exhibition (DATE’14), 2014, pp. 1–4.
    26. mDTM: Multi-objective dynamic thermal management for on-chip systems. H. Khdr; T. Ebi; M. Shafique; H. Amrouch and J. H. Karlsruhe. In Design, Automation Test in Europe Conference Exhibition (DATE’14), 2014, pp. 1–6.
    27. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, 6--7 (2014), pp. 1066--1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
    28. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    29. A comparison of parallel systemc simulation approaches at RTL. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119355
    30. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    31. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    32. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
    33. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    34. SystemC AMS power electronic modeling with ideal instantaneous switches. Leandro Gil and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119365
    35. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262--285.
    36. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    37. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    38. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    39. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    40. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    41. Asynchronous parallel simulation with transaction events. Bastian Haetzer and Martin Radetzki. In XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, 2014, pp. 242--249. DOI: https://doi.org/10.1109/SAMOS.2014.6893217
    42. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    43. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    44. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    45. RESI: Register-Embedded Self-Immunity for Reliability Enhancement. H. Amrouch; T. Ebi and J. Henkel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’14) 33, 5 (2014), pp. 677–690.
    46. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    47. Editorial introduction - Special issue on languages, models and model based design for embedded systems. Martin Radetzki and Axel Jantsch. Design Autom. for Emb. Sys. 18, 1–2 (2014), pp. 61--62. DOI: https://doi.org/10.1007/s10617-012-9094-x
  7. 2013

    1. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    2. Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
    3. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI: https://doi.org/10.1109/DFT.2013.6653580
    4. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    5. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
    6. Analyzing the thermal hotspots in FPGA-based embedded systems. H. Amrouch; T. Ebi; J. Schneider; S. Parameswaran and J. Henkel. In 23rd International Conference on Field programmable Logic and Applications (FPL’13), 2013, pp. 1–4.
    7. Test Strategies for Reliable Runtime Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. IEEE Transactions on Computers 62, 8 (2013), pp. 1494--1507. DOI: https://doi.org/10.1109/TC.2013.53
    8. Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS’13), Crete, Greece, 2013, pp. 240--243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
    9. Stress balancing to mitigate NBTI effects in register files. H. Amrouch; T. Ebi and J. Henkel. In 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’13), 2013, pp. 1–10.
    10. Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS’13), Avignon, France, 2013, pp. 39--45. DOI: https://doi.org/10.1109/ETS.2013.6569354
    11. Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW’13), Cordoba, Argentina, 2013.
    12. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip. Andreas Herkersdorf; Michael Engel; Michael Glaß; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. In Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 2013.
    13. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 436--441. DOI: https://doi.org/10.7873/DATE.2013.098
    14. Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 276--281. DOI: https://doi.org/10.7873/DATE.2013.069
    15. Thermal management for dependable on-chip systems. J. Henkel; T. Ebi; H. Amrouch and H. Khdr. In 18th Asia and South Pacific Design Automation Conference (ASP-DAC’13), 2013, pp. 113–118.
    16. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    17. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    18. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    19. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    20. Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits. A. Amouri; H. Amrouch; T. Ebi; J. Henkel and M. Tahoori. In IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’13), 2013, pp. 57–60, redHiPEAC Paper Award.
    21. Fine grained adaptive simulation with application to NoCs. Marcus Eggenberger and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--8.
    22. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    23. Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Weiyun Lu and Martin Radetzki. Microprocessors and Microsystems - Embedded Hardware Design 37, 2 (2013), pp. 115--128. DOI: https://doi.org/10.1016/j.micpro.2012.09.005
    24. Simulation analysis and validation. Frank Oppenheimer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    25. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
    26. Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. Gert Schley; Nikolaos Batzolis and Martin Radetzki. In 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013, pp. 454--461. DOI: https://doi.org/10.1109/PDP.2013.74
    27. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Aza; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    28. Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. Adán Kohler and Martin Radetzki. In 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, Physical and Social Computing (CPSCom), Beijing, China, August 20-23, 2013, 2013, pp. 77--85. DOI: https://doi.org/10.1109/GreenCom-iThings-CPSCom.2013.38
    29. Platform based design. Jean-Philippe Babau and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    30. Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. Khalid Latif; Amir-Mohammad Rahmani; Ethiopia Nigussie; Tiberiu Seceleanu; Martin Radetzki and Hannu Tenhunen. J. Electronic Testing 29, 3 (2013), pp. 431--452. DOI: https://doi.org/10.1007/s10836-013-5389-5
    31. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Aza; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    32. Optimal placement of vertical connections in 3D Network-on-Chip. Thomas Canhao Xu; Gert Schley; Pasi Liljeberg; Martin Radetzki; Juha Plosila and Hannu Tenhunen. Journal of Systems Architecture - Embedded Systems Design 59, 7 (2013), pp. 441--454. DOI: https://doi.org/10.1016/j.sysarc.2013.05.002
    33. Systemc transaction level modeling with transaction events. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--6.
    34. Methods for fault tolerance in networks-on-chip. Martin Radetzki; Chaochao Feng; Xueqian Zhao and Axel Jantsch. ACM Comput. Surv. 46, 1 (2013), pp. 8:1--8:38. DOI: https://doi.org/10.1145/2522968.2522976
    35. Scalable parallel simulation of networks on chip. Marcus Eggenberger and Martin Radetzki. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013, 2013, pp. 1--8. DOI: https://doi.org/10.1109/NoCS.2013.6558402
    36. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
  8. 2012

    1. Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
    2. Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, 12 (2012), pp. 1908--1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
    3. Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 155--160. DOI: https://doi.org/10.1109/ATS.2012.23
    4. Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 214--219. DOI: https://doi.org/10.1109/ATS.2012.32
    5. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    6. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
    7. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’12), Philadelphia, Pennsylvania, USA, 2012, pp. 1--6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
    8. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
    9. Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012, pp. 37--42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
    10. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, Germany, 2012, pp. 38--45. DOI: https://doi.org/10.1109/AHS.2012.6268667
    11. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS’12), Hyatt Maui, Hawaii, USA, 2012, pp. 50--55. DOI: https://doi.org/10.1109/VTS.2012.6231079
    12. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW’12), Quito, Ecuador, 2012, pp. 1--4. DOI: https://doi.org/10.1109/LATW.2012.6261229
    13. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    14. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12), Montreal, Canada, 2012, pp. 207--212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
    15. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. Alejandro Cook; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 146--151. DOI: https://doi.org/10.1109/ETS.2012.6233025
    16. Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 98--103. DOI: https://doi.org/10.1109/ETS.2012.6233017
    17. Efficient System-Level Aging Prediction. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 164--169. DOI: https://doi.org/10.1109/ETS.2012.6233028
    18. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    19. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    20. Semantics and efficient simulation of accuracy-adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. Design Autom. for Emb. Sys. 16, 3 (2012), pp. 1--29. DOI: https://doi.org/10.1007/s10617-012-9095-9
    21. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    22. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    23. Low-Latency Collectives for the Intel SCC. Adán Kohler; Martin Radetzki; Philipp Gschwandtner and Thomas Fahringer. In 2012 IEEE International Conference on Cluster Computing, CLUSTER 2012, Beijing, China, September 24-28, 2012, 2012, pp. 346--354. DOI: https://doi.org/10.1109/CLUSTER.2012.58
    24. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    25. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    26. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    27. Optimized Reduce for Mesh-Based NoC Multiprocessors. Adán Kohler and Martin Radetzki. In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, 2012, pp. 904--913. DOI: https://doi.org/10.1109/IPDPSW.2012.111
    28. COOL: Control-based Optimization of Load-balancing for Thermal Behavior. Thomas Ebi; Hussam Amrouch and Jörg Henkel. In Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’12), Tampere, Finland, 2012, pp. 255--264.
    29. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    30. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    31. Latency-optimized Collectives for High Performance on Intel’s Single-chip Cloud Computer. Adán Kohler and Martin Radetzki. In Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, November 29th-30th 2012, Aachen, Germany, 2012, pp. 7--12.
    32. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    33. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
    34. Minimal MPI as programming interface for multicore System-on-Chips. Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross and Martin Radetzki. In Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, 2012, pp. 127--134.
    35. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    36. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
  9. 2011

    1. Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 383--388. DOI: https://doi.org/10.1109/ATS.2011.52
    2. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
    3. Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 285--290. DOI: https://doi.org/10.1109/ATS.2011.55
    4. Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 213--218. DOI: https://doi.org/10.1109/ATS.2011.60
    5. Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS’11), Taipei, Taiwan, 2011, pp. 69--78. DOI: https://doi.org/10.1145/2039370.2039384
    6. Robuster Selbsttest mit Diagnose. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 48--53.
    7. Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 76--83.
    8. Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 43--47.
    9. P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
    10. A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing. Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara and Laung-Terng Wang. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139162
    11. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    12. Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults. Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich and Christian G. Zoellin. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1784--1796. DOI: https://doi.org/10.1007/s11432-011-4366-9
    13. SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures. Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, 2011, pp. 33--38. DOI: https://doi.org/10.1109/ISLPED.2011.5993600
    14. Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 169--174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
    15. Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 278--283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
    16. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 111--116. DOI: https://doi.org/10.1109/ETS.2011.25
    17. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 183--188. DOI: https://doi.org/10.1109/ETS.2011.33
    18. Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing. Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard and Mohammad Tehranipoor. In Proceedings of the 29th IEEE VLSI Test Symposium (VTS’11), Dana Point, California, USA, 2011, pp. 166--171. DOI: https://doi.org/10.1109/VTS.2011.5783778
    19. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011, pp. 1303--1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
    20. Self-Immunity Technique to Improve Register File Integrity Against Soft Errors. H. Amrouch and J. Henkel. In 2011 24th Internatioal Conference on VLSI Design (VLSID’11), 2011, pp. 189–194.
    21. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011, pp. 55--58.
    22. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    23. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    24. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    25. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    26. Cost-Based Deflection Routing for Intelligent NoC Switches. Martin Radetzki and Adán Kohler. In Solutions on Embedded Systems, Massimo Conti; Simone Orcioni; Natividad Mart Madrid and Ralf E. D. Seepold (eds.). Springer, 2011, pp. 77--90. DOI: https://doi.org/10.1007/978-94-007-0638-5_6
    27. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    28. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    29. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    30. A case study on message-based discrete event simulation for Transaction Level Modeling. Bastian Haetzer and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    31. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    32. Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. Martin Radetzki. In IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, Melbourne, Australia, October 24-26, 2011, 2011, pp. 33--40. DOI: https://doi.org/10.1109/EUC.2011.36
    33. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    34. Efficient Fault Simulation of SystemC Designs. Weiyun Lu and Martin Radetzki. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, 2011, pp. 487--494. DOI: https://doi.org/10.1109/DSD.2011.68
    35. A metamodel and semantics for transaction level modeling. Rauf Salimi Khaligh and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    36. Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 6th Workshop on Embedded Systems Education, WESE 2011, Taipei, Taiwan, October 13, 2011, 2011, pp. 1--8. DOI: https://doi.org/10.1145/2077370.2077371
    37. Optimal distribution of privileged nodes in networks-on-chip. Gert Schley and Martin Radetzki. In Proceedings of the Ninth Workshop on Intelligent Solutions in Embedded Systems, WISES 2011, Regensburg, Germany, July 7-8, 2011, 2011, pp. 87--92.
  10. 2010

    1. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 3--8. DOI: https://doi.org/10.1109/ATS.2010.10
    2. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T’10), Austin, Texas, USA, 2010.
    3. Efficient Concurrent Self-Test with Partially Specified Patterns. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 26, 5 (2010), pp. 581--594. DOI: https://doi.org/10.1007/s10836-010-5167-6
    4. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’10), Wildbad Kreuth, Germany, 2010, pp. 25--32.
    5. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen;  Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, 4 (2010), pp. 209--215. DOI: https://doi.org/10.1524/itit.2010.0593
    6. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 2010.
    7. Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC’10), Anaheim, California, USA, 2010, pp. 380--385. DOI: https://doi.org/10.1145/1837274.1837369
    8. Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS’10), Praha, Czech Republic, 2010, pp. 253--253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
    9. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS’10), Santa Cruz, California, USA, 2010, pp. 93--98. DOI: https://doi.org/10.1109/VTS.2010.5469607
    10. BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 1243--1248.
    11. Parity Prediction Synthesis for Nano-Electronic Gate Designs. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699312
    12. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
    13. Application Dependent Vulnerability of Combinational Circuits. Rafal Baranowski and Hans-Joachim Wunderlich. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    14. Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    15. Models in Hardware Testing. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.2010. DOI: https://doi.org/10.1007/978-90-481-3282-9
    16. A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 2010 Forum on specification & Design Languages,FDL 2010, September 14-16, 2010, Southampton, UK, 2010, pp. 130--135.
    17. Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133--155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
    18. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    19. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    20. Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). Gert Schley; Martin Radetzki and Adán Kohler. it - Information Technology 52, 4 (2010), pp. 201--208. DOI: https://doi.org/10.1524/itit.2010.0592
    21. Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187--215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
    22. Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117--146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
    23. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    24. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    25. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    26. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010, pp. 1183--1188. DOI: https://doi.org/10.1109/DATE.2010.5456987
    27. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    28. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    29. Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. Adán Kohler; Gert Schley and Martin Radetzki. IEEE Trans. on CAD of Integrated Circuits and Systems 29, 6 (2010), pp. 883--896. DOI: https://doi.org/10.1109/TCAD.2010.2048399
    30. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
  11. 2009

    1. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’09), Stuttgart, Germany, 2009, pp. 21--28.