Publikationen

Publikationen des Instituts

Publikationen

  1. 2019

    1. Combined MPSoC Task Mapping and Memory Optimization for Low-Power. Manuel Strobel; Gereon Führ; Martin Radetzki and Rainer Leupers. In to appear in Proc. IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Bangkok, Thailand, 2019.
    2. A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. Jie Hou; Q. Han and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, 2019.
    3. Design-Time Memory Subsystem Optimization for Low- Power Multi-Core Embedded Systems. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded (MCSoC), Singapore, 2019.
    4. A Methodology to Compute Long-Term Fault Resilience of NoCs under Fault-Tolerant Routing Algorithms. Jie Hou and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages(FDL), Southampton, UK, 2019.
    5. Power-Mode-Aware Memory Subsystem Optimization for Low-Power System-on-Chip Design. Manuel Strobel and Martin Radetzki. To appear in ACM Transactions on Embedded Computing Systems(TECS) (2019).
    6. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
    7. A Backend Tool for the Integration of Memory Optimizations into Embedded Software. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages (FDL), Southampton, UK, 2019.
    8. Automated Sensor Firmware Development - Generation, Optimization, and Analysis. Jens Rudolf; Manuel Strobel; Joscha Benz; Cristian Haubelt; Martin Radetzki and Oliver Bringmann. In MBMV 2019; 22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019, pp. 1–12.
    9. Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In to appear in Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019.
    10. Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395--416. DOI: https://doi.org/10.1049/PBPC022E_ch16
    11. Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans Joachim Wunderlich. In to appear in Proceedings of the IEEE International Test Conference(ITC’19), Washington DC, USA, 2019.
    12. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    13. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
    14. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    15. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
    16. On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’19), Florence, Italy, 2019, pp. 1016--1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
    17. Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (2019), pp. 78--91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
    18. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems (TCAD) 38, 10 (2019), pp. 1956–1968. DOI: https://doi.org/10.1109/TCAD.2018.2864255
  2. 2018

    1. Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. Jie Hou and Martin Radetzki. In 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2018, Cambridge, United Kingdom, March 21-23, 2018, 2018, pp. 609--616. DOI: https://doi.org/10.1109/PDP2018.2018.00102
    2. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    3. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    4. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    5. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    6. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    7. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    8. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
    9. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    10. Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, 1 (2018), pp. 1--1. DOI: https://doi.org/10.1109/LES.2018.2789942
    11. Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures  in Low-Power Scan Testing. Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 149--154. DOI: https://doi.org/10.1109/ATS.2018.00037
    12. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
    13. Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, 3 (2018), pp. 5--6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
    14. Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2018.8400685
    15. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
    16. Detecting and Resolving Security Violations in Reconfigurable Scan Networks. Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the 24th IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’18), Platja d’Aro, Spain, 2018, pp. 91--96. DOI: https://doi.org/10.1109/IOLTS.2018.8474188
    17. Device aging: A reliability and security concern. Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit Singh; Hans-Joachim Wunderlich and Naghmeh Karimi. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2018.8400702

Frühere Publikationen

  1. 2017

    1. Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
    2. Low power memory allocation and mapping for area-constrained systems-on-chips. Manuel Strobel; Marcus Eggenberger and Martin Radetzki. EURASIP J. Emb. Sys. 2017, (2017), pp. 2. DOI: https://doi.org/10.1186/s13639-016-0039-5
    3. Hybrid instruction set simulation for fast and accurate memory access profiling. Manuel Strobel and Martin Radetzki. In 13th Workshop on Intelligent Solutions in Embedded Systems, WISES 2017, Hamburg, Germany, June 12-13, 2017, 2017, pp. 23--28. DOI: https://doi.org/10.1109/WISES.2017.7986927
    4. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Trans. Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    5. Semi-symbolic operational computation for robust control system design. Leandro Gil and Martin Radetzki. In 22nd International Conference on Methods and Models in Automation and Robotics, MMAR 2017, Miedzyzdroje, Poland, August 28-31, 2017, 2017, pp. 779--784. DOI: https://doi.org/10.1109/MMAR.2017.8046927
    6. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    7. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    8. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    9. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    10. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    11. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    12. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    13. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    14. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
    15. Probabilistic Sensitization Analysis for Variation-Aware Path Delay Fault Test Evaluation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968226
    16. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, 6 (2017), pp. 957--970. DOI: https://doi.org/10.1109/TC.2016.2616405
    17. Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968247
    18. Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’17), Thessaloniki, Greece, 2017, pp. 237--239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
    19. Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1--6. DOI: https://doi.org/10.1109/VTS.2017.7928921
    20. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    21. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (2017), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    22. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’17), Fort Worth, Texas, USA, 2017, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2017.8242055
    23. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    24. Trustworthy Reconfigurable Access to On-Chip Infrastructure. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 1st International Test Conference in Asia (ITC-Asia’17), Taipei, Taiwan, 2017, pp. 119--124. DOI: https://doi.org/10.1109/ITC-ASIA.2017.8097125
    25. Special Session on Early Life Failures. Jyotirmoy Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017. DOI: https://doi.org/10.1109/VTS.2017.7928933
    26. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
  2. 2016

    1. Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
    2. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.
    3. Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Gert Schley; Ibrahim Ahmed; Muhammad Afzal and Martin Radetzki. Computers & Electrical Engineering 51, (2016), pp. 195--206. DOI: https://doi.org/10.1016/j.compeleceng.2016.02.013
    4. Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. Leandro Gil and Martin Radetzki. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 499--504.
    5. Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. Marcus Eggenberger; Manuel Strobel and Martin Radetzki. In 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, 2016, pp. 763--770. DOI: https://doi.org/10.1109/PDP.2016.118
    6. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    7. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    8. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
    9. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    10. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    11. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    12. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    13. Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 246--251. DOI: https://doi.org/10.1109/ATS.2016.18
    14. Applying Efficient Fault Tolerance to Enable the Preconditioned  Conjugate Gradient Solver on Approximate Computing Hardware. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance  in VLSI and Nanotechnology Systems (DFT’16), University of Connecticut, USA, 2016, pp. 21–26. DOI: https://doi.org/10.1109/DFT.2016.7684063
    15. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    16. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    17. Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS’16), Amsterdam, The Netherlands, 2016, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
    18. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    19. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
    20. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
    21. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16), Toulouse, France, 2016, pp. 251--262. DOI: https://doi.org/10.1109/DSN.2016.31
    22. SHIVA: Sichere Hardware in der Informationsverarbeitung. Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 2016.
    23. Pushing the Limits: How Fault Tolerance Extends the Scope of Approximate  Computing. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’16), Sant Feliu de Guixols, Catalunya, Spain, 2016, pp. 133--136. DOI: https://doi.org/10.1109/IOLTS.2016.7604686
    24. Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS’16), Foz do Iguaçu, Brazil, 2016, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
    25. A Neural-Network-Based Fault Classifier. Laura Rodríguez Gómez and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 144--149. DOI: https://doi.org/10.1109/ATS.2016.46
    26. Fault Tolerance of Approximate Compute Algorithms. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 34th VLSI Test Symposium (VTS’16), Caesars Palace, Las Vegas, Nevada, USA, 2016. DOI: https://doi.org/10.1109/VTS.2016.7477307
  3. 2015

    1. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    2. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    3. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
    4. Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. Gert Schley and Martin Radetzki. In 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, 2015, pp. 379--386. DOI: https://doi.org/10.1109/PDP.2015.36
    5. Optimal memory selection for low power embedded systems. Marcus Eggenberger and Martin Radetzki. In 12th International Workshop on Intelligent Solutions in Embedded Systems, WISES 2015, Ancona, Italy, October 29-30, 2015, 2015, pp. 11--16.
    6. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, 2015, pp. 5:1--5:8. DOI: https://doi.org/10.1145/2786572.2788708
    7. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
    8. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    9. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    10. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    11. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    12. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    13. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    14. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    15. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
    16. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    17. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate  Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 95--100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
    18. High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 3 (2015), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2714564
    19. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    20. Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, 3 (2015), pp. 149--158. DOI: https://doi.org/10.1515/itit-2014-1082
    21. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD’15), Austin, Texas, USA, 2015, pp. 38–45.
    22. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
    23. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI  and Nanotechnology Systems (DFT’15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
    24. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    25. Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. Michael Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omana; Cecilia Metra and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 157–162. DOI: https://doi.org/10.1109/ATS.2015.34
    26. On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 589--592. DOI: https://doi.org/10.7873/DATE.2015.0940
  4. 2014

    1. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    2. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE’14 Conference, Dresden, Germany, 2014.
    3. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262--285.
    4. SystemC AMS power electronic modeling with ideal instantaneous switches. Leandro Gil and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119365
    5. Asynchronous parallel simulation with transaction events. Bastian Haetzer and Martin Radetzki. In XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, 2014, pp. 242--249. DOI: https://doi.org/10.1109/SAMOS.2014.6893217
    6. Editorial introduction - Special issue on languages, models and model based design for embedded systems. Martin Radetzki and Axel Jantsch. Design Autom. for Emb. Sys. 18, 1–2 (2014), pp. 61--62. DOI: https://doi.org/10.1007/s10617-012-9094-x
    7. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    8. A comparison of parallel systemc simulation approaches at RTL. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119355
    9. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    10. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    11. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
    12. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    13. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    14. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    15. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
    16. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    17. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    18. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    19. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    20. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    21. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    22. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
    23. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    24. A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’14), Atlanta, Georgia, USA, 2014, pp. 443--454. DOI: https://doi.org/10.1109/DSN.2014.48
    25. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 4 (2014), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2647955
    26. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, 6--7 (2014), pp. 1066--1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
    27. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
    28. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2014.7035360
    29. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
    30. Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 5 (2014), pp. 527--540. DOI: https://doi.org/10.1007/s10836-014-5477-1
    31. Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Ulrich Abelein and Piet Engelke. In Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--9. DOI: https://doi.org/10.1145/2593069.2602971
    32. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
    33. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    34. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2014.7035350
    35. Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’14), Belfast, United Kingdom, 2014, pp. 424--431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
    36. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23.
    37. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    38. Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 3 (2014), pp. 28:1--28:17. DOI: https://doi.org/10.1145/2611760
    39. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    40. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    41. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
    42. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 4 (2014), pp. 401--413. DOI: https://doi.org/10.1007/s10836-014-5459-3
    43. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
    44. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--6. DOI: https://doi.org/10.1145/2593069.2593146
    45. SAT-Based ATPG beyond Stuck-at Fault Testing. Sybille Hellebrand and Hans-Joachim Wunderlich. it - Information Technology 56, 4 (2014), pp. 165--172. DOI: https://doi.org/10.1515/itit-2013-1043
    46. Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures. Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.373
    47. Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
  5. 2013

    1. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip. Andreas Herkersdorf; Michael Engel; Michael Glaß; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. In Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 2013.
    2. Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW’13), Cordoba, Argentina, 2013.
    3. Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. Gert Schley; Nikolaos Batzolis and Martin Radetzki. In 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013, pp. 454--461. DOI: https://doi.org/10.1109/PDP.2013.74
    4. Simulation analysis and validation. Frank Oppenheimer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    5. Fine grained adaptive simulation with application to NoCs. Marcus Eggenberger and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--8.
    6. Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. Khalid Latif; Amir-Mohammad Rahmani; Ethiopia Nigussie; Tiberiu Seceleanu; Martin Radetzki and Hannu Tenhunen. J. Electronic Testing 29, 3 (2013), pp. 431--452. DOI: https://doi.org/10.1007/s10836-013-5389-5
    7. Optimal placement of vertical connections in 3D Network-on-Chip. Thomas Canhao Xu; Gert Schley; Pasi Liljeberg; Martin Radetzki; Juha Plosila and Hannu Tenhunen. Journal of Systems Architecture - Embedded Systems Design 59, 7 (2013), pp. 441--454. DOI: https://doi.org/10.1016/j.sysarc.2013.05.002
    8. Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. Adán Kohler and Martin Radetzki. In 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, Physical and Social Computing (CPSCom), Beijing, China, August 20-23, 2013, 2013, pp. 77--85. DOI: https://doi.org/10.1109/GreenCom-iThings-CPSCom.2013.38
    9. Systemc transaction level modeling with transaction events. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--6.
    10. Platform based design. Jean-Philippe Babau and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    11. Scalable parallel simulation of networks on chip. Marcus Eggenberger and Martin Radetzki. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013, 2013, pp. 1--8. DOI: https://doi.org/10.1109/NoCS.2013.6558402
    12. Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Weiyun Lu and Martin Radetzki. Microprocessors and Microsystems - Embedded Hardware Design 37, 2 (2013), pp. 115--128. DOI: https://doi.org/10.1016/j.micpro.2012.09.005
    13. Methods for fault tolerance in networks-on-chip. Martin Radetzki; Chaochao Feng; Xueqian Zhao and Axel Jantsch. ACM Comput. Surv. 46, 1 (2013), pp. 8:1--8:38. DOI: https://doi.org/10.1145/2522968.2522976
    14. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    15. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    16. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    17. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    18. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    19. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    20. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    21. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
    22. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    23. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
    24. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    25. Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
    26. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    27. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI: https://doi.org/10.1109/DFT.2013.6653580
    28. Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS’13), Crete, Greece, 2013, pp. 240--243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
    29. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 436--441. DOI: https://doi.org/10.7873/DATE.2013.098
    30. Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 276--281. DOI: https://doi.org/10.7873/DATE.2013.069
    31. Test Strategies for Reliable Runtime Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. IEEE Transactions on Computers 62, 8 (2013), pp. 1494--1507. DOI: https://doi.org/10.1109/TC.2013.53
    32. Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS’13), Avignon, France, 2013, pp. 39--45. DOI: https://doi.org/10.1109/ETS.2013.6569354
  6. 2012

    1. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    2. Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
    3. Low-Latency Collectives for the Intel SCC. Adán Kohler; Martin Radetzki; Philipp Gschwandtner and Thomas Fahringer. In 2012 IEEE International Conference on Cluster Computing, CLUSTER 2012, Beijing, China, September 24-28, 2012, 2012, pp. 346--354. DOI: https://doi.org/10.1109/CLUSTER.2012.58
    4. Minimal MPI as programming interface for multicore System-on-Chips. Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross and Martin Radetzki. In Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, 2012, pp. 127--134.
    5. Latency-optimized Collectives for High Performance on Intel’s Single-chip Cloud Computer. Adán Kohler and Martin Radetzki. In Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, November 29th-30th 2012, Aachen, Germany, 2012, pp. 7--12.
    6. Semantics and efficient simulation of accuracy-adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. Design Autom. for Emb. Sys. 16, 3 (2012), pp. 1--29. DOI: https://doi.org/10.1007/s10617-012-9095-9
    7. Optimized Reduce for Mesh-Based NoC Multiprocessors. Adán Kohler and Martin Radetzki. In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, 2012, pp. 904--913. DOI: https://doi.org/10.1109/IPDPSW.2012.111
    8. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    9. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    10. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    11. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    12. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    13. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    14. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
    15. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    16. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    17. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    18. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    19. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    20. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    21. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    22. Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 98--103. DOI: https://doi.org/10.1109/ETS.2012.6233017
    23. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’12), Philadelphia, Pennsylvania, USA, 2012, pp. 1--6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
    24. Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 214--219. DOI: https://doi.org/10.1109/ATS.2012.32
    25. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
    26. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12), Montreal, Canada, 2012, pp. 207--212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
    27. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW’12), Quito, Ecuador, 2012, pp. 1--4. DOI: https://doi.org/10.1109/LATW.2012.6261229
    28. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS’12), Hyatt Maui, Hawaii, USA, 2012, pp. 50--55. DOI: https://doi.org/10.1109/VTS.2012.6231079
    29. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
    30. Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, 12 (2012), pp. 1908--1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
    31. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, Germany, 2012, pp. 38--45. DOI: https://doi.org/10.1109/AHS.2012.6268667
    32. Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012, pp. 37--42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
    33. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    34. Efficient System-Level Aging Prediction. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 164--169. DOI: https://doi.org/10.1109/ETS.2012.6233028
    35. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. Alejandro Cook; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 146--151. DOI: https://doi.org/10.1109/ETS.2012.6233025
    36. Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 155--160. DOI: https://doi.org/10.1109/ATS.2012.23
  7. 2011

    1. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Ena, Gifu, Japan, 2011.
    2. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011.
    3. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011.
    4. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011, pp. 55--58.
    5. Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. Martin Radetzki. In IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, Melbourne, Australia, October 24-26, 2011, 2011, pp. 33--40. DOI: https://doi.org/10.1109/EUC.2011.36
    6. A metamodel and semantics for transaction level modeling. Rauf Salimi Khaligh and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    7. Cost-Based Deflection Routing for Intelligent NoC Switches. Martin Radetzki and Adán Kohler. In Solutions on Embedded Systems, Massimo Conti; Simone Orcioni; Natividad Mart\’ınez Madrid and Ralf E. D. Seepold (eds.). Springer, 2011, pp. 77--90. DOI: https://doi.org/10.1007/978-94-007-0638-5_6
    8. Efficient Fault Simulation of SystemC Designs. Weiyun Lu and Martin Radetzki. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, 2011, pp. 487--494. DOI: https://doi.org/10.1109/DSD.2011.68
    9. Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 6th Workshop on Embedded Systems Education, WESE 2011, Taipei, Taiwan, October 13, 2011, 2011, pp. 1--8. DOI: https://doi.org/10.1145/2077370.2077371
    10. A case study on message-based discrete event simulation for Transaction Level Modeling. Bastian Haetzer and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    11. Optimal distribution of privileged nodes in networks-on-chip. Gert Schley and Martin Radetzki. In Proceedings of the Ninth Workshop on Intelligent Solutions in Embedded Systems, WISES 2011, Regensburg, Germany, July 7-8, 2011, 2011, pp. 87--92.
    12. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    13. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    14. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    15. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    16. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    17. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    18. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    19. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    20. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    21. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    22. Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing. Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard and Mohammad Tehranipoor. In Proceedings of the 29th IEEE VLSI Test Symposium (VTS’11), Dana Point, California, USA, 2011, pp. 166--171. DOI: https://doi.org/10.1109/VTS.2011.5783778
    23. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    24. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 183--188. DOI: https://doi.org/10.1109/ETS.2011.33
    25. Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 213--218. DOI: https://doi.org/10.1109/ATS.2011.60
    26. Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 169--174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
    27. Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 383--388. DOI: https://doi.org/10.1109/ATS.2011.52
    28. Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 285--290. DOI: https://doi.org/10.1109/ATS.2011.55
    29. Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS’11), Taipei, Taiwan, 2011, pp. 69--78. DOI: https://doi.org/10.1145/2039370.2039384
    30. Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 43--47.
    31. Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 76--83.
    32. A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing. Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara and Laung-Terng Wang. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139162
    33. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011, pp. 1303--1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
    34. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 111--116. DOI: https://doi.org/10.1109/ETS.2011.25
    35. Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 278--283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
    36. P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
    37. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
    38. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    39. Robuster Selbsttest mit Diagnose. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 48--53.
    40. SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures. Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, 2011, pp. 33--38. DOI: https://doi.org/10.1109/ISLPED.2011.5993600
    41. Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults. Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich and Christian G. Zoellin. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1784--1796. DOI: https://doi.org/10.1007/s11432-011-4366-9
  8. 2010

    1. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    2. Application Dependent Vulnerability of Combinational Circuits. Rafal Baranowski and Hans-Joachim Wunderlich. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    3. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 2010.
    4. Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    5. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T’10), Austin, Texas, USA, 2010.
    6. Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187--215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
    7. Models in Hardware Testing. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.2010. DOI: https://doi.org/10.1007/978-90-481-3282-9
    8. Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117--146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
    9. Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133--155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
    10. Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). Gert Schley; Martin Radetzki and Adán Kohler. it - Information Technology 52, 4 (2010), pp. 201--208. DOI: https://doi.org/10.1524/itit.2010.0592
    11. A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 2010 Forum on specification & Design Languages,FDL 2010, September 14-16, 2010, Southampton, UK, 2010, pp. 130--135.
    12. Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. Adán Kohler; Gert Schley and Martin Radetzki. IEEE Trans. on CAD of Integrated Circuits and Systems 29, 6 (2010), pp. 883--896. DOI: https://doi.org/10.1109/TCAD.2010.2048399
    13. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010, pp. 1183--1188. DOI: https://doi.org/10.1109/DATE.2010.5456987
    14. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    15. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    16. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
    17. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    18. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    19. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    20. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    21. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 3--8. DOI: https://doi.org/10.1109/ATS.2010.10
    22. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    23. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
    24. Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS’10), Praha, Czech Republic, 2010, pp. 253--253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
    25. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS’10), Santa Cruz, California, USA, 2010, pp. 93--98. DOI: https://doi.org/10.1109/VTS.2010.5469607
    26. Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC’10), Anaheim, California, USA, 2010, pp. 380--385. DOI: https://doi.org/10.1145/1837274.1837369
    27. BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 1243--1248.
    28. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen;  Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, 4 (2010), pp. 209--215. DOI: https://doi.org/10.1524/itit.2010.0593
    29. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    30. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’10), Wildbad Kreuth, Germany, 2010, pp. 25--32.
    31. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 39--44. DOI: https://doi.org/10.1109/ATS.2010.16
    32. Parity Prediction Synthesis for Nano-Electronic Gate Designs. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699312
    33. Efficient Concurrent Self-Test with Partially Specified Patterns. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 26, 5 (2010), pp. 581--594. DOI: https://doi.org/10.1007/s10836-010-5167-6
  9. 2009

    1. Modellierung der Testinfrastruktur auf der Transaktionsebene. Michael A. Kochte; Christian Zöllin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In 21th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 61--66.
    2. Diagnose mit extrem kompaktierten Fehlerdaten. Stefan Holst and Hans-Joachim Wunderlich. In 21. ITG/GI/GMM Workshop “Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 15--20.
    3. Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen. Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (Eds.). Springer-Verlag Heidelberg.2009. DOI: https://doi.org/10.1007/978-3-540-85091-5
    4. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen. Hans-Joachim Wunderlich; Melanie Elm and Michael A. Kochte. In Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertungin frühen Entwicklungsphasen, Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (eds.). Springer-Verlag Heidelberg, 2009, pp. 391--464. DOI: https://doi.org/10.1007/978-3-540-85091-5_8
    5. Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. Adán Kohler and Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, 2009, pp. 207--216.
    6. An intelligent deflection router for networks-on-chip. Martin Radetzki and Adán Kohler. In Seventh Workshop on Intelligent solutions in Embedded Systems, WISES 2009, Ancona, Italy, June 25-26, 2009, 2009, pp. 57--62.
    7. Test exploration and validation using transaction level models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    8. A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. Adán Kohler and Martin Radetzki. In Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, 2009, pp. 1--4.
    9. Fault-tolerant architecture and deflection routing for degradable NoC switches. Adán Kohler and Martin Radetzki. In Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, 2009, pp. 22--31. DOI: https://doi.org/10.1109/NOCS.2009.5071441
    10. Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL’08, September 23-25, 2008, Stuttgart, Germany. Martin Radetzki (Ed.). 2009. DOI: https://doi.org/10.1007/978-1-4020-9714-0
    11. Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. Rauf Salimi Khaligh and Martin Radetzki. In Analysis, Architectures and Modelling of Embedded Systems, Third IFIPTC 10 International Embedded Systems Symposium, IESS 2009, Langenargen,Germany, September 14-16, 2009. Proceedings, 2009, pp. 149--158. DOI: https://doi.org/10.1007/978-3-642-04284-3_14
    12. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
    13. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
    14. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
    15. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
    16. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    17. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    18. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
    19. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 53--58. DOI: https://doi.org/10.1109/ETS.2009.26
    20. Test Exploration and Validation Using Transaction Level Models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    21. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
    22. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
    23. Restrict Encoding for Mixed-Mode BIST. Abdul-Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke and Andreas Glowatz. In Proceedings of the 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, California, USA, 2009, pp. 179--184. DOI: https://doi.org/10.1109/VTS.2009.43
    24. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
    25. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’09), Stuttgart, Germany, 2009, pp. 21--28.
  10. 2008

    1. Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information. Michael E. Imhof; Hans-Joachim Wunderlich; Christian Zöllin; Jens Leenstra and Nicolas Maeding. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 137--141.
    2. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian Zöllin. In 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR’08), Verbania, Italy, 2008.
    3. Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008.
    4. Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung. Melanie Elm and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 7--11.
    5. On the Reliability Modeling of Embedded Hardware-Software Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 1st IEEE Workshop on Design for Reliability and Variability (DRV’08), Santa Clara, California, USA, 2008.
    6. Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. Torsten Coym; Sybille Hellebrand; Stefan Ludwig; Bernd Straube; Hans-Joachim Wunderlich and Christian Zöllin. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 153--157.
    7. A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. Rauf Salimi Khaligh and Martin Radetzki. In Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings, 2008, pp. 37--42. DOI: https://doi.org/10.1109/FDL.2008.4641418
    8. Adaptive Interconnect Models for Transaction-Level Simulation. Rauf Salimi Khaligh and Martin Radetzki. In Languages for Embedded Systems and their Applications - Selected Contributionson Specification, Design, and Verification from FDL’08, September23-25, 2008, Stuttgart, Germany, 2008, pp. 149--165. DOI: https://doi.org/10.1007/978-1-4020-9714-0_10
    9. A data traffic efficient H.264 deblocking IP. Weining Hao and Martin Radetzki. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, 2008, pp. 3430--3433. DOI: https://doi.org/10.1109/ISCAS.2008.4542196
    10. Accuracy-Adaptive Simulation of Transaction Level Models. Martin Radetzki and Rauf Salimi Khaligh. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 788--791. DOI: https://doi.org/10.1109/DATE.2008.4484912
    11. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    12. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
    13. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
    14. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
    15. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
    16. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
    17. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
    18. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
    19. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
    20. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
    21. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    22. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung;  Detection of transient faults in circuits with reduced power dissipation. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 107--114.
    23. Scan Chain Clustering for Test Power Reduction. Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra and Nicolas Maeding. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08), Anaheim, California, USA, 2008, pp. 828--833. DOI: https://doi.org/10.1145/1391469.1391680
    24. Signature Rollback – A Technique for Testing Robust Circuits. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, 2008, pp. 125--130. DOI: https://doi.org/10.1109/VTS.2008.34
    25. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
    26. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS’08), Rhodes, Greece, 2008, pp. 59--64. DOI: https://doi.org/10.1109/IOLTS.2008.31
    27. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer. Michael A. Kochte and Ramesh Natarajan. In Proceedings of the 2008 conference on Computing frontiers (CF’08), Ischia, Italy, 2008, pp. 97--104. DOI: https://doi.org/10.1145/1366230.1366245
    28. Test Set Stripping Limiting the Maximum Number of Specified Bits. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), Hong Kong, China, 2008, pp. 581--586. DOI: https://doi.org/10.1109/DELTA.2008.64
    29. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS’08), Lago Maggiore, Italy, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    30. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen;  On the Reliability Modeling of Hardware-Software-Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 83--90.
  11. 2007

    1. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian Zöllin; Andreas Glowatz; Jürgen Schlöffel and Friedrich Hapke. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 61--65.
    2. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 82--86.
    3. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 56--60.
    4. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (2. Auflage), Christian Siemers and Axel Sikora (eds.). Fachbuchverlag Leipzig im Carl Hanser Verlag, 2007, pp. 267--290.
    5. Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. Rauf Salimi Khaligh and Martin Radetzki. In Embedded System Design: Topics, Techniques and Trends, IFIP TC10Working Conference: International Embedded Systems Symposium (IESS),May 30 - June 1, 2007, Irvine, CA, USA, 2007, pp. 313--324. DOI: https://doi.org/10.1007/978-0-387-72258-0_27
    6. Modelling Alternatives for Cycle Approximate Bus TLMs. Martin Radetzki and Rauf Salimi Khaligh. In Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, 2007, pp. 74--79.
    7. Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007, 2007, pp. 181--190.
    8. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    9. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
    10. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
    11. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
    12. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
    13. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
    14. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (2007), pp. 235--243.
    15. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), Krakow, Poland, 2007, pp. 185--190. DOI: https://doi.org/10.1109/DDECS.2007.4295278
    16. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute. Michael E. Imhof; Christian G. Zöllin; Hans-Joachim Wunderlich; Nicolas Mäding and Jens Leenstra. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 69--76.
    17. Academic Network for Microelectronic Test Education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean Pierre Van Der Heyden. The International Journal of Engineering Education 23, 6 (2007), pp. 1245--1253.
    18. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. Informacije MIDEM 37, 4(124) (2007), pp. 212--219.
    19. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, 2007, pp. 50--58. DOI: https://doi.org/10.1109/DFT.2007.43
    20. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
    21. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper). Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 3--10.
    22. Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen. Michael Wedel; Peter Göhner; Jochen Gäng; Bernd Bertsche; Talal Arnaout and Hans-Joachim Wunderlich. In 5. Paderborner Workshop “Entwurf mechatronischer Systeme,” Paderborn, Germany, 2007, pp. 257--272.
    23. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Juergen Schloeffel and Laurent Souef. In Proceedings of the International Test Conference (ITC’07), Santa Clara, California, USA, 2007, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2007.4437611
    24. Scan Test Planning for Power Reduction. Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC’07), San Diego, California, USA, 2007, pp. 521--526. DOI: https://doi.org/10.1145/1278480.1278614
    25. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    26. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 7--12. DOI: https://doi.org/10.1109/ETS.2007.9
    27. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. IET Computers & Digital Techniques 1, 3 (2007), pp. 180--186. DOI: https://doi.org/http://digital-library.theiet.org/content/journals/10.1049/iet-cdt_20060131
    28. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 91--96. DOI: https://doi.org/10.1109/ETS.2007.10
    29. Synthesis of Irregular Combinational Functions with Large Don’t Care Sets. Valentin Gherman; Hans-Joachim Wunderlich; Rio Mascarenhas; Juergen Schloeffel and Michael Garbers. In Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI’07), Stresa - Lago Maggiore, Italy, 2007, pp. 287--292. DOI: https://doi.org/10.1145/1228784.1228856
  12. 2006

    1. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zöllin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 101--103.
    2. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 95--100.
    3. SystemC TLM Transaction Modelling and Dispatch for Active Object. Martin Radetzki. In Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings, 2006, pp. 203--209.
    4. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
    5. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
    6. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626