Publikationen

Publikationen des Instituts

Publikationen

  1. 2024

    1. Time and Space Optimized Storage-based BIST under Multiple  Voltages and Variations. Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the Proceedings of the IEEE European Test Symposium (ETS´24), The Hague, Netherland, 2024.
    2. Scenario-based test content optimization: Scan-test vs.~system-level test. Nourhan Elhamawy; Ilia Polian; Jens Anders and Matthias Sauer. In To appear in Proceedings of 42nd IEEE VLSI Test Symposium (VTS), Tempe, AZ, USA, 2024.
    3. Vmin Testing under Variations: Defect vs. Fault Coverage. Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In To appear in the Proceedings of the IEEE Latin-American Test Symposium (LATS’24), Maceio, Brazil, 2024.
    4. Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks. Paul R. Genssler; Sandy A. Wasif; Miran Wael; Rodion Novkin and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’24), 2024.
    5. Machine Learning Unleashes Aging and Self-Heating Effects:  From Transistors to Full Processor. Hussam Amrouch; Victor van Santan; Javier Diaz Fortuny and Florian Klemme. In Proceedings of the IEEE 62nd International Reliability  Physics Symposium  (IRPS’24), Dallas, Texas, U.S., 2024.
    6. HDCircuit: Brain-inspired Hyperdimensional Computing for Circuit Recognition. Paul R. Genssler; Lilas Alrahis; Ozgur Sinanoglu and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’24), 2024.
    7. In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies. Hamza E. Barkam; Sanggeon Yun; Paul R. Genssler; Che-Kai Liu; Zhuowen Zou; Hussam Amrouch and Mohsen Imani. (2024). DOI: https://doi.org/10.1109/TCSI.2024.3351966
    8. Algorithm to Technology Co-Optimization for CiM-based Hyperdimensional Computing. Mahta Mayahinia; Simon Thomann; Paul R. Genssler; Christopher Münch; Hussam Amrouch and Mehdi B. Tahoori. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’24), 2024.
    9. Locking enabled security analysis of cryptographic circuits. Devanshi Upadhyaya; Maël Gay and Ilia Polian. Cryptography 8, 1 (2024).
    10. On the Severity of Self-Heating in FDSOI at Cryogenic  Temperatures: In-depth analysis from Transistors to Full Processor. Anirban Kar; Florian Klemme; Yogesh Chauhan. S and Hussam Amrouch. In Proceedings of the IEEE 62nd International Reliability  Physics Symposium  (IRPS’24), Dallas, Texas, U.S., 2024.
    11. WaSSaBi: Wafer Selection with Self-supervised Representations and Brain-inspired Active Learning. Karthik Pandaram; Paul R. Genssler and Hussam Amrouch. (2024). DOI: https://doi.org/10.1109/TCSI.2024.3357975
    12. DropHD: Technology/Algorithm Co-design for Reliable Energy-efficient NVM-based Hyperdimensional Computing under Voltage Scaling. Paul R. Genssler; Mahta Mayahinia; Simon Thomann; Mehdi Tahoori and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’24), 2024.
  2. 2023

    1. Exploring gate-diversity enabled by reconfigurable memristive technology. Sebastian Brandhofer; Ziang Chen; Li-Wei Chen; Nan Du and Ilia Polian. In To appear in Proceedings of IEEE Int’l Conf. on Electronics, Circuits and Systems (ICECS), Istanbul, Turkey, 2023.
    2. Approximation-Aware and Quantization-Aware Training for  Graph Neural Networks. Rodion Novkin; Florian Klemme and Hussam Amrouch. IEEE Transactions on Computers (November 2023).
    3. Side-channel Attacks on Memristive Circuits Under External Disturbances. Li-Wei Chen; Xianyue Zhao; Ziang Chen; Nan Du and Ilia Polian. In 2023 IEEE 32nd Asian Test Symposium (ATS), Beijing, China, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ATS59501.2023.10317969
    4. Optimizing the Streaming of Sensor Data with Approximate Communication. Somayeh Sadeghi-Kohan; Jan Dennis Reimer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the IEEE Asian Test Symposium (ATS’23), Beijing, China, 2023.
    5. Robust Pattern Generation for Small Delay Faults under  Process Variations. Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Zahra Paria Najafi-Haghi; Hussam Amrouch; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’23), Disneyland, Anaheim, USA, 2023.
    6. Optimal qubit reuse for near-term quantum computers. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. In To appear in Proceedings Quantum Computing and Engineering Conf.~(QCE), Seattle, Washington, USA, 2023.
    7. A modular open-source cryptographic co-processor for Internet of Things. Dina Hesse; Maël Gay; Ilia Polian and Elif Bilge Kavun. In To appear in Proceedings of Euromicro Conf. Digital System Design (DSD), Durres, Albania, 2023.
    8. Optimizing quantum algorithms on bipotent architectures. Yanjun Ji; Kathrin F. Koenig and Ilia Polian. Phys. Rev. A 108, 2 (August 2023), pp. 022610. DOI: https://doi.org/10.1103/PhysRevA.108.022610
    9. Exploiting the Error Resilience of the Preconditioned  Conjugate Gradient Method for Energy and Delay Optimization. Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra . Kourfali and Hans-Joachim Wunderlich. In IEEE 29st International On-Line Testing Symposium (IOLTS`23), Chania (Crete), Greece, 2023, pp. 1–6.
    10. Stochastic Computing as a Defence Against Adversarial Attacks. Florian Neugebauer; Vivek Vekariya; Ilia Polian and John P. Hayes. In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), Porto, Portugal, 2023, pp. 191–194. DOI: https://doi.org/10.1109/DSN-W58399.2023.00053
    11. Overview of Memristive Cryptography. Ilia Polian; Nan Du and Werner Schindler. In 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), Edinburgh, United Kingdom, 2023, pp. 1–5. DOI: https://doi.org/10.1109/NEWCAS57931.2023.10198201
    12. Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm. Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali and Hans-Joachim Wunderlich. In International Conference on Dependable Systems and Networks(DSN’23), Porto, Portugal, 2023.
    13. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. Somayeh Sadeghi-Kohan; Sybille Hellebrand and Hans-Joachim Wunderlich. In International Conference on Dependable Systems and Networks(DSN’23), Porto, Portugal, 2023.
    14. Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing. Lorenzo Masciullo; Roberto Passerone; Francesco Regazzoni and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–6. DOI: https://doi.org/10.1109/ETS56758.2023.10174181
    15. Automating Greybox System-Level Test Generation. Denis Schwachhofer; Maik Betka; Steffen Becker; Stefan Wagner; Matthias Sauer and Ilia Polian. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–4. DOI: https://doi.org/10.1109/ETS56758.2023.10173985
    16. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. Jens Anders; Pablo Andreu; Bernd Becker; Steffen Becker; Riccardo Cantoro; Nikolaos I. Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernandez; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; Abolfazl Sajadi; Mathias Sauer; Denis Schwachhofer; Matteo Sonza Reorda; Todor Stefanov; Ilya Tuzov; Stefan Wagner and Nuša Zidarič. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–10. DOI: https://doi.org/10.1109/ETS56758.2023.10174099
    17. LEDA: Locking enabled differential analysis of cryptographic circuits. Devanshi Upadhyaya; Mael Gay and Ilia Polian. In To appear in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, CA, USA, 2023.
    18. Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. Payam Habiby; Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich; Sebastian Huhn and Rolf Drechsler. In Proceedings of the 28th IEEE European Test Symposium 2023  (ETS’ 23), Venice, Italy, 2023, pp. 6.
    19. SAT-Based Quantum Circuit Adaptation. Sebastian Brandhofer; Jinwoong Kim; Siyuan Niu and Nicholas T. Bronn. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    20. Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level. Behnaz Ranjbar; Florian Klemme; Paul R. Genssler; Hussam Amrouch; Jinhyo Jung; Shail Dave; Hwisoo So; Kyongwoo Lee; Aviral Shrivastava; Ji-Yung Lin; Pieter Weckx; Subrat Mishra; Francky Catthoor; Dwaipayan Biswas and Akash Kumar. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    21. Review on Resistive Switching Devices Based on Multiferroic              BiFeO(3). Xianyue Zhao; Stephan Menzel; Ilia Polian; Heidemarie Schmidt and Nan Du. Nanomaterials (Basel) 13, 8 (April 2023). DOI: https://doi.org/10.3390/nano13081325
    22. Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. Zahra Paria Najafi-Haghi; Florian Klemme; Hanieh Jafarzadeh; Hussam Amrouch and Hans-Joachim Wunderlich. In Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    23. Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows. Florian Klemme; Sami Salamin and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    24. HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable Highly-Scaled FeFET. Hamza Errahmouni Barkam; Sanggeon Yun; Paul R. Genssler; Zhuowen Zou; Che-Kai Liu; Hussam Amrouch and Mohsen Imani. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’23), Antwerp, Belgium, 2023.
    25. Test Aspects of System Health State Monitoring. Hans-Joachim Wunderlich; Hanieh Jafarzadeh; Alexandra Kourfali; Natalia Lylina and Zahra Paria Najafi-Haghi. In IEEE 24nd Latin American Test Symposium (LATS`23), Veracruz, Mexico, 2023, pp. 1–2.
    26. Design Rationale for Symbiotically Secure Key Management Systems in IoT and Beyond. W. Bartsch; P. Gope; E. Kavun; O. Millwood; A. Mohammadi Pasikhani; A. Panchenko and I. Polian. In To appear In 9th International Conference on Information System Security and Privacy (ICISSP 2023), Lisbon, Portugal, 2023.
    27. ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors all the Way up Processors. Hussam Amrouch and Florian Klemme. In 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023.
    28. Beyond von Neumann Era: Brain-inspired Hyperdimensional Computing to the Rescue. Hussam Amrouch; Paul R. Genssler; Mohsen Imani; Mariam Issa; Xun Jiao; Wegdan Ali Mohammadin; Gloria Sepanta and Ruixuan Wang. In 28th Asia and South Pacific Design Automation Conference (ASP-DAC), 2023.
    29. A Complete Design-for-Test Scheme for Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (January 2023), pp. 1--19. DOI: https://doi.org/10.1007/s10836-022-06038-3
    30. Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs. Liu Liu; Shubham Kumar; Simon Thomann; Hussam Amrouch and X. Sharon Hu. In Proceedings of the 60th Annual Design Automation Conference (DAC’23), San Francisco, USA, 2023.
    31. Golden-Free Robust Age Estimation to Triage Recycled ICs. V. Surabhi; P. Krishnamurthy; H. Amrouch; J. Henkel; R. Karri and F. Khorrami. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’23) (2023).
    32. Modeling and Predicting Transistor Aging under Workload Dependency using Machine Learning. Paul R. Genssler; Hamza E. Barkam; Karthik Pandaram; Mohsen Imani and Hussam Amrouch. (2023). DOI: https://doi.org/10.1109/TCSI.2023.3289325
    33. FDSOI-based Analog Computing for Ultra-efficient Hamming Distance Similarity Calculation. Albi Mema; Simon Thomann; Paul R. Genssler and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2023). DOI: https://doi.org/10.1109/TCSI.2023.3267837
    34. Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. van Santen Victor; Jose M. Gata-Romero; Juan Nunez; Roca Eli and Hussam Amrouch. In Proceedings of the IEEE 61st International Reliability Physics Symposium  (IRPS’23), Monterey, California, U.S., 2023.
    35. Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor. Paul R. Genssler; Florian Klemme; Shivendra Singh Parihar; Sebastian Brandhofer; Girish Pahwa; Ilia Polian; Yogesh Singh Chauhan and Hussam Amrouch. IEEE Transactions on Quantum Engineering (2023). DOI: https://doi.org/10.1109/TQE.2023.3300833
    36. Design Automation for Cryogenic CMOS Circuits. Victor van Santen; Marcel Walter; Florian Klemme; Shivendra Parihar; Girish Pahwa; Yogesh Chauhan; Robert Wille and Hussam Amrouch. In Proceedings of the 60th Annual Design Automation Conference (DAC’23), San Francisco, USA, 2023.
    37. Reliable FeFET-based Neuromorphic Computing through Joint Modeling of Cycle-to-Cycle Variability, Device-to-Device Variability, and Domain Stochasticity. Simon Thomann; Albi Mema; Kai Ni and Hussam Amrouch. In Proceedings of the IEEE 61st International Reliability Physics Symposium  (IRPS’23), Monterey, California, U.S., 2023.
    38. Comprehensive Reliability Analysis of 22nm FDSOI SRAM from Device Physics to Deep Learning. Om Prakash; Rodion Novkin; Virinchi Surabhi Roy; Prashanth Krishnamur; Ramesh Karri; Farshad Khorrami and Hussam Amrouch. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’23), Monterey, California, USA, 2023.
    39. Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits. Victor van Santen; Florian Klemme; Paul R. Genssler and Hussam Amrouch. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023.
    40. Stress-resiliency of AI implementations on FPGAs. Jonas Krautter; Paul R. Genssler; Gloria Sepanta; Hussam Amrouch and Mehdi Tahoori. In International Conference on Field Programmable Logic and Applications (FPL), 2023.
    41. Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies. Hamza Errahmouni Barkam; Sanggeon Yun; Paul R. Genssler; Hanning Chen; Albi Mema; Andrew Ding; Hussam Amrouch and Mohsen Imani. In 2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2023.
    42. SyncTREE: Fast Timing Analysis for Integrated Circuit  Design through a Physics-informed Tree-based Graph Neural Network. Yuting Hu; Jiajie Li; Florian Klemme; Gi-Joon Nam; Tengfei Ma; Hussam Amrouch and Jinjun Xiong. In Thirty-seventh Conference on Neural Information Processing  Systems, 2023.
    43. Optimal Partitioning of Quantum Circuits Using Gate Cuts and Wire Cuts. Sebastian Brandhofer; Ilia Polian and Kevin Krsulich. IEEE Transactions on Quantum Engineering (2023), pp. 1–10. DOI: https://doi.org/10.1109/TQE.2023.3347106
    44. Identifying Resistive Open Defects in Embedded Cells under Variations. Zahra Paria Najafi-Haghi and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (2023), pp. 1–27. DOI: https://doi.org/10.1007/s10836-023-06044-z
    45. Compact CMOS-Compatible Majority Gate using Body Biasing in FDSOI Technology. Brunno Alves Abreu; Albi Mema; Simon Thomann; Guilherme Paim; Paulo Flores; Sergio Bampi and Hussam Amrouch. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) (2023).
    46. Machine Learning Support for Logic Diagnosis and Defect Classification. Hans-Joachim Wunderlich. In Machine Learning Support for Fault Diagnosis of System-on-Chip, Patrick Girard; Shawn Blanton and Li-C. Wang (eds.). Springer International Publishing, Cham, 2023, pp. 99--133. DOI: https://doi.org/10.1007/978-3-031-19639-3_4
    47. HW/SW Co-design for Approximation-Aware Binary Neural Networks. Abhilasha Dave; Fabio Frustaci; Fanny Spagnolo; Mikail Yayla; Jian-Jia Chen and Hussam Amrouch. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), under major revision (2023).
    48. On Side-Channel Analysis of Memristive Cryptographic Circuits. Li-Wei Chen; Ziang Chen; Werner Schindler; Xianyue Zhao; Heidemarie Schmidt; Nan Du and Ilia Polian. IEEE Transactions on Information Forensics and Security 18, (2023), pp. 463–476. DOI: https://doi.org/10.1109/TIFS.2022.3223232
    49. On the limitations of logic locking the approximate circuits. Karthik Nayak; Devanshi Upadhyaya; Francesco Regazzoni and Ilia Polian. In To appear in Proceedings of IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Singapore, SG, 2023.
    50. Workload-Aware Periodic Interconnect BIST. Somayeh Sadeghi-Kohan; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Design & Test (2023), pp. 1–1. DOI: https://doi.org/10.1109/MDAT.2023.3298849
    51. Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness. Om Prakahs; Kai Ni and Hussam Amrouch. In Proceedings of the IEEE 61st International Reliability Physics Symposium  (IRPS’23), Monterey, California, U.S., 2023.
    52. Tutorial: The Synergy of Hyperdimensional and In-memory Computing. Paul R. Genssler; Simon Thomann and Hussam Amrouch. In International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS ’23 Companion), 2023.
    53. HW/SW Co-design for Reliable In-Memory Brain-Inspired Hyperdimensional Computing. Simon Thomann; Paul R. Genssler and Hussam Amrouch. IEEE Transactions on Computers (TC) (2023).
  3. 2022

    1. Benchmarking the performance of portfolio optimization with QAOA. Daniel Brandhofer, Sebastianand Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. Quantum Information Processing 22, 1 (December 2022), pp. 25. DOI: https://doi.org/10.1007/s11128-022-03766-5
    2. Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications. Shan Deng; Mahdi Benkhelifa; Simon Thomann; Zubair Faris; Zijian Zhao; Tzu-Jung Huang; Yixin Xu; Vijaykrishnan Narayanan; Kai Ni and Hussam Amrouch. In 68th Annual IEEE International Electron Devices Meeting (IEDM’22), 2022.
    3. Physics inspired compact modelling of \$\$\backslashhbox \BiFeO\\_3\$\$based memristors. Sahitya Yarragolla; Nan Du; Torben Hemke; Xianyue Zhao; Ziang Chen; Ilia Polian and Thomas Mussenbrock. Scientific Reports 12, 1 (November 2022), pp. 20490. DOI: https://doi.org/10.1038/s41598-022-24439-4
    4. Online Periodic Test of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE Asian Test Symposium, Taichung, Taiwan, 2022, pp. 1--6. DOI: https://doi.org/10.1109/ATS56056.2022.00026
    5. AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks. Tim Buecher; Lilas Alrahis; Sergio Bampi; Guilherme Paim; Ozgur Sinanoglu and Hussam Amrouch. In IEEE/ACM 41st International Conference on Computer-Aided Design (ICCAD’22), 2022.
    6. Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. Juan Núñez; Simon Thomann; Hussam Amrouch and María J. Avedillo. In IEEE International Conference on Electronics, Circuits and Systems (ICECS’22), 2022.
    7. Cross-layer FeFET Reliability Modeling towards Robust Hyperdimensional Computing. Shubham Kumar; Swetaki Chatterjee; Simon Thomann; Paul R Gemssler; Yogesh S. Chauhan and Hussam Amrouch. In IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC’22), 2022.
    8. Brain-Inspired Hyperdimensional Computing for Ultra-Efficient Edge AI. Hussam Amrouch; Mohsen Imani; Xun Jiao; Yiannis Aloimonos; Cornelia Fermuller; Dehao Yuan; Dongning Ma; Hamza Errahmouni; Paul R. Genssler and Peter Sutor. In Proceedings of the 2022 International Conference on Hardware/Software Codesign and System Synthesis, 2022.
    9. Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning. Yiwen Liao; Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich and Bin Yang. In In Proceedings of the IEEE International Test Conference (ITC’22), Anaheim, CA, USA, 2022. DOI: https://doi.org/10.1109/ITC50671.2022.00026
    10. Joint Modeling of Multi-Domain Ferroelectric and Distributed Channel towards Unveiling the Asymmetric Abrupt DC Current Jump in Ferroelectric FET. Simon Thomann; Kai Ni and Hussam Amrouch. In 48th  IEEE European Solid-state Circuits and Devices Conference (ESSDERC’22), 2022.
    11. Advanced Thermal Management using Approximate Computing and On-Chip Thermoelectric Cooling. Hammam Kattan and Hussam Amrouch. In IEEE Symposium on Integrated Circuits and Systems Design (SBCCI’22), 2022.
    12. A Novel Approach to Mitigate Power Side Channel Attacks for Emerging Negative Capacitance Transistor Technology. Shubham Kumar; Swetaki Chatterjee; Chetan Dabhi; Hussam Amrouch and Yogesh S Chauhan. In 20th IEEE International NEWCAS Conference, 2022.
    13. On Extracting Reliability Information from Speed Binning. Zahra Paria Najafi-Haghi; Florian Klemme; Hussam Amrouch and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE European Test Symposium (ETS’22), Barcelona, Spain, 2022. DOI: https://doi.org/10.1109/ETS54262.2022.9810443
    14. Mitigating the Complexity of Chip Designs with ML-based Cell Library Characterization. Florian Klemme and Hussam Amrouch. In Workshop on Intelligent Methods for Test and Reliability (IMTR’22), 2022.
    15. Hinter den Kulissen. Martin Rettinger; Jajnabalkya Guhathakurta; Peter Gänz; Sven Simon and Mike Schlaich. Beton- und Stahlbetonbau 117, (April 2022). DOI: https://doi.org/10.1002/best.202200008
    16. Robust Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’22), Antwerp, Belgium, 2022, pp. 1--4. DOI: https://doi.org/10.23919/DATE54114.2022.9774770
    17. Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
    18. Machine Learning for Reliability-Aware, yet Confidential Standard Cell Characterization. Florian Klemme and Hussam Amrouch. In The 34th Workshop on Test Methods and Reliability of Circuits and Systems (TuZ’22), 2022.
    19. Stress-Aware Periodic Test of Interconnects. Sadeghi-Kohan Somayeh; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) (January 2022). DOI: https://doi.org/10.1007/s10836-021-05979-5
    20. Design Close to the Edge in Advanced Technology using Machine  Learning and Brain-Inspired Algorithms. Hussam Amrouch; Florian Klemme and Paul R. Genssler. In 27th Asia and South Pacific Design Automation Conference  (ASP-DAC’22), 2022.
    21. Trojan Detection in Embedded Systems with FinFET Technology. V. Surabhi; P. Krishnamurthy; H. Amrouch; J. Henkel; R. Karri and F. Khorrami. Transactions on Computers (TC’22) (2022).
    22. Trojan Detection in Embedded Systems with FinFET Technology. V. Surabhi; P. Krishnamurthy; H. Amrouch; R. Henkel, J. Karri and F. Khorrami. Transactions on Computers (TC’22) (2022).
    23. Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage. Navjeet Bagga; Kai Ni; Nitanshu Chauhan; Sharon Hu and Hussam Amrouch. In Proceedings of the IEEE 60th International Reliability Physics Symposium  (IRPS’22), Dallas, U.S., 2022.
    24. Suppressing Channel Percolation in Ferroelectric FET for Reliable Neuromorphic Applications. Kai Ni; Simon Thomann; Zijian Zhao; Shan Deng and Hussam Amrouch. In Proceedings of the IEEE 60th International Reliability Physics Symposium  (IRPS’22), Dallas, U.S., 2022.
    25. Calibration-Aware Transpilation for Variational Quantum Optimization. Yanjun Ji; Sebastian Brandhofer and Ilia Polian. In 2022 IEEE International Conference on Quantum Computing and Engineering (QCE), 2022, pp. 204–214. DOI: https://doi.org/10.1109/QCE53715.2022.00040
    26. Human vs. Automatic Detection of Deepfake Videos Over Noisy Channels. Swaroop Shankar Prasad; Ofer Hadar; Thang Vu and Ilia Polian. In 2022 IEEE International Conference on Multimedia and Expo (ICME), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ICME52920.2022.9859954
    27. A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. Nikhil Rangarajan; Nimisha Knechtel, Limaye; Johann; Ozgur Sinanoglu and Hussam Amrouch. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’22), ESWEEK Special Issue (2022).
    28. CARAT: A Framework for Analysis of BTI-HCD Aging in Digitial and AMS Circuits. Narendra Gangwar; Chaitanya Pasupuleti; M van Santen Victor; Uma Sharma; Hussam Amrouch and Souvik Mahapatra. Solid-State Electronics (SSE’22) (2022).
    29. Scatter Correction for High-Resolution Flat-Panel CT Based on a Fast Monte Carlo Photon Transport Model. A. Alsaffar; S. Kieß; K. Sun and S. Simon. 2022.
    30. Benchmarking the performance of portfolio optimization with QAOA. Sebastian Brandhofer; Daniel Braun; Vanessa Dehn; Gerhard Hellstern; Matthias Hüls; Yanjun Ji; Ilia Polian; Amandeep Singh Bhatia and Thomas Wellens. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2207.10555
    31. Reliable Binarized Neural Networks on Unreliable Beyond von-Neumann Architecture. Mikail Yayla; Sebastian Buschjäger; Katharina Morik; Jian-Jia Chen and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers  (TCAS-I) (2022).
    32. Leveraging Ferroelectric Stochasticity and In-Memory Computing for DNN IP Obfuscation. Likhitha Mankali; Nikhil Rangarajan; Swetaki Chatterjee; Shubham Kumar; Yogesh S. Chauhan; Ozgur Sinanoglu and Hussam Amrouch. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC) (2022).
    33. Asymmetric Double Gate Ferroelectric FET to Break the Tradeoff Between Thickness Scaling and Memory Window. Zhouhang Jiang; Yi Xiao; Swetaki Chatterjee; Halid Mulaosmanovic; Stefan Duenkel; Steven Soss; Sven Beyer; Rajiv Joshi; Yogesh S. Chauhan; Hussam Amrouch; Vijaykrishnan Narayanan and Kai Ni. In Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI’22), Hawaii, U.S., 2022.
    34. SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2022), pp. 1--14. DOI: https://doi.org/10.1109/TCAD.2022.3158250
    35. Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing? Paul Genssler; Austin Vas and Hussam Amrouch. IEEE Embedded Systems Letters (ESL’22) (2022).
    36. Targeting DNN Inference via Efficient Utilization of Heterogeneous Precision DNN Accelerators. Ourania Spantidi; Georgios Zervakis; Sami Salamin; Isai Roman Ballesteros; Joerg Henkel; Hussam Amrouch and Iraklis Anagnostopoulos. IEEE Transactions on Emerging Topics in Computing (TETC) (2022).
    37. Wafer Map Defect Identification Based on the Fusion of Pattern and Pixel Information. Yiwen Liao; Raphael Latty; Paul R. Genssler; Hussam Amrouch and Bin Yang. In IEEE International Test Conference (ITC’22), 2022.
    38. Ferroelectric FDSOI FET Modeling for Memory and Logic Applications. Swetaki Chatterjee; Shubham Kumar; Chetankumar Dabhi; Yogesh S. Chauhan and Hussam Amrouch. Solid-State Electronics (SSE’22) (2022).
    39. Thermal-Aware DNN Accelerator Design. Georgios Zervakis; Iraklis Anagnostopoulos; Sami Salamin; Ourania Spantidi; Isai Roman Ballesteros; Joerg Henkel and Hussam Amrouch. Transactions on Computers (TC’22) (2022).
    40. Brain-Inspired Computing for Circuit Reliability Characterization. Paul R. Genssler and Hussam Amrouch. Transactions on Computers (TC) (2022). DOI: https://doi.org/10.1109/TC.2022.3151857
    41. Novel FDSOI-Based Dynamic XNOR Logic for Ultra-Efficient High-Dense Computing. Shubham Kumar; Swetaki Chatterjee; Chetankumar Dabhi; Hussam Amrouch and Yogesh S. Chauhan. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’22), Austin Texas, USA, 2022.
    42. Efficient Learning Strategies for Machine Learning-based Cell Library Characterization. Florian Klemme and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
    43. Printed Temperature Sensor Array for High-Resolution Thermal Mapping. Tim Buecher; Robert Huber; Carsten Eschenbaum; Adrian Mertens; Uli Lemmer and Hussam Amrouch. Nature Scientific Reports (2022).
    44. Multi-Material Blind Beam Hardening Correction Based on Non-Linearity Adjustment of Projections. Ammar Alsaffar; Kaicong Sun and Sven Simon. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2203.04587
    45. FL-MISR: fast large-scale multi-image super-resolution for computed tomography based on multi-GPU acceleration. Kaicong Sun; Trung-Hieu Tran; Jajnabalkya Guhathakurta and Sven Simon. Journal of Real-Time Image Processing 19, 2 (2022), pp. 331--344. DOI: https://doi.org/10.1007/s00138-014-0623-4
    46. An FPGA-Based Residual Recurrent Neural Network for Real-Time Video Super-Resolution. Kaicong Sun; Maurice Koch; Zhe Wang; Slavisa Jovanovic; Hassan Rabah and Sven Simon. IEEE Transactions on Circuits and Systems for Video Technology 32, 4 (2022), pp. 1739–1750. DOI: https://doi.org/10.1109/TCSVT.2021.3080241
    47. 3DVSR: 3D EPI volume-based approach for angular and spatial light field image super-resolution. Trung-Hieu Tran; Jan Berberich and Sven Simon. Signal Processing 192, (2022), pp. 108373. DOI: https://doi.org/10.1016/j.sigpro.2021.108373
    48. Beneath the Surface - Computed Tomography for Precast Segmental Bridges. M. Rettinger; J. Guhathakurta; P. Ganz; S. Simon and M. Schlaich. Beton- und Stahlbetonbau 117, 2 (2022).
    49. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (4. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2022, pp. 266–289. DOI: https://doi.org/10.3139/9783446470453.009
    50. Comprehensive Variability Analysis in Dual-Port FeFET for Reliable Multi-Level-Cell Storage. Swetaki Chatterjee; Simon Thomann; Chetan; Yogesh S Chauhan and Hussam Amrouch. IEEE Transactions on Electron Devices (TED’22) (2022).
    51. Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. Hussam Amrouch; Krishnendu Chakrabarty; Dirk Pflüger; Ilia Polian; Matthias Sauer and Matteo Sonza Reorda. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810416
    52. Stochastic Computing Architectures for Lightweight LSTM Neural Networks. Roshwin Sengupta; Ilia Polian and John P. Hayes. In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2022, pp. 124–129. DOI: https://doi.org/10.1109/DDECS54261.2022.9770167
    53. On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks. Florian Neugebauer; Stefan Holst and Ilia Polian. In 2022 IEEE European Test Symposium (ETS), 2022, pp. 1–6. DOI: https://doi.org/10.1109/ETS54262.2022.9810429
    54. Security in an Approximated World: New Threats and Opportunities in the Approximate Computing Paradigm. Paolo Palmieri; Ilia Polian and Francesco Regazzoni. In Approximate Computing Techniques: From Component- to Application-Level, Alberto Bosio; Daniel Ménard and Olivier Sentieys (eds.). Springer International Publishing, Cham, 2022, pp. 323--348. DOI: https://doi.org/10.1007/978-3-030-94705-7_11
    55. Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries. Florian Klemme and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022). DOI: https://doi.org/10.1109/TCSI.2022.3201431
    56. Scalable Machine Learning to Estimate the Impact of Aging on Circuits under Workload Dependency. Florian Klemme and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
    57. Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing. Kai Ni and Hussam Amrouch. In Proceedings of the IEEE 60th International Reliability Physics Symposium  (IRPS’22), Dallas, U.S., 2022.
    58. Design-Time Exploration of Voltage Switching Against Power Analysis Attacks in 14nm FinFET Technology. J. Knechtel; Tarek Asha; Natasha Fernengel; S. Patnaik; M. Nabeel; M. Ashraf; O. Sinanoglu and H. Amrouch. Integration VLSI Journal (IVLSI) (2022).
    59. GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. Lilas Alrahis; Johann Knechtel; Florian Klemme; Hussam Amrouch and Ozgur Sinanoglu. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’22), ESWEEK Special Issue (2022).
    60. Characterizing Approximate Arithmetic Adders and Multipliers for Mitigating Aging and Temperature Degradations. Francisco J. H. Santiago; Honglan Jiang; Hussam Amrouch; Andreas Gerstlauer; Leibo Liu and Jie Han. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
    61. Machine Learning-Based Microarchitecture-Level Power Modeling of CPUs. Ajay Krishna; Sami Salamin; Hussam Amrouch and Andreas Gerstlauer. IEEE Transactions on Computers (TC) (2022).
    62. All-in-Memory Brain-Inspired Computing using FeFET Synapses. Simon Thomann; Nguyen Hong Lam Giang; Paul R. Genssler and Hussam Amrouch. Frontiers in Electronics (2022). DOI: https://doi.org/10.3389/felec.2022.833260
    63. Modeling TPU Thermal Maps under Superlattice Thermoelectric Cooling. Tim Buecher and Hussam Amrouch. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2022).
    64. Variability-Aware Approximate Circuit Synthesis via Genetic Optimization. Konstantinos Balaskas; Florian Klemme; Georgios Zervakis; Kostas Siozios; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
    65. Computational Scatter Correction for High-Resolution Flat-Panel CT Based on a Fast Monte Carlo Photon Transport Model. Ammar Alsaffar; Steffen Kieß; Kaicong Sun and Sven Simon. 2022.2022. DOI: https://doi.org/10.48550/ARXIV.2201.13191
    66. Second Harmonic Generation Exploiting Ultra-Stable Resistive Switching Devices for Secure Hardware Systems. Ziang Chen; Nan Du; Mahdi Kiani; Xianyue Zhao; Ilona Skorupa; Stefan E. Schulz; Danilo Bürger; Massimiliano Di Ventra; Ilia Polian and Heidemarie Schmidt. IEEE Transactions on Nanotechnology 21, (2022), pp. 71–80. DOI: https://doi.org/10.1109/TNANO.2021.3135713
  4. 2021

    1. On the Channel Percolation in Ferroelectric FET Towards Proper Analog States Engineering. Kai Ni; Simon Thomann; Om Prakash; Zijian Zhao; Shan Deng and Hussam Amrouch. In 67th Annual IEEE International Electron Devices Meeting (IEDM’21), 2021.
    2. Positive/Negative Approximate Multipliers for DNN Accelerators. Ourania Spantidi; Georgios Zervakis; Hussam Amrouch; Jörg Henkel and Iraklis Anagnostopoulos. In IEEE/ACM 39th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    3. Binarized SNNs: Efficient and Error-Resilient Spiking Neural  Networks through Binarization. Ming-Liang Wei; Mikail Yayla; SY Ho; Chia-Lin Yang; Jian-Jia Chen and Hussam Amrouch. In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    4. Resistive Open Defect Classification of Embedded Cells under Variations. Zahra Paria Najafi-Haghi and Hans-Joachim Wunderlich. In Proceedings of the IEEE Latin-American Test Symposium (LATS’21), Virtual, 2021, pp. 1--6. DOI: https://doi.org/10.1109/LATS53581.2021.9651857
    5. Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’21), Virtual, 2021, pp. 1--10. DOI: https://doi.org/10.1109/ITC50571.2021.00009
    6. Brain-Inspired Computing for Wafer Map Defect Pattern Classification. Paul R. Genssler and Hussam Amrouch. In IEEE International Test Conference (ITC’21), 2021.
    7. Machine Learning for Circuit Aging Estimation under Workload Dependency. Florian Klemme and Hussam Amrouch. In IEEE International Test Conference (ITC’21), 2021.
    8. Variability Effects in FinFET and Negative Captitance FinFET technologies. Aniket Gupta; Nitanshu Chauhan; Om Prakash and Hussam Amrouch. In 19th IEEE International Conference on IC Design and Technology (ICICDT’21), 2021.
    9. On the Resiliency of NC-FinFET SRAMs against Variation: MFIS Structure. Anekit Gupta; Nitanshu Chauhan; Om Prakash and Hussam Amrouch. In International Conference on Simulation of Semiconductor Processes and Devices (SISPAD’21), 2021.
    10. Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. Chih-Hao Wang; Natalia Lylina; Ahmed Atteya; Tong-Yu Hsieh and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’21), Virtual, 2021, pp. 1--7. DOI: https://doi.org/10.1109/IOLTS52814.2021.9486710
    11. Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security. Domenic Forte; Debdeep Mukhopadhyay; Ilia Polian; Yunsi Fei and Rosario Cammarota. J. Emerg. Technol. Comput. Syst. 17, 3 (June 2021). DOI: https://doi.org/10.1145/3464326
    12. ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), Virtual, 2021, pp. 1--6.
    13. Security, Reliability and Test Aspects of the RISC-V Ecosystem. Jaume Abella; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernandez; Mike Hutter; Leonidas Kosmidis; Ilia Polian; Matthias Sauer; Stefan Wagner and Francesco Regazzoni. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), 2021.
    14. Noisy Intermediate-Scale Quantum (NISQ) Computers: How They Work, How They Fail, How to Test Them? Sebastian Brandhofer; Simon Devitt; Thomas Wellens and Ilia Polian. In Proceedings of the 39th IEEE VLSI Test Symposium (VTS’21), Virtual, 2021, pp. 1--6.
    15. A Hybrid Protection Scheme for Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya and Hans-Joachim Wunderlich. In Proceedings of the IEEE VLSI Test Symposium (VTS’21), Virtual, 2021, pp. 1--7. DOI: https://doi.org/10.1109/VTS50974.2021.9441029
    16. Impact of Transistor Self-Heating  on Logic Gates. Victor M. van Santen; Linda Schillinger and Hussam Amrouch. In IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’21), Virtual, 2021.
    17. On the Critical Role of Ferroelectric Thickness for Negative Capacitance Transistor Optimization. Om Prakash; Aniket Gupta; Girish Pahwa; Yogesh Chauhan and Hussam Amrouch. In IEEE Electron Devices Technology & Manufacturing Conference    (EDTM’21), 2021.
    18. Soft Errors in Negative Capacitance FDSOI SRAMs. Govind Bajpai; Aniket Gupta; Om Prakash; Yogesh Chauhan and Hussam Amrouch. In IEEE Electron Devices Technology & Manufacturing Conference    (EDTM’21), 2021.
    19. Towards Utilizing Self-awareness During System-level Test. Denis Schwachhofer; Steffen Becker; Matthias Sauer; Stefan Wagner and Ilia Polian. In 33. GI / GMM / ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ’21)), 2021.
    20. Reliability-Aware Quantization for Anti-Aging NPUs. Sami Salamin; Georgios Zervakis; Ourania Spantidi; Iraklis Anagnostopoulos; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
    21. Machine Learning for Semiconductor Test and Reliability. Hussam Amrouch; Animesh Basak Chowdhury; Wentian Jin; Ramesh Karri; Khorrami Farshad; Prashanth Krishnamurthy; Ilia Polian; Victor M. van Santen; Benjamin Tan and Sheldon Tan. In IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
    22. Nano Security: From Nano-Electronics to Secure Systems. Ilia Polian; Frank Altmann; Tolga Arul; Christian Boit; Ralf Brederlow; Lucas Davi; Rolf Drechsler; Nan Du; Thomas Eisenbarth; Tim Güneysu; Sascha Hermann; Matthias Hiller; Rainer Leupers; Farhad Merchant; Thomas Mussenbrock; Stefan Katzenbeisser; Akash Kumar; Wolfgang Kunz; Thomas Mikolajick; Vivek Pachauri; Jean-Pierre Seifert; Frank Sill Torres and Jens Trommer. In Proceedings of the Conference on Design, Automation &  Test in Europe (DATE’21), Virtual Event, 2021.
    23. Approximate Computing for ML: State-of-the-art, Challenges and  Visions. Georgios Zervakis; Hassaan Saadat; Hussam Amrouch; Andreas Gerstlauer; Sri Parameswaran and Joerg Henkel. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    24. Cross-layer Design for Computing-in-Memory: From Devices,  Circuits, to Architectures and Applications. Hussam Amrouch; Xiaobo Sharon Hu; Mohsen Imani; Ann Franchesca Laguna; Michael Niemier; Simon Thomann; Xunzhao Yin and Cheng Zhuo. In 26th Asia and South Pacific Design Automation Conference  (ASP-DAC’21), 2021.
    25. Traps Based Reliability Barrier on Performance and Revealing  Early Ageing in Negative Capacitance (NC) FET. Nitanshu Chauhan; Aniket Gupta; Govind Bajapi; Priynshi Singhal; Navjeet Bagga; Om Prakash; Shashank Banchhor and Hussam Amrouch. In Proceedings of the IEEE 59th International Reliability Physics Symposium  (IRPS’21), Dallas, Texas, U.S., Virtual, 2021.
    26. Control Variate Approximation for DNN Accelerators. Georgios Zervakis; Ourania Spantidi; Iraklis Anagnostopoulos; Hussam Amrouch and Joerg Henkel. In Proceedings of the 58th Annual Design Automation Conference (DAC’21), San Francisco, USA, 2021.
    27. On-demand Mobile CPU Cooling with Thin-Film Thermoelectric  Array. Hammam Kattan; Sung Woo Chung; Joerg Henkel and Hussam Amrouch. IEEE Micro Magazine (MICRO’21) (2021).
    28. Automated Design Approximation to Suppress Circuit Aging. Konstantinos Balaskas; Georgios Zervakis; Hussam Amrouch; Jörg Henkel and Kostas Siozios. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2021).
    29. GVLD: A Fast and Accurate GPU-Based Variational Light-Field Disparity Estimation Approach. Trung-Hieu Tran; Gasim Mammadov and Sven Simon. IEEE Transactions on Circuits and Systems for Video Technology 31, 7 (2021), pp. 2562–2574. DOI: https://doi.org/10.1109/TCSVT.2020.3028258
    30. A lightweight and robust VCSEL-based 3D-depth sensing approach for mobile application. Trung-Hieu Tran; Sven Simon; Bo Chen; Detlef Russ and Daniel Claus. In Digital Optical Technologies 2021, 2021, pp. 70-- 77. DOI: https://doi.org/10.1117/12.2591653
    31. Robust Brain-Inspired Computing: On the Reliability of  Spiking Neural Network Using Emerging Non-Volatile Synapses. Ming-Ling Wei; Hussam Amrouch; Cheng-Lin Sung; Chia-Lin Yang; Khe-Chung Wang and Chin-Yuan Lu. In Proceedings of the IEEE 59th International Reliability Physics Symposium  (IRPS’21), Dallas, Texas, U.S., Virtual, 2021.
    32. System-Level Test: State of the Art and Challenges. D. Appello; H. H. Chen; M. Sauer; I. Polian; P. Bernardi and M. Sonza Reorda. In 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, pp. 1–7. DOI: https://doi.org/10.1109/IOLTS52814.2021.9486708
    33. Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications. Ilia Polian; John P. Hayes; Vincent T. Lee and Weikang Qian. IEEE Design & Test 38, 6 (2021), pp. 5–15. DOI: https://doi.org/10.1109/MDAT.2021.3080989
    34. On the Reliability of In-Memory Computing: Impact of  Temperature on Ferroelectric TCAM. Simon Thomann; Chao Li; Cheng Zhuo; Om Prakash; Xunzhao Yin; X. Sharon Hu and Hussam Amrouch. In Proceedings of IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
    35. Investigation of the Influence of Transport Processes on Chemical Reactions in Bubbly Flows Using Space-Resolved In Situ Analytics and Simultaneous Characterization of Bubble Dynamics in Real-Time, Reactive Bubbly Flows. J. Guhathakurta; D. Schurr; G. Rinke; D. Grottke; Kraut M.; R. Dittmeyer and S. Simon. Springer (2021), pp. 163–196.
    36. 3DVSR: 3D EPI Volume-based Approach for Angular and Spatial Light filed Image Super-resolution. T. H. Tran; J. Berberich and S. Simon. Signal processing (2021), pp. 108373.
    37. Impact of Self-Heating on Negative-Capacitance FinFET:  Device-Circuit Interaction. Om Prakash; Girish Pahwa; Chetan Dabhi; Yogesh S Chauhan and Hussam Amrouch. IEEE Transactions on Electron Devices (TED’21) (2021).
    38. Toward Security Closure in the Face of Physical Migration Effects. Jens Lienig; Susann Rothe; Matthias Thiele; Mohammed Ashraf; Mohammed Nabeel; Nikhil Rangarajan; Hussam Amrouch; Ozgur Sinanoglu; Ramesh Karri and Johann Knechtel. In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    39. Energy Efficient Edge Computing Enabled by Satisfaction Games and Approximate Computing. Nafis Irtija; Iraklis Anagnostopoulos; Georgios Zervakis; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Green Communications and Networking (TGCN) (2021).
    40. Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures. Hussam Amrouch; Jian-Jia Chen; Kaushik Roy; Yuan Xie; Indranil Chakraborty; Wenqin Huangfu; Ling Liang; Fengbin Tu; Cheng Wang and Mikail Yayla. In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    41. Towards reliable in-memory computing: From emerging devices to post-von-Neumann architectures. Hussam Amrouch; Nan Du; Anteneh Gebregiorgis; Said Hamdioui and Ilia Polian. In Proc. IFIP / IEEE Int’l Conf. on Very Large Scale Integration (VLSI-SoC). (Accepted), online, 2021.
    42. Machine Learning for On-the-fly Reliability-Aware Cell Library Characterization. Florian Klemme and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2021).
    43. Bridging the Gap Between Voltage Over-Scaling and Joint  Hardware Accelerator-Algorithm Closed-Loop. Guilherme Paim; Hussam Amrouch; Eduardo A. C. da Costa; Sergio Bampi and Jörg Henkel. IEEE Transactions on Circuits and Systems for Video Technology  (TCSVT’21) (2021).
    44. Detection of malicious spatial-domain steganography over noisy channels. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. In Multidisciplinary Approach to Modern Digital Steganography, Sabyasachi Pramanik; Mangesh Manikrao Ghonge; Renjith V. Ravi and Korhan Cengiz (eds.). IGI Global, 2021.
    45. MLCAD: A Survey of Research in Machine Learning for CAD. Martin Rapp; Hussam Amrouch; Yibo Lin; Bei Yu; David Pan; M. Wolf and J. Henkel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2021).
    46. FeFET and NCFET for Future DNNs: Visions and Opportunities. Yayla Mikail; Kuan-Hsun Chen; Christian Hakert; Georgios Zervakis; Jian-Jia Chen; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’21), Virtual Event, 2021.
    47. Extending circuit design flow for early assessment of fault attack vulnerabilities. Felipe Valencia; Ilia Polian and Francesco Regazzoni. In Proc. Euromicro Conf. on Digital System Design. (Accepted), online, 2021.
    48. Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning. Francesco Regazzoni; Paolo Palmieri; Fethulah Smailbegovic; Rosario Cammarota and Ilia Polian. CAAI Transactions on Intelligence Technology 6, 2 (2021), pp. 180–191. DOI: https://doi.org/10.1049/cit2.12029
    49. PROTON: Post-synthesis ferROelectric Thickness OptimizatioN for NCFET Circuits. Sami Salamin; Georgios Zervakis; Joerg Henkel and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2021).
    50. On the Reliability of FeFET On-Chip Memory. Paul R. Genssler; Victor M. van Santen; Joerg Henkel and Hussam Amrouch. IEEE Transactions on Computers (TC’21) (2021).
    51. FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors. Mikail Yayla; Sebastian Buschjäger; Aniket Gupta; Jian-Jia Chen; Joerg Henkel; Katharina Morik; Kuan-Hsun Chen and Hussam Amrouch. IEEE Transactions on Computers (TC) (2021).
    52. On resilience of security-oriented error detecting architectures against power attacks: A theoretical analysis. Osnat Keren and I. Polian. In Proc. Computing Frontiers Conference / MalIoT Workshop., online, 2021.
    53. Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU. Sami Salamin; Georgios Zervakis; Florian Klemme; Hammam Kattan; Yogesh Chauhan; Jörg Henkel and Hussam Amrouch. IEEE Transactions on Computers (TC’21) (2021).
    54. Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. In Dependable Embedded Systems, Jörg Henkel and Nikil Dutt (eds.). Springer International Publishing, Cham, 2021, pp. 277--302. DOI: https://doi.org/10.1007/978-3-030-52017-5_12
    55. Bilateral Spectrum Weighted Total Variation for Noisy-Image Super-Resolution and Image Denoising. Kaicong Sun and Sven Simon. IEEE Transactions on Signal Processing 69, (2021), pp. 6329–6341. DOI: https://doi.org/10.1109/TSP.2021.3127679
    56. Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms. Sebastian Brandhofer; Ilia Polian and Hans Peter Büchler. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1–7. DOI: https://doi.org/10.1109/ICCAD51958.2021.9643490
    57. On the Resiliency of NCFET Circuits against Voltage  Over-Scaling. Guilherme Paim; Georgios Zervakis; Eduardo A. C. da Costa; Sergio Bampi; Jörg Henkel and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’21) (2021).
    58. Comprehensive Design-Space Exploration for NCFET-based SRAM  Arrays. Victor M van Santen; Simon Thomann; Yogesh S. Chauhan; Joerg Henkel and Hussam Amrouch. In Proceedings of IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
    59. Containing Self-Heating Effects in Advanced Technologies. S. Salamin; V. van Santen; M. Rapp; J. Henkel and H. Amrouch. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access’21) (2021).
    60. Real-Time Full-Chip Thermal Tracking: A Post-Silicon, Machine Learning Perspective. Sheriff Sadiqbatcha; Jinwei Zhao; Hussam Amrouch and Sheldon Tan. IEEE Transactions on Computers (TC) (2021).
    61. Adv-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. Divya Praneetha; Rajesh Kedia; Victor van Santen; Preeti Panda and Hussam Amrouch. IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (2021).
    62. Longevity of Commodity DRAMs in Harsh Environments through Thermoelectric Cooling. Deepak M. Mathew; Hammam Kattan; Christian Weis; Jörg Henkel; Norbert Wehn and Hussam Amrouch. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2021).
    63. Bilateral Spectrum Weighted Total Variation for Real-World Super Resolution and Image Denoising. K. Sun and S. Simon. (2021), pp. 1–13.
    64. Making Historical Gyroscopes Alive -- 2D and 3D Preservations by Sensor Fusion and Open Data Access. J. Wagner Fritsch; B. Ceranski; S. Simon; M. Niklaus; K. Zhan and G. Mammadov. Sensors 21, 3 (2021), pp. 957.
    65. Ferroelectric FET Technologies and Its Applications: From Device to System. Hussam Amrouch; Di Gao; Xiaobo Sharon Hu; Arman Kazemi; Ann Franchesca Laguna; Kai Ni; Michael Niemier; Simon Thomann; Xunzhao and Cheng Zhuo. In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    66. Impact of NCFET on Neural Network Accelerators. Georgios Zervakis; Iraklis Anagnostopoulos; Yogesh Chauhan; Jörg Henkel and Hussam Amrouch. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access’21) (2021).
    67. Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors. Ji Heon Lee; Jeong Hwan Choi; Young Seo Lee; Hussam Amrouch; Joonho Kong; Young-Ho Gong and Sung Woo Chung. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2021).
    68. Software Based Read and Write Wear-Leveling for Non-Volatile Main Memory. Christian Hakert; Kuan-Hsun Chen; Horst Schirmeier; Lars Bauer; Paul Genßler; Georg von der Brüggen; Hussam Amrouch; Jörg Henkel and Jian-Jia Chen. ACM Transactions on Embedded Computing Systems (TECS) (2021).
    69. Full-Chip  Power Density and Thermal Map Characterization for Commercial Microprocessors under Heat Sink Cooling. Jinwei Zhang; Sadiqbatcha Sheriff; Michael O’Dea; Hussam Amrouch and Sheldon Tan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2021).
    70. Security Closure of Physical Layouts. Johann Knechtel; Jayanth Gopinath; Jitendra Bhandari; Mohammed Ashraf; Hussam Amrouch; Shekhar Borkar; Sung-Kyu Lim; Ozgur Sinanoglu and Ramesh Karri. In IEEE/ACM 40th International Conference on Computer-Aided Design (ICCAD’21), 2021.
    71. Electrothermal Simulation and Optimization of Thermoelectric Cooler using an Analytical Approach. Liang Chen; Hussam Amrouch and Sheldon Tan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2021).
    72. Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology. Om Prakash; Nitanshu Chauhan; Anekit Gupta and Hussam Amrouch. Elsevier Microelectronics Journal (Microelectronics’21) (2021).
    73. FDRN: A fast deformable registration network for medical images. Kaicong Sun and Sven Simon. Medical Physics 48, 10 (2021), pp. 6453–6463. DOI: https://doi.org/10.1002/mp.15011
    74. Making Historical Gyroscopes Alive—2D and 3D Preservations by Sensor Fusion and Open Data Access. Dieter Fritsch; Jörg F. Wagner; Beate Ceranski; Sven Simon; Maria Niklaus; Kun Zhan and Gasim Mammadov. Sensors 21, 3 (2021). DOI: https://doi.org/10.3390/s21030957
    75. Investigation of the Influence of Transport Processes on Chemical Reactions in Bubbly Flows Using Space-Resolved In Situ Analytics and Simultaneous Characterization of Bubble Dynamics in Real-Time. Jajnabalkya Guhathakurta; Daniela Schurr; Günter Rinke; Daniel Grottke; Manfred Kraut; Roland Dittmeyer and Sven Simon. In Reactive Bubbly Flows: Final Report of the DFG Priority Program 1740, Michael Schlüter; Dieter Bothe; Sonja Herres-Pawlis and Ulrich Nieken (eds.). Springer International Publishing, Cham, 2021, pp. 163--196. DOI: https://doi.org/10.1007/978-3-030-72361-3_9
    76. Error Analysis of the Variational Quantum Eigensolver Algorithm. Sebastian Brandhofer; Simon Devitt and Ilia Polian. In 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021, pp. 1–6. DOI: https://doi.org/10.1109/NANOARCH53687.2021.9642249
    77. Low-power emerging memristive designs towards secure hardware systems for applications in internet of things. Nan Du; Heidemarie Schmidt and Ilia Polian. Nano Materials Science 3, 2 (2021), pp. 186–204.
    78. Transistor Self-Heating: The Rising Challenge for  Semiconductor Testing. Om Prakash; Chetan Dabhim; Yogesh Chauhan and Hussam Amrouch. In Proceedings of IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.

Frühere Publikationen

  1. 2020

    1. Logic Fault Diagnosis of Hidden Delay Defects. Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’20), Washington DC, USA, 2020. DOI: https://doi.org/10.1109/ITC44778.2020.9325234
    2. Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’20), Washington DC, USA, 2020. DOI: https://doi.org/10.1109/ITC44778.2020.9325227
    3. Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. Florian Klemme; Yogesh Chauhan; Joerg Henkel and Hussam Amrouch. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’20), 2020.
    4. Machine learning and hardware security: challenges and opportunities. Francesco Regazzoni; Shivam Bhasin; Amir Ali Pour; Ihab Alshaer; Furkan Aydin; Aydin Aysu; Vincent Beroulle; Giorgio Di Natal; Paul Franzon; David Hely; Naofumi Homma; Akira Ito; Dirmanto Jap; Priyank Kashyap; Ilia Polian; Seetal Potluri; Rei Ueno; Elena Ioana Vatajelu and Ville Yli-Mayry. In Proceedings of the 39th IEEE International Conference On Computer Aided Design 2020 (ICCAD’20), 2020.
    5. Modeling Emerging Technologies using Machine Learning:  Challenges and Opportunities. Florian Klemme; Jannik Prinz; Victor M. van Santen; Joerg Henkel and Hussam Amrouch. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’20), 2020.
    6. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
    7. Hardware-based fast real-time image classification with stochastic computing. Ponana Kelettira Muthappa; Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 38th IEEE International Conference on Computer Design (ICCD’20), 2020.
    8. Side Channel Attacks vs Approximated Computing. Francesco Regazzoni and Ilia Polian. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI 2020 (GLSVLSI ’20), 2020, pp. 321–326. DOI: https://doi.org/10.1145/3386263.3407592
    9. FDRN: Fast Deformable Image Registration Based on Unsupervised Convolutional Neural Networks. Kaicong Sun; Zhaowen Gong and Sven Simon. In Proceedings of the 6th International Conference on Image Formation in X-Ray Computed Tomography, Regensburg, Germany, 2020, pp. 202--205.
    10. Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. Junseok Oh; Florian Neugebauer; Ilia Polian and John Hayes. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 246–251. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00052
    11. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
    12. IPM-RED: combining higher-order masking with robust error detection. Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00229-4
    13. Error control scheme for malicious and natural faults in cryptographic modules. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Journal of Cryptographic Engineering 10, (June 2020). DOI: https://doi.org/10.1007/s13389-020-00234-7
    14. Variation-Aware Defect Characterization at Cell Level. Zahra Najafi Haghi; Marzieh Hashemipour Nazari and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE European Test Symposium (ETS’20), Tallinn, Estonia, 2020, pp. 1--6. DOI: https://doi.org/10.1109/ETS48528.2020.9131600
    15. Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the  IEEE VLSI TestSymposium (VTS’20), San Diego, US, 2020, pp. 1--6.
    16. BTI and HCI Degradation in a Complete 32X64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity. Victor van Santen; Simon Thomann; C. Pasupuleti; P. Genssler; N. Gangwar; U. Sharma; J. Henkel; S. Mahapatra and H. Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    17. GPU-accelerated Time Simulation of  Systems with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116256
    18. Using Programmable Delay Monitors for  Wear-Out and Early Life Failure Prediction. Chang Liu; Eric Schneider and Hans-Joachim. Wunderlich. In Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116284
    19. Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6. DOI: https://doi.org/10.23919/DATE48585.2020.9116525
    20. Impact of NBTI Aging on Self-Heating in Nanowire FET. Om Prakash; S. Manhas; Jörg Henkel and Hussam Amrouch. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’20), Grenoble, France, 2020.
    21. Energy Optimization in NCFET-based Processors. Sami Salamin; Martin Rapp; Hussam Amrouch; Andreas Gerstlauer and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’20), Grenoble, France, 2020.
    22. Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont and Ilia Polian. In 2020 Design, Automation  Test in Europe Conference  Exhibition (DATE), 2020, pp. 508–513. DOI: https://doi.org/10.23919/DATE48585.2020.9116483
    23. Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET. Om Prakash; Aniket Gupta; Girish Pahwa; Jörg Henkel; Yogesh Chauhan and Hussam Amrouch. In IEEE Electron Devices Technology & Manufacturing Conference (EDTM’20), 2020.
    24. Scattering Correction of CBCT Projections for the Quality Enhanced CT Reconstruction Using an Efficient Monte Carlo Photon Transport Model. Ammar Alsaffar; Gasim Mammadov and Sven Simon. In Proceedings of the 10th Conference on Industrial Computed Tomography (iCT 2020), Wels, Austria, 2020, pp. 1--6.
    25. Machine Learning Based Online Full-Chip Heatmap Estimation. Sheriff Sadiqbatcha; Yue Zhao; Jinwei Zhang; Hussam Amrouch; Jörg Henkel and Sheldon Tan. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20), 2020.
    26. NCFET to Rescue Technology Scaling: Opportunities and Challenges. Hussam Amrouch; Victor M. van Santen; Girish Pahwa; Yogesh Chauhan and Jörg Henkel. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20), 2020.
    27. Impact of Self-Heating On Performance, Power and Reliability in FinFET Technology. Victor M. van Santen; Paul R. Genssler; Om Prakash; S. Thomann; Jörg Henkel and Hussam Amrouch. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20, 2020.
    28. Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks. Swaroop Shankar Prasad; Ofer Hadar and Ilia Polian. Electronic Imaging 2020, 4 (January 2020), pp. 76-1-76–7. DOI: https://doi.org/10.2352/ISSN.2470-1173.2020.4.MWSF-076
    29. Machine Learning for CAD. Marilyn Wolf; Jörg Henkel and Hussam Amrouch (Eds.). . Springer International Publishing, 2020.
    30. Towards a New Thermal Monitoring Based Framework for Embedded CPS Device Security. N. Patel; P. Krishnamurthy; H. Amrouch; J. Henkel; M. Shamouilian; R. Karri and Khorrami. R. IEEE Transactions on Dependable and Secure Computing  (TDSC’20) (2020).
    31. Power-Efficient Heterogeneous Many-Core Design with NCFET Technology. S. Salamin; M. Rapp; A. Pathania; A. Maity; J. Henkel; T. Mitra and H. Amrouch. IEEE Transactions on Computers (TC’20) (2020).
    32. Multi-frame Super-resolution Reconstruction based on Mixed Poisson-Gaussian Noise. K. Sun; T.-H. Tran; R. Krawtschenko and S. Simon. Signal Processing: Image Communication, Elsevier 82, (2020), pp. 1–10.
    33. Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology. H. Amrouch; G. Pahwa; A. Gaidhane; F. Klemme; O. Prakash; C. Dabhi and Y. Chauhan. IEEE Transactions on Circuits and Systems I: Regular Paper  (TCAS-I’20), 2020 (2020).
    34. Information leakage from robust codes protecting cryptographic primitives. Osnat Keren and Ilia Polian. In Frontiers in Hardware Security and Trust: Theory, design and practice, C.H. Chang and Y Cao (eds.). The Institution of Engineering and Technology, 2020.
    35. Scattering Correction of CBCT Projections for the Quality Enhanced CT Reconstruction Using Efficient Monte Carlo Photon Transport Model. A. Alsaffar; G. Mammadov and S. Simon. In 10th Conference on Industrial Computed Tomography, 2020, pp. 1–6.
    36. Hardware Trojan Detection Using Controlled Circuit Aging. V. Surabhi; P. Krishnamurthy; H. Amrouch; K. Basu; R. Henkel, J. Karri and F. Khorrami. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2020).
    37. Massively Parallel Circuit Setup in GPU-SPICE. V. van Santen; F. Florian Diep; J. Henkel and H. Amrouch. IEEE Transactions on Computers (TC’20) (2020).
    38. Impact of Interface Traps on Negative Capacitance Transistor:  Device and Circuit Reliability. Om Prakash; Anekit Gupta; Girish Pahwa; Joerg Henkel; Yogesh S. Chauhan and Hussam Amrouch. IEEE Journal of the Electron Devices Society (JEDS’20) (2020).
    39. A Framework for Crossing Temperature-Induced Timing Errors  Underlying Hardware Accelerators to the Algorithm and Application Layers. G. Paim; H. Amrouch; L. Rocha; B. Abreu; E. da Costa; S. Bampi and J. Henkel. IEEE Transactions on Computers (TC’20) (2020).
    40. Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET. Aniket Gupta; Kai Ni; Om Prakash; X. Sharon Hu and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    41. Weight-Oriented Approximation for Energy-Efficient Neural  Network Inference Accelerators. Zois-Gerasimos Tasoulas; Georgios Zervakis; Iraklis Anagnostopoulos; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers  (TCAS-I) (2020).
    42. Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging. V. Surabhi; P. Krishnamurthy; H. Amrouch; R. Henkel, J. Karri and F. Khorrami. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    43. Dynamic Power and Energy Management for NCFET-based Processors. Sami Salamin; Martin Rapp; Andreas Gerstlauer; Joerg Henkel and Hussam Amrouch. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    44. Data compression by means of adaptive subsampling. Z. Wang; Y. Baroud; S. Najmabadi and S. Simon. US Patent 10,867,412 (2020).
    45. Analysis of Digital Logic Circuit Degradation. Subrat Misra; Thirunavukkarasu Vignesh; Jerin Joe; Hussam Amrouch; Jörg Henkel and Souvik Mahapatra. In Recent Advances in Negative Bias Temperature Instability, Souvik Mahapatra (ed.). Springer International Publishing, 2020.
    46. Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). J. Knechtel; S. Patnaik; M. Nabeel; M. Ashraf; Y. Chauhan; J. Henkel; O. Sinanoglu and H. Amrouch. IEEE Micro Magazine (MICRO’20) (2020).
    47. Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy. G. Zervakis; H. Amrouch and J. Henkel. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access) (2020).
    48. NPU Thermal Management. Hussam Amrouch; Georgios Zervakis; Kattan; Hammam; Iraklis Anagnostopoulos and Joerg Henkel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20), ESWEEK Special Issue (2020).
    49. Impact of Extrinsic Variation Sources on the Device-to-Device Variation in Ferroelectric FET. Kai Ni; Aniket Gupta; Om Prakash; Simon Thomann; X. Sharon Hu and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
    50. Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems. Hussam Amrouch; Martin Rapp; Sami Salamin and Jörg Henkel. In A Journey of Embedded and Cyber-Physical Systems. Springer, Cham, 2020, pp. 107.
    51. Aging Compensation with Dynamic Computation Approximation. H. Kim; J. Kim; H. Amrouch; Jörg Henkel; A. Gerstlauer; K. Choi and P. Hanmin. IEEE Transactions on Circuits and Systems I: Regular Paper  (TCAS-I’20) (2020).
    52. Post-Silicon Hot-Spot Identification and Machine-LearningBased Thermal Modeling Using Infrared Thermal Imaging. S. M Sheriff; Z. Jinwei; Z. Hengyang; Amrouch; H.; Jörg Henkel and S. Tan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’20) (2020).
    53. Impact of Radiation on Negative Capacitance FinFET. Govind Bajpai; Aniket Gupta; Om Prakash; Girish Pahwa; Jörg Henkel; Yogesh Chauhan and Hussam Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.
  2. 2019

    1. Architecture for parallel marker-free variable length streams decoding. Yousef Baroud; José Manuel Mariños Velarde; Zhe Wang; Steffen Kieß; Seyyed Mahdi Najmabadi; Jajnabalkya Guhathakurta and Sven Simon. Journal of Real-Time Image Processing 16, 6 (December 2019), pp. 2127–2146. DOI: https://doi.org/10.1007/s11554-017-0715-2
    2. Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000143
    3. Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019. DOI: https://doi.org/10.1109/ITC44170.2019.9000114
    4. Combined MPSoC Task Mapping and Memory Optimization for Low-Power. Manuel Strobel; Gereon Führ; Martin Radetzki and Rainer Leupers. In Proc. IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), Bangkok, Thailand, 2019.
    5. On the Limits of Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In 2019 IEEE International Conference on Rebooting Computing, ICRC, 2019, pp. 98--105. DOI: https://doi.org/10.1109/ICRC.2019.8914706
    6. The Impact of Emerging Technologies on Architectures and System-level Management. Jörg Henkel; Hussam Amrouch; Martin Rapp; Sami Salamin; Dayane Reis; Di Gao; Xunzhao Yin; Michael Niemier; Cheng Zhuo; Hu X. Sharon; Hsiang-Yun Cheng and Chia-Lin Yang. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’19), 2019.
    7. Design-Time Memory Subsystem Optimization for Low- Power Multi-Core Embedded Systems. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded(MCSoC), Singapore, 2019. DOI: https://doi.org/10.1109/MCSoC.2019.00056
    8. A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs. Jie Hou; Q. Han and Martin Radetzki. In Proceedings of the 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, 2019.
    9. Comparative Study and Proof of Single-Pass Connected Components Algorithms. Michael J. Klaiber; Donald G. Bailey and Sven Simon. J. Math. Imaging Vis. 61, 8 (October 2019), pp. 1112–1134. DOI: https://doi.org/10.1007/s10851-019-00891-2
    10. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems (TCAD) 38, 10 (October 2019), pp. 1956–1968. DOI: https://doi.org/10.1109/TCAD.2018.2864255
    11. A Backend Tool for the Integration of Memory Optimizations into Embedded Software. Manuel Strobel and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages (FDL), Southampton, UK, 2019. DOI: https://doi.org/10.1109/FDL.2019.8876895
    12. A Methodology to Compute Long-Term Fault Resilience of NoCs under Fault-Tolerant Routing Algorithms. Jie Hou and Martin Radetzki. In Proceedings of the 2019 Forum on Specification and Design Languages(FDL), Southampton, UK, 2019.
    13. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Mael Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019, pp. 25–32. DOI: https://doi.org/10.1109/FDTC.2019.00012
    14. NCFET-Aware Voltage Scaling. Sami Salamin; Martin Rapp; Hussam Amrouch; Girish Pahwa; Yogesh S. Chauhan and Jörg Henkel. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’19), 2019.
    15. Automated Sensor Firmware Development - Generation, Optimization, and Analysis. Jens Rudolf; Manuel Strobel; Joscha Benz; Cristian Haubelt; Martin Radetzki and Oliver Bringmann. In MBMV 2019; 22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019, pp. 1–12.
    16. On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’19), Florence, Italy, 2019, pp. 1016--1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
    17. Spatial Resolution Enhancement Based on Detector Displacement for Computed Tomography. Kaicong Sun; Steffen Kieß and Sven Simon. In Proceedings of the 9th Conference on Industrial Computed Tomography (iCT 2019), Padova, Italy, 2019, pp. 1--8.
    18. Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (January 2019), pp. 78--91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
    19. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (January 2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
    20. Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. Martin Rapp; Sami Salamin; Hussam Amrouch; Girish Pahwa; Yogesh S. Chauhan and Jörg Henkel. In Proceedings of the 56th Annual Design Automation Conference (DAC’19), Las Vegas, USA, 2019.
    21. Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal Imaging. Sheriff Sadiqbatcha; Hengyang Zhao; Hussam Amrouch; Jörg Henkel and Sheldon Tan. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’19), Florence, Italy, 2019.
    22. Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395--416. DOI: https://doi.org/10.1049/PBPC022E_ch16
    23. Hybrid telecentric triangulation sensor system with real-time field-dependent deconvolution. A. Faulhaber; M. Gronle; T. Haist; C. Pruß; Y. Baroud; W. Osten and S. Simon. Optical Measurement Systems for Industrial Inspection XI 1105, (2019), pp. 1105613.
    24. Hybrid telecentric triangulation sensor system with real-time field-dependent deconvolution. Andreas Faulhaber; Marc Gronle; Tobias Haist; Christof Pruß; Yousef Baroud; Wolfgang Osten and Sven Simon. In Optical Measurement Systems for Industrial Inspection XI, 2019, pp. 264-- 277. DOI: https://doi.org/10.1117/12.2525568
    25. A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding. Zhe Wang; Trung-Hieu Tran; Ponnanna Kelettira Muthappa and Sven Simon. Journal of Imaging 5, 5 (2019). DOI: https://doi.org/10.3390/jimaging5050050
    26. An Architecture for Asymmetric Numeral Systems Entropy Decoder-A Comparison with a Canonical Huffman Decoder. S. M. Najmabadi; T. H. Tran; S. Eissa; S. Tungal and S. Simon. Journal of Signal Processing Systems 91, 7 (2019), pp. 805–817.
    27. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    28. Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation. Frank Sill Torres; Hussam Amrouch; Jörg Henkel and Rolf Drechsler. In Proceedings of the IEEE 56th International Reliability Physics Symposium  (IRPS’19), Las Vegas, USA, 2019.
    29. Rebirth-FTL: Lifetime optimization via Approximate Storage for NAND Flash. Lei Han; Hussam Amrouch; Zili Shao and Jörg Henkel. In IEEE Non-Volatile Memory Systems and Applications Symposium  (NVMSA’19), Hangzhou, China, 2019.
    30. Aging Gracefully with Approximation. Jongho Kim; Heesu Kim; Hussam Amrouch; Jörg Henkel; Andreas Gerstlauer and Kiyoung Choi. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’19), Las Vegas, USA, 2019.
    31. Unveiling the Impact of IR-drop on Performance Gain in NCFET-based Processors. Hussam Amrouch; Sami Salamin; Girish Pahwa; Amol D Gaidhane; Jörg Henkel and Yogesh S Chauhan. IEEE Transactions on Electron Devices (T-ED’19) (2019).
    32. Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits. A Thirunavukkarasu; Hussam Amrouch; Jerin Joe; Nilesh Goel; Narendra Parihar; Subrat Mishra; Chetan K Dabhi; Yogesh S Chauhan; Jörg Henkel and Souvik Mahapatra. IEEE Transactions on Electron Devices (T-ED’19) 66, 1 (2019), pp. 316--323.
    33. On the Workload Dependence of Self-Heating in FinFET Circuits. Victor M van Santen; Hussam Amrouch; Pooja Sharma and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’19) (2019).
    34. On the Efficiency of Voltage Overscaling under Temperature and Aging Effects. Hussam Amrouch; Borna Ehsani; Andreas Gerstlauer and Jörg Henkel. IEEE Transactions on Computers (TC’19) (2019).
    35. New Worst-Case Timing for Standard Cells Under Aging Effects. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Device and Materials Reliability (T-DMR’19) 19, 1 (2019), pp. 149--158.
    36. Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’19) (2019).
    37. Reliability Challenges with Self-Heating in FinFET Technology. H. Amrouch; V. M. van Santen; O. Prakash; H. Kattan; S. Salamin; S. Thomann and J. Henkel. In IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS’19), 2019.
    38. Aging Effects: From Physics to CAD. Hussam Amrouch; Heba Khdr and Jörg Henkel. In Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approach, William Fornaciari and Dimitrios Soudris (eds.). Springer International Publishing, 2019, pp. 43--69. DOI: https://doi.org/10.1007/978-3-319-91962-1_3
    39. A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives. Osnat Keren and Ilia Polian. In Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019, pp. 49--63. DOI: https://doi.org/10.29007/r2sc
    40. Power-Mode-Aware Memory Subsystem Optimization for Low-Power System-on-Chip Design. Manuel Strobel and Martin Radetzki. ACM Transactions on Embedded Computing Systems(TECS) (2019). DOI: https://doi.org/10.1145/3356583
    41. Constructive Side-Channel Analysis and Secure Design - 10th International Workshop, COSADE 2019, Darmstadt, Germany, April 3-5, 2019, Proceedings. Ilia Polian and Marc Stöttinger (Eds.). Springer.2019. DOI: https://doi.org/10.1007/978-3-030-16350-1
    42. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    43. Multi-Branch Deep Residual Neural Networks for Enhancing the Spatial Resolution of 2D Computed Tomography Images. K. Sun; Y. Liu and S. Simon. 15th International Meeting on Fully Three-Dimensional Image Reconstruction (2019), pp. 2.
    44. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
    45. Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. Sami Salamin; Victor M van Santen; Hussam Amrouch; Narendra Parihar; Souvik Mahapatra and Jörg Henkel. IEEE Transactions on Very Large Scale Integration Systems (TVLSI’19) (2019).
    46. Estimating and Mitigating Aging Effects in Routing Network of FPGAs. Behnam Khaleghi; Behzad Omidi; Hussam Amrouch; Jörg Henkel and Hossein Asadi. IEEE Transactions on Very Large Scale Integration Systems (TVLSI’19) 27, 3 (2019), pp. 651--664.
    47. Selecting the Optimal Energy Point in Near-Threshold Computing. Sami Salamin; Hussam Amrouch and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’19), Florence, Italy, 2019.
    48. Sub-Pixel Registration Technique for X-ray Phase Contrast Imaging. Hamish Bradley; Donald Bailey; Steven Le Moan; Peter Gaenz and Sven Simon. In 2019 International Conference on Image and Vision Computing New Zealand (IVCNZ), 2019, pp. 1–5. DOI: https://doi.org/10.1109/IVCNZ48456.2019.8960959
    49. A Cross-layer Gate-Level-to-Application Co-simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders. Guilherme Paim; Leandro M. G. Rocha; Hussam Amrouch; A. C. da Costa Eduardo; Sergio Bampi and Jörg Henkel. IEEE Transactions on Circuits and Systems for Video Technology  (TCSVT’19) (2019).
    50. Dynamic guardband selection: Thermal-aware optimization for unreliable multi-core systems. Heba Khdr; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Computers (TC’19) 68, 1 (2019), pp. 53--66.
    51. A simulation study of NBTI impact on 14-nm node FinFET technology for logic applications: Device degradation to circuit-level interaction. Subrat Mishra; Hussam Amrouch; Jerin Joe; Chetan K Dabhi; Karansingh Thakor; Yogesh S Chauhan; Jörg Henkel and Souvik Mahapatra. IEEE Transactions on Electron Devices (T-ED’19) 66, 1 (2019), pp. 271--278.
    52. Improving Testability and Reliability of Advanced SRAM Architectures. Josef Kinseher; Moritz Völker and Ilia Polian. IEEE Trans. Emerging Topics Comput. 7, 3 (2019), pp. 456–467.
    53. An Architecture for Asymmetric Numeral Systems Entropy Decoder - A                Comparison with a Canonical Huffman Decoder. Seyyed Mahdi Najmabadi; Trung-Hieu Tran; Sherif Eissa; Harsimran Singh Tungal and Sven Simon. J. Signal Process. Syst. 91, 7 (2019), pp. 805--817. DOI: https://doi.org/10.1007/s11265-018-1421-4
    54. Spatial Resolution Enhancement Based on Detector Displacement for Computed Tomography. K. Sun; S. Kieß and S. Simon. In 9th Conference on Industrial Computed Tomography, 2019, pp. 1–8.
  3. 2018

    1. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
    2. Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures  in Low-Power Scan Testing. Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 149--154. DOI: https://doi.org/10.1109/ATS.2018.00037
    3. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (October 2018), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    4. Device aging: A reliability and security concern. Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit Singh; Hans-Joachim Wunderlich and Naghmeh Karimi. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2018.8400702
    5. Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2018.8400685
    6. Detecting and Resolving Security Violations in Reconfigurable Scan Networks. Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the 24th IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’18), Platja d’Aro, Spain, 2018, pp. 91--96. DOI: https://doi.org/10.1109/IOLTS.2018.8474188
    7. Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, 3 (June 2018), pp. 5--6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
    8. Design-Time Optimization Techniques for Low-Power Embedded Memory Subsystems. Manuel Strobel and Martin Radetzki. In Proc. of the 1st International Workshop on Embedded Software for Industrial IOT (ESIIT), Dresden, Germany, 2018.
    9. Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, 1 (March 2018), pp. 1--1. DOI: https://doi.org/10.1109/LES.2018.2789942
    10. Efficient Data Structures for the Fast 3D Reconstruction of Voxel Volumes with Inhomogeneous Spatial Resolution. Benjamin Betz; Steffen Kieß; Michael Krumm; Gunnar Knuppe; Tsegaye Eshete and Sven Simon. In 8th Conference on Industrial Computed Tomography (iCT), Wels, Austria, 2018.
    11. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
    12. Recent Advances in EM and BTI Induced Reliability Modeling, Analysis and Optimization. Sheldon X.-D. Tan; Hussam Amrouch; Taeyoung Kim; Zeyu Sun; Chase Cook and Jrg Henkel. Integration VLSI Journal (IVLSI’18) 60, C (January 2018), pp. 132--152.
    13. Voltage Adaptation Under Temperature Variation. H. Amrouch; B. Khaleghi and J. Henkel. In 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD’18), 2018, pp. 57–60.
    14. Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE. V. M. van Santen; H. Amrouch and J. Henkel. In IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS’18), 2018, pp. 143–146.
    15. Aging-constrained Performance Optimization for Multi Cores. Heba Khdr; Hussam Amrouch and Jürg Henkel. In Proceedings of the 55th Annual Design Automation Conference (DAC’18), San Francisco, California, 2018, pp. 63:1--63:6.
    16. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    17. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    18. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    19. Aging-Aware Boosting. H. Khdr; H. Amrouch and J. Henkel. IEEE Transactions on Computers (TC’18) 67, 9 (2018), pp. 1217–1230.
    20. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    21. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    22. Gyrolog — Towards VR Preservations of Gyro Instruments for Historical and Didactical Research. Dieter Fritsch; Joerg F. Wagner; Sven Simon; Beate Ceranski; Maria Niklaus; Kun Zhan; Timo Schweizer and Zhe Wang. In 2018 Pacific Neighborhood Consortium Annual Conference and Joint Meetings (PNC), 2018, pp. 1–7. DOI: https://doi.org/10.23919/PNC.2018.8579456
    23. Effiziente CT-Rekonstruktion eines Voxel-Volumens mit inhomogener räumlicher Auflösung mithilfe eines Octrees. B. Betz; S. Kie; M. Krumm; G. Knupe; T. Eshete and S. Simon. DGZfP-JAHRESTAGUNG (2018), pp. 1–5.
    24. GPU-Accelerated Light-Field Image Super-Resolution. Trung-Hieu Tran; Gasim Mammadov; Kaicong Sun and Sven Simon. In 2018 International Conference on Advanced Computing and Applications (ACOMP), 2018, pp. 7–13. DOI: https://doi.org/10.1109/ACOMP.2018.00010
    25. Efficient Data Structures for the Fast 3D Reconstruction of Voxel Volumes with Inhomogeneous Spatial Resolution. B. Betz; S. Kieß; M. Krumm; G. Knupe; T. Eshete and S. Simon. In 8th Conference on Industrial Computed Tomography, 2018, pp. 1–6.
    26. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
    27. Modeling and Evaluating the Gate Length Dependence of BTI. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’18) (2018).
    28. Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV. V. M. van Santen; J. Martin-Martinez; H. Amrouch; M. M. Nafria and J. Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’18) 65, 1 (2018), pp. 293–306.
    29. Dynamic Resource Management for Heterogeneous Many-cores. Jörg Henkel; Jürgen Teich; Stefan Wildermann and Hussam Amrouch. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18), San Diego, California, 2018, pp. 60:1--60:6.
    30. Performability Analysis of Mesh-Based NoCs Using Markov Reward Model. Jie Hou and Martin Radetzki. In 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2018, Cambridge, United Kingdom, March 21-23, 2018, 2018, pp. 609--616. DOI: https://doi.org/10.1109/PDP2018.2018.00102
    31. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    32. Dynamic holography for speckle noise reduction in hybrid measurement system. Andreas Faulhaber; Stefan Haberl; Tobias Haist; Marc Gronle; Yousef Baroud; Wolfgang Osten and Sven Simon. In Laser Beam Shaping XVIII, 2018, pp. 94-- 105. DOI: https://doi.org/10.1117/12.2320486
    33. A spatial moments sub-pixel edge detector with edge blur compensation for imaging metrology. D. Gester and S. Simon. In 2018 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2018, pp. 1–6. DOI: https://doi.org/10.1109/I2MTC.2018.8409664
    34. Dynamic holography for speckle noise reduction in hybrid measurement system. A. Faulhaber; T. Haist; W. Osten and S. Simon. In Laser Beam Shaping XVIII, 2018, pp. 1–12.
    35. Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance. Hussam Amrouch; Girish Pahwa; Amol D Gaidhane; Jörg Henkel and Yogesh Singh Chauhan. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access’18) 6, (2018), pp. 52754--52765.
    36. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    37. Estimating and Optimizing BTI Aging Effects: From Physics to CAD. Hussam Amrouch; Victor M. van Santen and Jörg Henkel. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18), San Diego, California, 2018, pp. 125:1--125:6.
    38. Trading Off Temperature Guardbands via Adaptive Approximations. B. Boroujerdian; H. Amrouch; J. Henkel and A. Gerstlauer. In 2018 IEEE 36th International Conference on Computer Design (ICCD’18), 2018, pp. 202–209.
    39. Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. V. M. van Santen; J. Diaz-Fortuny; H. Amrouch; J. Martin-Martinez; R. Rodriguez; R. Castro-Lopez; E. Roca; F. V. Fernandez; J. Henkel and M. Nafria. In IEEE International Reliability Physics Symposium (IRPS’18), 2018, pp. P-CR.6-1-P-CR.6-6.
  4. 2017

    1. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
    2. Hardware and software innovations in energy-efficient system-reliability monitoring. V. Tenentes; C. Leech; G. M. Bragg; G. Merrett; B. M. Al-Hashimi; H. Amrouch; J. Henkel and S. Das. In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’17), 2017, pp. 1–5.
    3. Trustworthy Reconfigurable Access to On-Chip Infrastructure. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 1st International Test Conference in Asia (ITC-Asia’17), Taipei, Taiwan, 2017, pp. 119--124. DOI: https://doi.org/10.1109/ITC-ASIA.2017.8097125
    4. Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’17), Thessaloniki, Greece, 2017, pp. 237--239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
    5. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, 6 (June 2017), pp. 957--970. DOI: https://doi.org/10.1109/TC.2016.2616405
    6. Towards aging-induced approximations. H. Amrouch; B. Khaleghi; A. Gerstlauer and J. Henkel. In 54th ACM/EDAC/IEEE Design Automation Conference (DAC’17), 2017, pp. 1–6.
    7. Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
    8. Probabilistic Sensitization Analysis for Variation-Aware Path Delay Fault Test Evaluation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968226
    9. Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968247
    10. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (May 2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    11. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (May 2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    12. Special Session on Early Life Failures. Jyotirmoy Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017. DOI: https://doi.org/10.1109/VTS.2017.7928933
    13. Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1--6. DOI: https://doi.org/10.1109/VTS.2017.7928921
    14. Impact of BTI on dynamic and static power: From the physical to circuit level. H. Amrouch; S. Mishra; V. van Santen; S. Mahapatra and J. Henkel. In 017 IEEE International Reliability Physics Symposium (IRPS’17), 2017, pp. CR-3.1-CR-3.6.
    15. Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). J. Henkel; S. Pagani; H. Amrouch; L. Bauer and F. Samie. In Design, Automation Test in Europe Conference Exhibition (DATE’17), 2017, pp. 954–959.
    16. Containing guardbands. H. Amrouch and J. Henkel. In 22nd Asia and South Pacific Design Automation Conference (ASP-DAC’17), 2017, pp. 537–542.
    17. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’17), Fort Worth, Texas, USA, 2017, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2017.8242055
    18. Special session: emerging (Un-)reliability based security threats and mitigations for embedded systems. H. Amrouch; P. Krishnamurthy; N. Patel; J. Henkel; R. Karri and F. Khorrami. In International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES’17), 2017, pp. 1–10.
    19. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    20. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    21. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    22. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    23. Simultaneous In Situ Characterisation of Bubble Dynamics and a Spatially Resolved Concentration Profile: A Combined Mach--Zehnder Holography and Confocal Raman-Spectroscopy Sensor System. J. Guhathakurta; D. Schurr; G. Rinke; R. Dittmeyer and S. Simon. Journal of Sensors and Sensor Systems 6, 1 (2017), pp. 223–236.
    24. Contactless characterization of electric structures with simulation models based on CT data. C. Jauch; J. Denecke; J. Kuehnle; I. Effenberger; S. Kiess and S. Simon. In 7th Conference on Industrial Computed Tomography, 2017, pp. 1–7.
    25. Variational disparity estimation framework for plenoptic images. Trung-Hieu Tran; Zhe Wang and Sven Simon. In 2017 IEEE International Conference on Multimedia and Expo (ICME), 2017, pp. 1189–1194. DOI: https://doi.org/10.1109/ICME.2017.8019377
    26. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    27. Hybrid instruction set simulation for fast and accurate memory access profiling. Manuel Strobel and Martin Radetzki. In 13th Workshop on Intelligent Solutions in Embedded Systems, WISES 2017, Hamburg, Germany, June 12-13, 2017, 2017, pp. 23--28. DOI: https://doi.org/10.1109/WISES.2017.7986927
    28. Low power memory allocation and mapping for area-constrained systems-on-chips. Manuel Strobel; Marcus Eggenberger and Martin Radetzki. EURASIP J. Emb. Sys. 2017, (2017), pp. 2. DOI: https://doi.org/10.1186/s13639-016-0039-5
    29. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    30. Semi-symbolic operational computation for robust control system design. Leandro Gil and Martin Radetzki. In 22nd International Conference on Methods and Models in Automation and Robotics, MMAR 2017, Miedzyzdroje, Poland, August 28-31, 2017, 2017, pp. 779--784. DOI: https://doi.org/10.1109/MMAR.2017.8046927
    31. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    32. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    33. Characterization of a Raman Spectroscopic and Holographic System for Gas-Liquid Flows in Microchannels. D. Schurr; J. Guhathakurta; S. Simon; G. Rinke and R. Dittmeyer. Chemical Engineering & Technology 40, 8 (2017), pp. 1400–1407.
    34. Architecture for parallel marker-free variable length streams decoding. Y. Baroud; J. M. M. Velarde; Z. Wang; S. Kieß; M. Najmabadi; J. Guhathakurta and S. Simon. Journal of Real-Time Image Processing (2017), pp. 1–20.
    35. Hardware-based architecture for asymmetric numeral systems entropy decoder. Seyyed Mahdi Najmabadi; Harsimran Singh Tungal; Trung-Hieu Tran and Sven Simon. In 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017, pp. 1–6. DOI: https://doi.org/10.1109/DASIP.2017.8122109
    36. A resource-efficient monitoring architecture for hardware accelerated self-adaptive online data stream compression. Seyyed Mahdi Najmabadi; Prajwala Pandit; Trung-Hieu Tran and Sven Simon. In 2017 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 2017, pp. 222–227. DOI: https://doi.org/10.23919/SPA.2017.8166868
    37. Light-field image compression based on variational disparity estimation and motion-compensated wavelet decomposition. Trung-Hieu Tran; Yousef Baroud; Zhe Wang; Sven Simon and David Taubman. In 2017 IEEE International Conference on Image Processing (ICIP), 2017, pp. 3260–3264. DOI: https://doi.org/10.1109/ICIP.2017.8296885
    38. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
    39. Evaluating and Mitigating Degradation Effects in Multimedia Circuits. Hussam Amrouch and Jörg Henkel. In Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia’17), Seoul, Republic of Korea, 2017, pp. 61--67.
    40. Optimizing Temperature Guardbands. Hussam Amrouch; Behnam Khaleghi and Jörg Henkel. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE’17), Lausanne, Switzerland, 2017, pp. 175--180.
    41. Analyzing the effect and Performance of Lossy Compression on Aeroacoustic Simulation of Gas Injector. M. Najmabadi; P. Offenhäuser; M. Hamann; J. Guhathakurta; F. Hempert; C. Glass and S. Simon. Journal Computation 5, 2 (2017), pp. 24.
    42. Interdependencies of Degradation Effects and Their Impact on Computing. H. Amrouch; V. M. van Santen and J. Henkel. IEEE Design and Test Magazine (DNT’17) 34, 3 (2017), pp. 59–67.
  5. 2016

    1. Designing reliable, yet energy-efficient guardbands. J. Henkel and H. Amrouch. In IEEE International Conference on Electronics, Circuits and Systems (ICECS’16), 2016, pp. 540–543.
    2. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
    3. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    4. Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 246--251. DOI: https://doi.org/10.1109/ATS.2016.18
    5. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    6. A Neural-Network-Based Fault Classifier. Laura Rodríguez Gómez and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 144--149. DOI: https://doi.org/10.1109/ATS.2016.46
    7. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
    8. Accuracy of 3D position measurement of spherical objects with a holographic single camera setup. J. Guhathakurta; W. Li and S. Simon. N“urnberg, Germany, 2016, pp. 431–437.
    9. Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
    10. Power and thermal management in massive multicore chips: Theoretical foundation meets architectural innovation and resource allocation. P. Bogdan; P. P. Pande; H. Amrouch; M. Shafique and J. Henkel. In 2016 International Conference on Compliers, Architectures, and Sythesis  of Embedded Systems (CASES’16), 2016, pp. 1–2.
    11. Applying Efficient Fault Tolerance to Enable the Preconditioned  Conjugate Gradient Solver on Approximate Computing Hardware. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’16), University of Connecticut, USA, 2016, pp. 21–26. DOI: https://doi.org/10.1109/DFT.2016.7684063
    12. Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. B. Khaleghi; B. Omidi; H. Amrouch; J. Henkel and H. Asadi. In 26th International Conference on Field Programmable Logic and Applications (FPL’16), 2016, pp. 1–8.
    13. Pushing the Limits: How Fault Tolerance Extends the Scope of Approximate  Computing. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS’16), Sant Feliu de Guixols, Catalunya, Spain, 2016, pp. 133--136. DOI: https://doi.org/10.1109/IOLTS.2016.7604686
    14. position measurement of spherical objects with a holographic single camera setup. J. Guhathakurta; D. Schurr; R. Rinke and 3d S. Simon: FERMAT-DFG SPP1740 (June 2016), pp. 6–8.
    15. SHIVA: Sichere Hardware in der Informationsverarbeitung. Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 2016.
    16. Local concentration measurements in the wake of bubbles based on in-situ Raman spectroscopy and statistical analysis. D. Schurr; J. Guhathakurta; Y. Baroud; S. Simon; G. Rinke and R. Dittmeyer. In 9th International Conference on Multiphase Flow (ICMF 2016), Full Paper, Florence , Italy, 2016, pp. 22–27.
    17. Fault Tolerance of Approximate Compute Algorithms. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 34th VLSI Test Symposium (VTS’16), Caesars Palace, Las Vegas, Nevada, USA, 2016. DOI: https://doi.org/10.1109/VTS.2016.7477307
    18. Aging-aware voltage scaling. V. M. van Santen; H. Amrouch; N. Parihar; S. Mahapatra and J. Henkel. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE’16), 2016, pp. 576–581.
    19. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16), Toulouse, France, 2016, pp. 251--262. DOI: https://doi.org/10.1109/DSN.2016.31
    20. Designing guardbands for instantaneous aging effects. V. M. van Santen; H. Amrouch; J. Martin-Martinez; M. Nafria and J. Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), 2016, pp. 1–6, redHiPEAC Paper Award.
    21. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    22. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    23. Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Gert Schley; Ibrahim Ahmed; Muhammad Afzal and Martin Radetzki. Computers & Electrical Engineering 51, (2016), pp. 195--206. DOI: https://doi.org/10.1016/j.compeleceng.2016.02.013
    24. Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. Marcus Eggenberger; Manuel Strobel and Martin Radetzki. In 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016, Heraklion, Crete, Greece, February 17-19, 2016, 2016, pp. 763--770. DOI: https://doi.org/10.1109/PDP.2016.118
    25. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    26. Architecture for Parallelizing Decoding of Marker-Free Variable Length Code Streams. Y. Baroud; J. M. M. Velarde and S. Simon. IEEE SPA (2016), pp. 270–275.
    27. Real-time compression of high-bandwidth measurement data of thermographic cameras with high temporal and spatial resolution. Z. Wang; M. Najmabadi; Y. Baroud; M. Wachs; G. Dammass and S. Simon. NDT ISSN 1435-4934 (2016), pp. 902–909.
    28. Light scattering microscopy measurements of single nuclei compared with GPU-accelerated FDTD simulations. J. Stark; T. Rothe; S. Kieß; S. Simon and A. Kienle. Physics in Medicine and Biology 61, 7 (2016), pp. 2749–2761.
    29. CAD model reconstruction for electromagnetic field simulations by using computed tomography scans. J. Hillebrand; S. Kieß; K. Sun and S. Simon. Dimensional X-ray Computed Tomography Conference, NPL, UK.2016.
    30. A self-adaptive dynamic partial reconfigurable architecture for online data stream compression. Seyyed Mahdi Najmabadi; Zhe Wang; Yousef Baroud and Sven Simon. In 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC), 2016, pp. 19–24. DOI: https://doi.org/10.1109/FPGA4GPC.2016.7518529
    31. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    32. Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. Leandro Gil and Martin Radetzki. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 499--504.
    33. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    34. Reliability-aware design to suppress aging. H. Amrouch; B. Khaleghi; A. Gerstlauer and J. Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), 2016, pp. 1–6, redHiPEAC Paper Award.
    35. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    36. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
    37. Improving Mobile Gaming Performance Through Cooperative CPU-GPU Thermal Management. Alok Prakash; Hussam Amrouch; Muhammad Shafique; Tulika Mitra and Jörg Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), Austin, Texas, 2016, pp. 47:1--47:6.
    38. Low Complexity Pixel Domain Perceptual Image Compression via Adaptive Down-Sampling. Zhe Wang and Sven Simon. In 2016 Data Compression Conference (DCC), 2016, pp. 636–636. DOI: https://doi.org/10.1109/DCC.2016.107
    39. Online Bandwidth Reduction Using Dynamic Partial Reconfiguration. Seyyed Mahdi Najmabadi; Zhe Wang; Yousef Baroud and Sven Simon. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, pp. 168–171. DOI: https://doi.org/10.1109/FCCM.2016.49
    40. A Single-Cycle Parallel Multi-Slice Connected Components Analysis Hardware Architecture. M. Klaiber; D. Bailey and S. Simon. Journal of Real-Time Processing (2016), pp. 1–11.
    41. A Resource-Efficient Hardware Architecture for Connected Component Analysis. Michael J. Klaiber; Donald G. Bailey; Yousef O. Baroud and Sven Simon. IEEE Transactions on Circuits and Systems for Video Technology 26, 7 (2016), pp. 1334–1349. DOI: https://doi.org/10.1109/TCSVT.2015.2450371
    42. A Parallel Codec Architecture for Marker-free Variable Length Code Streams. Y. Baroud; N. Lê; Z. Wang; S. Kieß; S. M. Najmabadi and S. Simon. in Proceedings of the HiPEAC Workshop on Reconfigurable Computing (WRC) 10, (2016), pp. 1–7.
    43. Low complexity perceptual image coding by just-noticeable difference model based adaptive downsampling. Zhe Wang; Yousef Baroud; Seyyed Mahdi Najmabadi and Sven Simon. In 2016 Picture Coding Symposium (PCS), 2016, pp. 1–5. DOI: https://doi.org/10.1109/PCS.2016.7906359
  6. 2015

    1. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (December 2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    2. Reliability degradation in the scope of aging -- From physical to system level. H. Amrouch and J. Henkel. In 10th International Design Test Symposium (IDT’15), 2015, pp. 9–12.
    3. Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. Michael Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omana; Cecilia Metra and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 157–162. DOI: https://doi.org/10.1109/ATS.2015.34
    4. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    5. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    6. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD’15), Austin, Texas, USA, 2015, pp. 38–45.
    7. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
    8. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI  and Nanotechnology Systems (DFT’15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
    9. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
    10. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    11. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate  Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 95--100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
    12. Lucid infrared thermography of thermally-constrained processors. H. Amrouch and J. Henkel. In 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’15), 2015, pp. 347–352.
    13. Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, 3 (June 2015), pp. 149--158. DOI: https://doi.org/10.1515/itit-2014-1082
    14. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (June 2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    15. High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 3 (June 2015), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2714564
    16. Connecting the physical and application level towards grasping aging effects. H. Amrouch; J. Martin-Martinez; V. M. van Santen; M. Moras; R. Rodriguez; M. Nafria and J. Henkel. In IEEE International Reliability Physics Symposium (IRPS’15), 2015, pp. 3D.1.1-3D.1.8.
    17. On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 589--592. DOI: https://doi.org/10.7873/DATE.2015.0940
    18. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    19. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    20. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    21. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (February 2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
    22. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    23. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
    24. A High-Speed Process Monitoring System to Detect and Analyze Filaments and Droplet Collisions in Spray Processes in Real Time. M. Klaiber; S. Simon; J. Guhathakurta; W. Li; Z. Wang; A. Lampa and U. Fritsching. 13th Triennial Internat Conf. on Liquid Atomization and Spray Systems, Taiwan, ICLASS (2015), pp. 1–6.
    25. Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. Gert Schley and Martin Radetzki. In 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, Turku, Finland, March 4-6, 2015, 2015, pp. 379--386. DOI: https://doi.org/10.1109/PDP.2015.36
    26. Optimal memory selection for low power embedded systems. Marcus Eggenberger and Martin Radetzki. In 12th International Workshop on Intelligent Solutions in Embedded Systems, WISES 2015, Ancona, Italy, October 29-30, 2015, 2015, pp. 11--16.
    27. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    28. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    29. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    30. Visually lossless image compression extension for JPEG based on just-noticeable distortion evaluation. Zhe Wang; Sven Simon; Yousef Baroud and Seyyed Mahdi Najmabadi. In 2015 International Conference on Systems, Signals and Image Processing (IWSSIP), 2015, pp. 237–240. DOI: https://doi.org/10.1109/IWSSIP.2015.7314220
    31. Signal Integrity Model Extraction Based on Computed Tomography Scans—Analysis of the Required Voxel Resolution. Jürgen Hillebrand; Steffen Kieß; Jajnabalkya Guhathakurta and Sven Simon. IEEE Transactions on Electromagnetic Compatibility 57, 4 (2015), pp. 847–857. DOI: https://doi.org/10.1109/TEMC.2015.2435995
    32. High throughput hardware architectures for asymmetric numeral systems entropy coding. Seyyed Mahdi Najmabadi; Zhe Wang; Yousef Baroud and Sven Simon. In 2015 9th International Symposium on Image and Signal Processing and Analysis (ISPA), 2015, pp. 256–259. DOI: https://doi.org/10.1109/ISPA.2015.7306068
    33. ’Computed Tomography Resolution Enhancement by Integrating High-Resolution 2D X-Ray Images into the CT reconstruction. S. Kieß; J. Guhathakurta; J. Hillebrand and S. Simon et al.: 2015, pp. 1–9.
  7. 2014

    1. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (December 2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    2. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    3. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    4. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23. DOI: https://doi.org/10.1109/ICCAD.2014.7001324
    5. Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine(BIBM’14), Belfast, United Kingdom, 2014, pp. 424--431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
    6. Towards interdependencies of aging mechanisms. H. Amrouch; V. M. van Santen; T. Ebi; V. Wenzel and J. Henkel. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’14), 2014, pp. 478–485.
    7. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2014.7035350
    8. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2014.7035360
    9. Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 5 (September 2014), pp. 527--540. DOI: https://doi.org/10.1007/s10836-014-5477-1
    10. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 4 (August 2014), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2647955
    11. SAT-Based ATPG beyond Stuck-at Fault Testing. Sybille Hellebrand and Hans-Joachim Wunderlich. it - Information Technology 56, 4 (July 2014), pp. 165--172. DOI: https://doi.org/10.1515/itit-2013-1043
    12. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
    13. A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’14), Atlanta, Georgia, USA, 2014, pp. 443--454. DOI: https://doi.org/10.1109/DSN.2014.48
    14. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 4 (June 2014), pp. 401--413. DOI: https://doi.org/10.1007/s10836-014-5459-3
    15. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--6. DOI: https://doi.org/10.1145/2593069.2593146
    16. Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Ulrich Abelein and Piet Engelke. In Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--9. DOI: https://doi.org/10.1145/2593069.2602971
    17. Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 3 (June 2014), pp. 28:1--28:17. DOI: https://doi.org/10.1145/2611760
    18. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
    19. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
    20. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
    21. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
    22. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE’14 Conference, Dresden, Germany, 2014.
    23. Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
    24. Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures. Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.373
    25. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    26. hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding. D. Palomino; M. Shafique; H. Amrouch; A. Susin and J. Henkel. In Design, Automation Test in Europe Conference Exhibition (DATE’14), 2014, pp. 1–4.
    27. mDTM: Multi-objective dynamic thermal management for on-chip systems. H. Khdr; T. Ebi; M. Shafique; H. Amrouch and J. H. Karlsruhe. In Design, Automation Test in Europe Conference Exhibition (DATE’14), 2014, pp. 1–6.
    28. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, 6--7 (2014), pp. 1066--1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
    29. Asynchronous parallel simulation with transaction events. Bastian Haetzer and Martin Radetzki. In XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, 2014, pp. 242--249. DOI: https://doi.org/10.1109/SAMOS.2014.6893217
    30. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    31. RESI: Register-Embedded Self-Immunity for Reliability Enhancement. H. Amrouch; T. Ebi and J. Henkel. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’14) 33, 5 (2014), pp. 677–690.
    32. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    33. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    34. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    35. Real-time Process Analysis System for the Pulsation Detection and Measurement in Spray Processes. M. Klaiber; A. Kleinhans; P. Stähle; V. Gaukel and S. Simon. In 26th Annual Conference on Liquid Atomization and Spray Systems, 2014, pp. 1–5.
    36. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
    37. Editorial introduction - Special issue on languages, models and model based design for embedded systems. Martin Radetzki and Axel Jantsch. Design Autom. for Emb. Sys. 18, 1–2 (2014), pp. 61--62. DOI: https://doi.org/10.1007/s10617-012-9094-x
    38. SystemC AMS power electronic modeling with ideal instantaneous switches. Leandro Gil and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119365
    39. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    40. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    41. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    42. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    43. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262--285.
    44. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    45. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    46. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    47. A comparison of parallel systemc simulation approaches at RTL. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014, 2014, pp. 1--8. DOI: https://doi.org/10.1109/FDL.2014.7119355
    48. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    49. Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures. Ghada Dessouky; Michael J. Klaiber; Donald G. Bailey and Sven Simon. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8. DOI: https://doi.org/10.1109/FPL.2014.6927471
    50. Simulation Models for Signal Integrity Analyses Extracted from Computed Tomography Scans -- A Case Study for High-Speed Interconnects. S. Simon; J. Hillebrand and S. Kieß. In IEEE International Symposium on Electromagnetic Compatibility, USA, 2014, pp. 973–978.
  8. 2013

    1. Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
    2. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    3. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    4. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI: https://doi.org/10.1109/DFT.2013.6653580
    5. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
    6. Analyzing the thermal hotspots in FPGA-based embedded systems. H. Amrouch; T. Ebi; J. Schneider; S. Parameswaran and J. Henkel. In 23rd International Conference on Field programmable Logic and Applications (FPL’13), 2013, pp. 1–4.
    7. Test Strategies for Reliable Runtime Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. IEEE Transactions on Computers 62, 8 (August 2013), pp. 1494--1507. DOI: https://doi.org/10.1109/TC.2013.53
    8. Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS’13), Crete, Greece, 2013, pp. 240--243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
    9. Stress balancing to mitigate NBTI effects in register files. H. Amrouch; T. Ebi and J. Henkel. In 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’13), 2013, pp. 1–10.
    10. Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS’13), Avignon, France, 2013, pp. 39--45. DOI: https://doi.org/10.1109/ETS.2013.6569354
    11. Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW’13), Cordoba, Argentina, 2013.
    12. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip. Andreas Herkersdorf; Michael Engel; Michael Glaß; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. In Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 2013.
    13. Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 276--281. DOI: https://doi.org/10.7873/DATE.2013.069
    14. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 436--441. DOI: https://doi.org/10.7873/DATE.2013.098
    15. Thermal management for dependable on-chip systems. J. Henkel; T. Ebi; H. Amrouch and H. Khdr. In 18th Asia and South Pacific Design Automation Conference (ASP-DAC’13), 2013, pp. 113–118.
    16. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    17. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    18. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    19. Simulation analysis and validation. Frank Oppenheimer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    20. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    21. Comparison of CPU and GPU based coding on low-complexity algorithms for display signals. T. Richter and S. Simon. Proceedings SPIE 8856 : Application of Digital Image Processing XXXVI (2013), pp. 1–14.
    22. Imaging Sensor with Integrated Feature Extraction Using Connected Component Labeling. M. Klaiber; S. Ahmed; M. Najmabadi; W. Li Y. Baroud and S. Simon. Proceedings SENSOR 2013, Nuremberg (2013), pp. 426–431.
    23. Optimal placement of vertical connections in 3D Network-on-Chip. Thomas Canhao Xu; Gert Schley; Pasi Liljeberg; Martin Radetzki; Juha Plosila and Hannu Tenhunen. Journal of Systems Architecture - Embedded Systems Design 59, 7 (2013), pp. 441--454. DOI: https://doi.org/10.1016/j.sysarc.2013.05.002
    24. Scalable parallel simulation of networks on chip. Marcus Eggenberger and Martin Radetzki. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013, 2013, pp. 1--8. DOI: https://doi.org/10.1109/NoCS.2013.6558402
    25. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    26. Methods for fault tolerance in networks-on-chip. Martin Radetzki; Chaochao Feng; Xueqian Zhao and Axel Jantsch. ACM Comput. Surv. 46, 1 (2013), pp. 8:1--8:38. DOI: https://doi.org/10.1145/2522968.2522976
    27. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    28. Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits. A. Amouri; H. Amrouch; T. Ebi; J. Henkel and M. Tahoori. In IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’13), 2013, pp. 57–60, redHiPEAC Paper Award.
    29. Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. Gert Schley; Nikolaos Batzolis and Martin Radetzki. In 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013, Belfast, United Kingdom, February 27 - March 1, 2013, 2013, pp. 454--461. DOI: https://doi.org/10.1109/PDP.2013.74
    30. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
    31. Power Management for High-Performance Applications on Network-on-Chip-Based Multiprocessors. Adán Kohler and Martin Radetzki. In 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, Physical and Social Computing (CPSCom), Beijing, China, August 20-23, 2013, 2013, pp. 77--85. DOI: https://doi.org/10.1109/GreenCom-iThings-CPSCom.2013.38
    32. Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. Khalid Latif; Amir-Mohammad Rahmani; Ethiopia Nigussie; Tiberiu Seceleanu; Martin Radetzki and Hannu Tenhunen. J. Electronic Testing 29, 3 (2013), pp. 431--452. DOI: https://doi.org/10.1007/s10836-013-5389-5
    33. Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. Weiyun Lu and Martin Radetzki. Microprocessors and Microsystems - Embedded Hardware Design 37, 2 (2013), pp. 115--128. DOI: https://doi.org/10.1016/j.micpro.2012.09.005
    34. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    35. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    36. Systemc transaction level modeling with transaction events. Bastian Haetzer and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--6.
    37. Fine grained adaptive simulation with application to NoCs. Marcus Eggenberger and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1--8.
    38. Stream Processing of Scientific Big Data on Heterogeneous Platforms -- Image Analytics on Big Data in Motion. S.M. Najmabadi; M. Klaiber; Z. Wang; Y. Baroud and S. Simon. In 2013 IEEE 16th International Conference on Computational Science and Engineering, 2013, pp. 965–970. DOI: https://doi.org/10.1109/CSE.2013.142
    39. Coding strategies and performance analysis of GPU accelerated image compression. Thomas Richter and Sven Simon. In 2013 Picture Coding Symposium (PCS), 2013, pp. 125–128. DOI: https://doi.org/10.1109/PCS.2013.737699
    40. Real-time Determination of Interfacial Tension from the Shape of a Pendant Drop Based on Embedded Image Processing. M. Najmabadi; F. Tamm; M. Klaiber; Y. Baroud; S. Drusch and S. Simon. 2013, pp. 1–6.
    41. Platform based design. Jean-Philippe Babau and Martin Radetzki. In Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, 2013, pp. 1.
    42. A high-throughput FPGA architecture for parallel connected components analysis based on label reuse. Michael J. Klaiber; Donald G. Bailey; Silvia Ahmed; Yousef Baroud and Sven Simon. In 2013 International Conference on Field-Programmable Technology (FPT), 2013, pp. 302–305. DOI: https://doi.org/10.1109/FPT.2013.6718372
    43. High Throughput Coding of Video Signals. Thomas Richter and Sven Simon. In 2013 Data Compression Conference, 2013, pp. 517–517. DOI: https://doi.org/10.1109/DCC.2013.96
  9. 2012

    1. Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
    2. Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, 12 (December 2012), pp. 1908--1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
    3. Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 214--219. DOI: https://doi.org/10.1109/ATS.2012.32
    4. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    5. Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 155--160. DOI: https://doi.org/10.1109/ATS.2012.23
    6. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
    7. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’12), Philadelphia, Pennsylvania, USA, 2012, pp. 1--6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
    8. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (October 2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
    9. Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012, pp. 37--42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
    10. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, Germany, 2012, pp. 38--45. DOI: https://doi.org/10.1109/AHS.2012.6268667
    11. Online Imaging Analysis of Spray Processes Based on a Reconfigurable Embedded System. M. Klaiber; S. Ahmed; Z. Wang; L. Rockstroh; Y. Gera and S. Simon. In 10. Workshop über Sprays, Techniken der Fluidzerstäubung und Untersuchungen von Sprühvorgängen. 2012, pp. 1–7.
    12. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS’12), Hyatt Maui, Hawaii, USA, 2012, pp. 50--55. DOI: https://doi.org/10.1109/VTS.2012.6231079
    13. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW’12), Quito, Ecuador, 2012, pp. 1--4. DOI: https://doi.org/10.1109/LATW.2012.6261229
    14. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    15. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12), Montreal, Canada, 2012, pp. 207--212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
    16. Efficient System-Level Aging Prediction. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 164--169. DOI: https://doi.org/10.1109/ETS.2012.6233028
    17. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. Alejandro Cook; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 146--151. DOI: https://doi.org/10.1109/ETS.2012.6233025
    18. Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 98--103. DOI: https://doi.org/10.1109/ETS.2012.6233017
    19. COOL: Control-based Optimization of Load-balancing for Thermal Behavior. Thomas Ebi; Hussam Amrouch and Jörg Henkel. In Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’12), Tampere, Finland, 2012, pp. 255--264.
    20. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    21. Latency-optimized Collectives for High Performance on Intel’s Single-chip Cloud Computer. Adán Kohler and Martin Radetzki. In Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University, November 29th-30th 2012, Aachen, Germany, 2012, pp. 7--12.
    22. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    23. Minimal MPI as programming interface for multicore System-on-Chips. Adán Kohler; Juan Manuel Castillo-Sanchez; Joachim Gross and Martin Radetzki. In Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, 2012, pp. 127--134.
    24. Semantics and efficient simulation of accuracy-adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. Design Autom. for Emb. Sys. 16, 3 (2012), pp. 1--29. DOI: https://doi.org/10.1007/s10617-012-9095-9
    25. Low-Latency Collectives for the Intel SCC. Adán Kohler; Martin Radetzki; Philipp Gschwandtner and Thomas Fahringer. In 2012 IEEE International Conference on Cluster Computing, CLUSTER 2012, Beijing, China, September 24-28, 2012, 2012, pp. 346--354. DOI: https://doi.org/10.1109/CLUSTER.2012.58
    26. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    27. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    28. Optimized Reduce for Mesh-Based NoC Multiprocessors. Adán Kohler and Martin Radetzki. In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, 2012, pp. 904--913. DOI: https://doi.org/10.1109/IPDPSW.2012.111
    29. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    30. Correlation and convolution of image data using fermat number transform based on two’s complement. Lars Rockstroh; Michael Klaiber and Sven Simon. In 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2012, pp. 1637–1640. DOI: https://doi.org/10.1109/ICASSP.2012.6288209
    31. In-process Measuring Procedure for Sub-100 nm Structures. M. Zimmermann; A. Tausendfreund; S. Patzelt; G. Goch and S. Simon et al. Journal of Laser Applications 24, 4 (2012).
    32. Fast and Context-Free Lossless Image Compression Algorithm Based on JPEG-LS. Yurij Gera; Zhe Wang; Sven Simon and Thomas Richter. In 2012 Data Compression Conference, 2012, pp. 396–396. DOI: https://doi.org/10.1109/DCC.2012.64
    33. Memory efficient lossless compression of image sequences with JPEG-LS and temporal prediction. Zhe Wang; Debasish Chanda; Sven Simon and Thomas Richter. In 2012 Picture Coding Symposium, 2012, pp. 305–308. DOI: https://doi.org/10.1109/PCS.2012.6213353
    34. Monitoring of collisions in fast droplet streams by real-time image processing with line sensors. Y. Baroud; S. Eggerstedt; M. Klaiber; R. Süverkrüp; S. Simon and A. Lamprecht. ILASS-Americas 24th Conf. on Liquid Atomization and Spray System (2012), pp. 1–7.
    35. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    36. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    37. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
    38. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    39. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    40. On the JPEG 2000 ultrafast mode. Thomas Richter and Sven Simon. In 2012 19th IEEE International Conference on Image Processing, 2012, pp. 2501–2504. DOI: https://doi.org/10.1109/ICIP.2012.6467406
    41. Towards high-speed, low-complexity image coding: variants and modification of JPEG 2000. T. Richter and S. Simon. SPIE 8499 Optical Engineering + Applications (2012), pp. 1–11.
    42. SSPQ - spatial domain perceptual image codec based on subsampling and perceptual quantization. Z. Wang; S. Simon; M. Klaiber; S. Ahmed and Th. Richter. In 2012 19th IEEE International Conference on Image Processing, 2012, pp. 1061–1064. DOI: https://doi.org/10.1109/ICIP.2012.6467046
    43. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    44. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    45. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    46. S-parameter extraction of bond wires based on EM field simulations of computed tomography-generated 3D CAD models. Jürgen Hillebrand; Steffen Kieß; Marek Wróblewski and Sven Simon. In 2012 IEEE 16th Workshop on Signal and Power Integrity (SPI), 2012, pp. 39–42. DOI: https://doi.org/10.1109/SaPIW.2012.6222907
    47. A memory-efficient parallel single pass architecture for connected component labeling of streamed images. Michael Klaiber; Lars Rockstroh; Zhe Wang; Yousef Baroud and Sven Simon. In 2012 International Conference on Field-Programmable Technology, 2012, pp. 159–165. DOI: https://doi.org/10.1109/FPT.2012.6412129
    48. On the Estimation of Numerical Error Bounds in Linear Algebra Based on Discrete Stochastic Arithmetic. W. Li; S. Simon and S. Kiess. Journal: Applied Numerical Mathematics 62, 5 (2012), pp. 536–555.
    49. Investigation of polymerization and drying of polyvinylpyrrolidone in an acoustic levitator using a smart camera for online process measurement. J. Laackmann; S. Ahmed; R. Sedelmayer; M. Klaiber; W. Pauer; S. Simon and H.-U. Moritz. In ICLASS 2012, 12th Triennial Internat. Conf. on Liquid Atomization and Spray Systems. 2012, pp. 1–8.
    50. Relaxation of particle image velocimetry based on single autocorrelation of filtered motion blurring. T. Lefeure; L. Rockstroh; M. Klaiber; N. Fortier and S. Simon. In 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2012, pp. 1329–1332. DOI: https://doi.org/10.1109/ICASSP.2012.6288135
  10. 2011

    1. Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 213--218. DOI: https://doi.org/10.1109/ATS.2011.60
    2. Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 285--290. DOI: https://doi.org/10.1109/ATS.2011.55
    3. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
    4. Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 383--388. DOI: https://doi.org/10.1109/ATS.2011.52
    5. Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS’11), Taipei, Taiwan, 2011, pp. 69--78. DOI: https://doi.org/10.1145/2039370.2039384
    6. Robuster Selbsttest mit Diagnose. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 48--53.
    7. Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 76--83.
    8. Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 43--47.
    9. P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
    10. A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failures in Scan Testing. Yuta Yamato; Xiaoqing Wen; Michael A. Kochte; Kohei Miyase; Seiji Kajihara and Laung-Terng Wang. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139162
    11. Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults. Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich and Christian G. Zoellin. SCIENCE CHINA Information Sciences 54, 9 (September 2011), pp. 1784--1796. DOI: https://doi.org/10.1007/s11432-011-4366-9
    12. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (September 2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    13. SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures. Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, 2011, pp. 33--38. DOI: https://doi.org/10.1109/ISLPED.2011.5993600
    14. Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 169--174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
    15. Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 278--283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
    16. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 111--116. DOI: https://doi.org/10.1109/ETS.2011.25
    17. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    18. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 183--188. DOI: https://doi.org/10.1109/ETS.2011.33
    19. Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing. Xiaoqing Wen; Kazunari Enokimoto; Kohei Miyase; Yuta Yamato; Michael A. Kochte; Seiji Kajihara; Patrick Girard and Mohammad Tehranipoor. In Proceedings of the 29th IEEE VLSI Test Symposium (VTS’11), Dana Point, California, USA, 2011, pp. 166--171. DOI: https://doi.org/10.1109/VTS.2011.5783778
    20. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011, pp. 1303--1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
    21. Self-Immunity Technique to Improve Register File Integrity Against Soft Errors. H. Amrouch and J. Henkel. In 2011 24th Internatioal Conference on VLSI Design (VLSID’11), 2011, pp. 189–194.
    22. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011, pp. 55--58.
    23. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    24. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    25. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    26. Efficient Fault Simulation of SystemC Designs. Weiyun Lu and Martin Radetzki. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, 2011, pp. 487--494. DOI: https://doi.org/10.1109/DSD.2011.68
    27. A metamodel and semantics for transaction level modeling. Rauf Salimi Khaligh and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    28. Practical embedded systems engineering syllabus for graduate students with multidisciplinary backgrounds. Bastian Haetzer; Gert Schley; Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 6th Workshop on Embedded Systems Education, WESE 2011, Taipei, Taiwan, October 13, 2011, 2011, pp. 1--8. DOI: https://doi.org/10.1145/2077370.2077371
    29. Cost-Based Deflection Routing for Intelligent NoC Switches. Martin Radetzki and Adán Kohler. In Solutions on Embedded Systems, Massimo Conti; Simone Orcioni; Natividad Mart\’ınez Madrid and Ralf E. D. Seepold (eds.). Springer, 2011, pp. 77--90. DOI: https://doi.org/10.1007/978-94-007-0638-5_6
    30. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    31. Exploitation of context classification for parallel pixel coding in JPEG-LS. S. Wahl; H. A. Tantawy; Z. Wang; P. Werner and S. Simon. In 2011 18th IEEE International Conference on Image Processing, 2011, pp. 2001–2004. DOI: https://doi.org/10.1109/ICIP.2011.6115869
    32. A memory efficient parallel lossless image compression engine for high performance embedded systems. Zhe Wang; Anto Y. Michael; Simeon Wahl; Philipp Werner and Sven Simon. In 2011 7th International Symposium on Image and Signal Processing and Analysis (ISPA), 2011, pp. 390–395.
    33. In Situ Power Analysis of General Purpose Graphical Processing Units. M.Z. Shaikh; M. Gregoire; W. Li; M. Wroblewski and S. Simon. In 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011, pp. 40–44. DOI: https://doi.org/10.1109/PDP.2011.67
    34. In-Process Defect Characterization Method for Nanostructured Surfaces. A. Tausendfreund and S. Simon et. al. the 10th International Symposium of Measurement Technology and Intelligent Instruments 10, (2011), pp. 1–5.
    35. CAD model reconstruction of solder balls for the computationally efficient electromagnetic field simulation. Jürgen Hillebrand; Steffen Kieß; Yu Wang; Marek Wróblewski and Sven Simon. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011, pp. 279–282. DOI: https://doi.org/10.1109/EPEPS.2011.6100246
    36. Simulation von Streulicht-Messeffekten im Nanometerbereich. A. Tausendfreund; S. Patzelt; L. Rockstroh; S. Simon and G. Goch. 14. GMA/ITG-Fachtagung "Sensoren und Messsysteme 2008 ", VDI Berichte (2011).
    37. S-parameter extraction of passive sub-circuits using computed tomography scans and measured substrate material parameters. Jürgen Hillebrand; Steffen Kieß; Marek Wróblewski and Sven Simon. In 78th ARFTG Microwave Measurement Conference, 2011, pp. 1–6. DOI: https://doi.org/10.1109/ARFTG78.2011.6183869
    38. Numerical Accuracy Analysis and Debugging for Complex Simulation Software. W. Li and S. Simon. Simulation Technology Conference.2011.
    39. 3D Computed Tomography for High-Speed Interconnect Characterization. J. Hillebrand; M. Wroblewski and S. Simon. DesignCon USA (2011), pp. 9–19.
    40. Optimal distribution of privileged nodes in networks-on-chip. Gert Schley and Martin Radetzki. In Proceedings of the Ninth Workshop on Intelligent Solutions in Embedded Systems, WISES 2011, Regensburg, Germany, July 7-8, 2011, 2011, pp. 87--92.
    41. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    42. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    43. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    44. A case study on message-based discrete event simulation for Transaction Level Modeling. Bastian Haetzer and Martin Radetzki. In 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011, 2011, pp. 1--8.
    45. Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. Martin Radetzki. In IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, EUC 2011, Melbourne, Australia, October 24-26, 2011, 2011, pp. 33--40. DOI: https://doi.org/10.1109/EUC.2011.36
    46. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    47. Determining the Numerical Stability of Quantum Chemistry Algorithms. G. Knizia; W. Li; S. Simon and H.-J. Werner. Journal of Chemical Theory and Computation 7, 8 (2011), pp. 2387–2398.
    48. Estimation of Rounding Errors on Hybrid Hardware Systems. W. Li and S. Simon. In International Conference on High Performance Computing & Simulation, 2011.
    49. Accuracy of 2D Continuous Particle Image Velocimetry Measurements in Thermal Spraying Processes. L. Rockstroh; S. Wahl; P. Werner; Z. Wang; S. Simon and R. Gadow. In Proceedings of International Thermal Spray Conference, Hamburg, 2011, pp. 1426–1432.
    50. An image filter technique to relax particle image velocimetry. L. Rockstroh; S. Wahl; Z. Wang; P. Werner and S. Simon. In 2011 19th European Signal Processing Conference, 2011, pp. 283–287.
    51. In-process optical characterization method for sub-100-nm nanostructures. S. Kieß; M. Z. Shaikh; M. Grégoire; T. Bringewat; S. Simon; A. Tausendfreund; M. Zimmermann and G. Goch. In 2011 IEEE International Instrumentation and Measurement Technology Conference, 2011, pp. 1–4. DOI: https://doi.org/10.1109/IMTC.2011.5944117
    52. Simultaneous characterization of particle velocities and sizes based on autocorrelation of filtered motion blurring. L. Rockstroh; T. Lefeure; S. Wahl; N. Fortier and S. Simon. In International Conference on Liquid Atomization and Spray Systems, Portugal, 2011, pp. 1–5.
  11. 2010

    1. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 39--44. DOI: https://doi.org/10.1109/ATS.2010.16
    2. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    3. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 3--8. DOI: https://doi.org/10.1109/ATS.2010.10
    4. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T’10), Austin, Texas, USA, 2010.
    5. Efficient Concurrent Self-Test with Partially Specified Patterns. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 26, 5 (October 2010), pp. 581--594. DOI: https://doi.org/10.1007/s10836-010-5167-6
    6. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’10), Wildbad Kreuth, Germany, 2010, pp. 25--32.
    7. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen;  Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, 4 (August 2010), pp. 209--215. DOI: https://doi.org/10.1524/itit.2010.0593
    8. Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC’10), Anaheim, California, USA, 2010, pp. 380--385. DOI: https://doi.org/10.1145/1837274.1837369
    9. Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS’10), Praha, Czech Republic, 2010, pp. 253--253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
    10. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS’10), Santa Cruz, California, USA, 2010, pp. 93--98. DOI: https://doi.org/10.1109/VTS.2010.5469607
    11. BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 1243--1248.
    12. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
    13. Parity Prediction Synthesis for Nano-Electronic Gate Designs. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699312
    14. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    15. Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    16. Application Dependent Vulnerability of Combinational Circuits. Rafal Baranowski and Hans-Joachim Wunderlich. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    17. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    18. A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Proceedings of the 2010 Forum on specification & Design Languages,FDL 2010, September 14-16, 2010, Southampton, UK, 2010, pp. 130--135.
    19. Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches). Gert Schley; Martin Radetzki and Adán Kohler. it - Information Technology 52, 4 (2010), pp. 201--208. DOI: https://doi.org/10.1524/itit.2010.0592
    20. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. Rauf Salimi Khaligh and Martin Radetzki. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010, pp. 1183--1188. DOI: https://doi.org/10.1109/DATE.2010.5456987
    21. Memory-Efficient Parallelization of JPEG-LS with Relaxed Context Update. S. Wahl; Z. Wang and S. Simon. Picture Coding Symposium (2010), pp. 423–426.
    22. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    23. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
    24. Fault Tolerant Network on Chip Switching With Graceful Performance Degradation. Adán Kohler; Gert Schley and Martin Radetzki. IEEE Trans. on CAD of Integrated Circuits and Systems 29, 6 (2010), pp. 883--896. DOI: https://doi.org/10.1109/TCAD.2010.2048399
    25. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    26. Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187--215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
    27. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    28. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    29. Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133--155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
    30. Numerical Error Analysis for Statistical Software on Multi-Core Systems. W. Li and S. Simon. In 19th International Conference on Computational Statistics, 2010, pp. 1–5.
    31. Messung von Partikelgeschwindigkeiten in Fertigungsprozessen unter Berücksichtigung der Abbildungseigenschaften des eingesetzten Kamerasystems. L. Rockstroh and S. Simon et. al. Expertenforum Bilderverarbeitung VDI (2010), pp. 229–241.
    32. Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117--146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
    33. Models in Hardware Testing. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.2010. DOI: https://doi.org/10.1007/978-90-481-3282-9
    34. A Particle Image Velocimetry Method for Low Illumination Conditions in Thermal Spray Processes. L. Rockstroh and S. Simon et.al. Conference Proceedings, International Thermal Spray Conference, Singapore (2010), pp. 1–4.
    35. Error Analysis of Image-based Measuring Methods in Thermal Spraying Processes: A simulation-Driven Approach. S. Simon L. Rockstroh and R. Gadow et.al. International Thermal Spray Conference, Singapore (2010), pp. 1–4.
  12. 2009

    1. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’09), Stuttgart, Germany, 2009, pp. 21--28.
    2. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (August 2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
    3. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 53--58. DOI: https://doi.org/10.1109/ETS.2009.26
    4. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
    5. Restrict Encoding for Mixed-Mode BIST. Abdul-Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke and Andreas Glowatz. In Proceedings of the 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, California, USA, 2009, pp. 179--184. DOI: https://doi.org/10.1109/VTS.2009.43
    6. Test Exploration and Validation Using Transaction Level Models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    7. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
    8. Modellierung der Testinfrastruktur auf der Transaktionsebene. Michael A. Kochte; Christian Zöllin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In 21th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 61--66.
    9. Diagnose mit extrem kompaktierten Fehlerdaten. Stefan Holst and Hans-Joachim Wunderlich. In 21. ITG/GI/GMM Workshop “Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 15--20.
    10. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
    11. Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. Rauf Salimi Khaligh and Martin Radetzki. In Analysis, Architectures and Modelling of Embedded Systems, Third IFIPTC 10 International Embedded Systems Symposium, IESS 2009, Langenargen,Germany, September 14-16, 2009. Proceedings, 2009, pp. 149--158. DOI: https://doi.org/10.1007/978-3-642-04284-3_14
    12. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
    13. Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. Adán Kohler and Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009, 2009, pp. 207--216.
    14. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    15. Fault-tolerant architecture and deflection routing for degradable NoC switches. Adán Kohler and Martin Radetzki. In Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, 2009, pp. 22--31. DOI: https://doi.org/10.1109/NOCS.2009.5071441
    16. Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen. Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (Eds.). Springer-Verlag Heidelberg.2009. DOI: https://doi.org/10.1007/978-3-540-85091-5
    17. An intelligent deflection router for networks-on-chip. Martin Radetzki and Adán Kohler. In Seventh Workshop on Intelligent solutions in Embedded Systems, WISES 2009, Ancona, Italy, June 25-26, 2009, 2009, pp. 57--62.
    18. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    19. Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL’08, September 23-25, 2008, Stuttgart, Germany. Martin Radetzki (Ed.). 2009. DOI: https://doi.org/10.1007/978-1-4020-9714-0
    20. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
    21. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
    22. Benchmark results for asynchronous high-speed FPGAs focusing on high performance digital signal processing. Lars Rockstroh; Wenbin Li; Juergen Hillebrand; Marek Wroblewski and Sven Simon. In 2009 International Conference on Field-Programmable Technology, 2009, pp. 423–426. DOI: https://doi.org/10.1109/FPT.2009.5377696
    23. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
    24. A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip. Adán Kohler and Martin Radetzki. In Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, 2009, pp. 1--4.
    25. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen. Hans-Joachim Wunderlich; Melanie Elm and Michael A. Kochte. In Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertungin frühen Entwicklungsphasen, Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (eds.). Springer-Verlag Heidelberg, 2009, pp. 391--464. DOI: https://doi.org/10.1007/978-3-540-85091-5_8
  13. 2008

    1. On the Reliability Modeling of Embedded Hardware-Software Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 1st IEEE Workshop on Design for Reliability and Variability (DRV’08), Santa Clara, California, USA, 2008.
    2. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS’08), Rhodes, Greece, 2008, pp. 59--64. DOI: https://doi.org/10.1109/IOLTS.2008.31
    3. Scan Chain Clustering for Test Power Reduction. Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra and Nicolas Maeding. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08), Anaheim, California, USA, 2008, pp. 828--833. DOI: https://doi.org/10.1145/1391469.1391680
    4. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS’08), Lago Maggiore, Italy, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    5. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian Zöllin. In 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR’08), Verbania, Italy, 2008.
    6. A Framework for Scheduling Parallel DBMS User-Defined Programs on an Attached High-Performance Computer. Michael A. Kochte and Ramesh Natarajan. In Proceedings of the 2008 conference on Computing frontiers (CF’08), Ischia, Italy, 2008, pp. 97--104. DOI: https://doi.org/10.1145/1366230.1366245
    7. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
    8. Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. Torsten Coym; Sybille Hellebrand; Stefan Ludwig; Bernd Straube; Hans-Joachim Wunderlich and Christian Zöllin. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 153--157.
    9. Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008.
    10. Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information. Michael E. Imhof; Hans-Joachim Wunderlich; Christian Zöllin; Jens Leenstra and Nicolas Maeding. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 137--141.
    11. Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung. Melanie Elm and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 7--11.
    12. Test Set Stripping Limiting the Maximum Number of Specified Bits. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE International Symposium on ElectronicDesign, Test and Applications (DELTA’08), 2008, pp. 581--586. DOI: https://doi.org/10.1109/DELTA.2008.64
    13. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung;  Detection of transient faults in circuits with reduced power dissipation. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 107--114.
    14. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen;  On the Reliability Modeling of Hardware-Software-Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 83--90.
    15. Signature Rollback – A Technique for Testing Robust Circuits. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, 2008, pp. 125--130. DOI: https://doi.org/10.1109/VTS.2008.34
    16. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
    17. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
    18. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
    19. Accuracy-Adaptive Simulation of Transaction Level Models. Martin Radetzki and Rauf Salimi Khaligh. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 788--791. DOI: https://doi.org/10.1109/DATE.2008.4484912
    20. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
    21. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
    22. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
    23. Accelerating light scattering simulations of nanostructures by reconfigurable computing. L. Rockstroh; A. Balevic; M. Wroblewski; J. Hillebrand; A. Tausendfreund; S. Patzelt; S. Simon and G. Goch. In 2008 3rd IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2008, pp. 1177–1180. DOI: https://doi.org/10.1109/NEMS.2008.4484527
    24. et.al., Virtuelle Messgeräte - Eine Definition. R. Schmitt; F. Koerfer; A. Tausendfreund; S. Patzelt; S. Simon and L. Rockstroh. Zeitschrift: Technisches Messen 75, (2008), pp. 327–339.
    25. Erfassung von Standardgeometrieelementen im Mikrobereich. S. Patzelt; A. Tausendfreund; J. Mehner and S. Simon et.al. Zeitschrift: Technisches Messen (2008), pp. 327–33.
    26. Acceleration of a finite-difference method with general purpose GPUs - Lesson learned. A. Balevic; L. Rockstroh; W. Li; J. Hillebrand; S. Simon; A. Tausendfreund; S. Patzelt and G. Goch. In 2008 8th IEEE International Conference on Computer and Information Technology, 2008, pp. 291–294. DOI: https://doi.org/10.1109/CIT.2008.4594689
    27. A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. Rauf Salimi Khaligh and Martin Radetzki. In Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings, 2008, pp. 37--42. DOI: https://doi.org/10.1109/FDL.2008.4641418
    28. Adaptive Interconnect Models for Transaction-Level Simulation. Rauf Salimi Khaligh and Martin Radetzki. In Languages for Embedded Systems and their Applications - Selected Contributionson Specification, Design, and Verification from FDL’08, September23-25, 2008, Stuttgart, Germany, 2008, pp. 149--165. DOI: https://doi.org/10.1007/978-1-4020-9714-0_10
    29. A data traffic efficient H.264 deblocking IP. Weining Hao and Martin Radetzki. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, 2008, pp. 3430--3433. DOI: https://doi.org/10.1109/ISCAS.2008.4542196
    30. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
    31. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
    32. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
    33. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    34. Accelerating Simulations of Light Scattering Based on Finite-Difference Time-Domain Method with General Purpose GPUs. A. Balevic; L. Rockstroh; A. Tausendfreund; S. Patzelt; G. Goch and S. Simon. In 2008 11th IEEE International Conference on Computational Science and Engineering, 2008, pp. 327–334. DOI: https://doi.org/10.1109/CSE.2008.16
    35. Using Arithmetic Coding for the Reduction of Simulation Data on Massive Parallel GPGPU,. A. Balevic and S. Simon. ParSim (2008), pp. 1–8.
  14. 2007

    1. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. Informacije MIDEM 37, 4(124) (December 2007), pp. 212--219.
    2. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (December 2007), pp. 235--243.
    3. Academic Network for Microelectronic Test Education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean Pierre Van Der Heyden. The International Journal of Engineering Education 23, 6 (November 2007), pp. 1245--1253.
    4. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Juergen Schloeffel and Laurent Souef. In Proceedings of the International Test Conference (ITC’07), Santa Clara, California, USA, 2007, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2007.4437611
    5. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, 2007, pp. 50--58. DOI: https://doi.org/10.1109/DFT.2007.43
    6. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper). Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 3--10.
    7. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
    8. Scan Test Planning for Power Reduction. Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC’07), San Diego, California, USA, 2007, pp. 521--526. DOI: https://doi.org/10.1145/1278480.1278614
    9. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 7--12. DOI: https://doi.org/10.1109/ETS.2007.9
    10. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 91--96. DOI: https://doi.org/10.1109/ETS.2007.10
    11. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. IET Computers & Digital Techniques 1, 3 (May 2007), pp. 180--186. DOI: http://digital-library.theiet.org/content/journals/10.1049/iet-cdt_20060131
    12. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE Workshop on Design and Diagnostics ofElectronic Circuits and Systems (DDECS’07), Krakow, Poland, 2007, pp. 185--190. DOI: https://doi.org/10.1109/DDECS.2007.4295278
    13. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute. Michael E. Imhof; Christian G. Zöllin; Hans-Joachim Wunderlich; Nicolas Mäding and Jens Leenstra. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 69--76.
    14. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    15. Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen. Michael Wedel; Peter Göhner; Jochen Gäng; Bernd Bertsche; Talal Arnaout and Hans-Joachim Wunderlich. In 5. Paderborner Workshop “Entwurf mechatronischer Systeme,” Paderborn, Germany, 2007, pp. 257--272.
    16. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian Zöllin; Andreas Glowatz; Jürgen Schlöffel and Friedrich Hapke. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 61--65.
    17. Synthesis of Irregular Combinational Functions with Large Don’t Care Sets. Valentin Gherman; Hans-Joachim Wunderlich; Rio Mascarenhas; Juergen Schloeffel and Michael Garbers. In Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI’07), Stresa - Lago Maggiore, Italy, 2007, pp. 287--292. DOI: https://doi.org/10.1145/1228784.1228856
    18. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    19. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
    20. Modelling Alternatives for Cycle Approximate Bus TLMs. Martin Radetzki and Rauf Salimi Khaligh. In Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings, 2007, pp. 74--79.
    21. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
    22. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (2. Auflage), Christian Siemers and Axel Sikora (eds.). Fachbuchverlag Leipzig im Carl Hanser Verlag, 2007, pp. 267--290.
    23. Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. Martin Radetzki. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007, 2007, pp. 181--190.
    24. Simulation of Light Scattering from Nanostructured Surfaces. A. Tausendfreund; S. Patzelt; S. Simon and G. Goch. In 8th International Symposium on Measurement Technology and Intelligent Instruments, 2007, pp. 207–210.
    25. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
    26. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
    27. Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. Rauf Salimi Khaligh and Martin Radetzki. In Embedded System Design: Topics, Techniques and Trends, IFIP TC10Working Conference: International Embedded Systems Symposium (IESS),May 30 - June 1, 2007, Irvine, CA, USA, 2007, pp. 313--324. DOI: https://doi.org/10.1007/978-0-387-72258-0_27
    28. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
  15. 2006

    1. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the International Test Conference (ITC’06), Santa Clara, California, USA, 2006, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2006.297695
    2. Structural-based Power-aware Assignment of Don’t Cares for Peak Power Reduction during Scan Testing. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Virazel Arnaud and Hans-Joachim Wunderlich. In Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, 2006, pp. 403--408. DOI: https://doi.org/10.1109/VLSISOC.2006.313222
    3. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme;  DFG-Project – Test and Reliability of Nano-Electronic Systems. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. it - Information Technology 48, 5 (October 2006), pp. 304--311. DOI: https://doi.org/10.1524/itit.2006.48.5.304
    4. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS’06), Tunis, Tunisia, 2006, pp. 359--364. DOI: https://doi.org/10.1109/DTIS.2006.1708693
    5. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. In Proceedings of the 11th European Test Symposium (ETS’06), Southampton, United Kingdom, 2006, pp. 123--130. DOI: https://doi.org/10.1109/ETS.2006.12
    6. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zöllin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 101--103.
    7. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 95--100.
    8. Software-Based Self-Test of Processors under Power Constraints. Jun Zhou and Hans-Joachim Wunderlich. In Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE’06), Munich, Germany, 2006, pp. 430--436. DOI: https://doi.org/10.1109/DATE.2006.243798
    9. X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilian Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14, 2 (February 2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    10. Some Common Aspects of Design Validation, Debug and Diagnosis. Talal Arnaout; Günter Bartsch and Hans-Joachim Wunderlich. In Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA’06), Kuala Lumpur, Malaysia, 2006, pp. 3--10. DOI: https://doi.org/10.1109/DELTA.2006.79
    11. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
    12. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
    13. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
    14. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
    15. SystemC TLM Transaction Modelling and Dispatch for Active Object. Martin Radetzki. In Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings, 2006, pp. 203--209.
    16. Simulation of Light Scattering from Surfaces Containing Spherical and Elliptical Nanoparticles. A. Tausendfreund; D. Mader; S. Simon; S. Patzelt and G. Goch. In Proceedings of SPIE 6195, 2006, pp. 1–13.
    17. Low Power Synthesizable Register Files for Processor and IP Cores. M. Müller; S. Simon; H. Gryska; A. Wortmann and S. Buch. 2006.
    18. Simulation of Light Scattering for Surfaces with Statistically Distributed Subwavelength Cavities. A. Tausendfreund; S. Patzelt; D. Mader; S. Simon and G. Goch. In Proceedings of SPIE 6195, 2006, pp. 1–12.
    19. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
    20. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    21. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
    22. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
    23. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
  16. 2005

    1. Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. Jun Zhou and Hans-Joachim Wunderlich. In INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 2005, pp. 441--441.
    2. On the Reliability Evaluation of SRAM-based FPGA Designs. Oliver Héron; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, 2005, pp. 403--408. DOI: https://doi.org/10.1109/FPL.2005.1515755
    3. Development of an Audio Player as System-on-a-Chip using an Open Source Platform. Kiatisevi Pattara; Luis Azuara; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’05), Kobe, Japan, 2005, pp. 2935--2938. DOI: https://doi.org/10.1109/ISCAS.2005.1465242
    4. From Embedded Test to Embedded Diagnosis. Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE European Test Sypmposium (ETS’05), Tallinn, Estonia, 2005, pp. 216--221. DOI: https://doi.org/10.1109/ETS.2005.26
    5. Implementing a Scheme for External Deterministic Self-Test. Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS’05), Palm Springs, California, USA, 2005, pp. 101--106. DOI: https://doi.org/10.1109/VTS.2005.50
    6. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
    7. Frühe Zuverlässigkeitsanalyse mechatronischer Systeme;  Early Reliability Analysis for Mechatronic Systems. Patrick Jäger; Bernd Bertsche; Talal Arnout and Hans-Joachim Wunderlich. In 22. VDI Tagung Technische Zuverlässigkeit (TTZ’05), Stuttgart, Germany, 2005, pp. 39--56.
    8. DLBIST for Delay Testing. Michael Garbers; Jürgen Schlöffel; Valentin Gherman and Hans-Joachim Wunderlich. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 39--43.
    9. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
    10. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
    11. Simulation of Light Scattering from Nanosurfaces based on Frequency Scaled Measurements. D. Mader; A. Tausendfreund; S. Simon; S. Patzelt and G. Goch. Nanoengineering Symposium (2005), pp. 1–5.
    12. Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen. M. Müller and S. Simon. GI Jahrestagung 1, (2005), pp. 457.
    13. Method for Light Scattering from Nanostructures. D. Mader; A. Tausendfreund; S. Simon; S. Patzelt; G. Goch and A. Computation. Nanoengineering Symposium (2005), pp. 1–5.
    14. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
    15. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
    16. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
    17. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
    18. Power reduction of ASIPs by distributing the workload on several ASIP-instances. V. Kalyanaraman; M. Mueller; S. Simon; M. Steinert and H. Gryska. In Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2005, pp. III/457-III/460 vol. 3. DOI: https://doi.org/10.1109/ECCTD.2005.1523159
    19. Data Scaling of Two’s Complement Data Representation for Low Power SoC Architectures. M. Müller; S. Simon; V. Kalyanaraman; M. Steinert and H. Gryska. 2005, pp. 1–6.
    20. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
    21. A power dissipation comparison of ALU-architectures for ASIPs. V. Kalyanaraman; M. Mueller; S. Simon; M. Steinert and H. Gryska. In Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2005, pp. II/217-II/220 vol. 2. DOI: https://doi.org/10.1109/ECCTD.2005.1523032
  17. 2004

    1. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In Proceedings of the 35th IEEE International Test Conference (ITC’04), Charlotte, New York, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    2. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke and Michael Garbers. In Proceedings of the 35th IEEE International Test Conference (ITC’04), Charlotte, New York, USA, 2004, pp. 48--56. DOI: https://doi.org/10.1109/TEST.2004.1386936
    3. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke and Michael Wittke. In Proceedings of the 9th IEEE European Test Sypmposium (ETS’04), Ajaccio, Corsica, France, 2004, pp. 327--332.
    4. EuNICE-Test: European network for test education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’04), Tatranska Lomnica, Slovakia, 2004.
    5. Reliability Considerations for Mechatronic Systems on the Basis of a State Model. Peter Göhner; Eduard Zimmer; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 17th International Conference on Architecture of Computing Systems (ARCS’04) - Organic and Pervasive Computing, Augsburg, Germany, 2004, pp. 106--112.
    6. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
    7. Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE International Workshop on Electronic Design, Test and Applications (DELTA’04), Perth, Australia, 2004, pp. 135--140.
    8. Impact of Test Point Insertion on Silicon Area and Timing during Layout. Harald Vranken; Ferry Syafei Sapei and Hans-Joachim Wunderlich. In Proceedings of the 7th Conference on Design, Automation and Test in Europe (DATE’04), Paris, France, 2004, pp. 20810--20815. DOI: https://doi.org/10.1109/DATE.2004.1268981
    9. Masking X-Responses During Deterministic Self-Test. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Garbers and Jürgen Schlöffel. In 16th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’04), Dresden, Germany, 2004, pp. 13--19.
    10. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
    11. IPQ: IP Qualification for Efficient System Design. Hans-Jürgen Brand; Steffen Rülke and Martin Radetzki. In 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, 2004, pp. 478--482. DOI: https://doi.org/10.1109/ISQED.2004.1283719
    12. A high-speed transceiver architecture implementable as synthesizable IP core. A. Wortmann; S. Simon and M. Muller. In Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 46- 51 Vol.3. DOI: https://doi.org/10.1109/DATE.2004.1269197
    13. An instruction set for the efficient implementation of the CORDIC algorithm. S. Simon; M. Muller; H. Gryska; A. Wortmann and S. Buch. In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004, pp. II–357. DOI: https://doi.org/10.1109/ISCAS.2004.1329282
    14. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
    15. Intelligent IP retrieval driven by application requirements. Martin Schaaf; Andrea Freßmann; Rainer Maximini; Ralph Bergmann; Alexander Tartakovski and Martin Radetzki. Integration 37, 4 (2004), pp. 253--287. DOI: https://doi.org/10.1016/j.vlsi.2004.01.002
    16. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
    17. Measurement of IP Qualification Costs and Benefits. Andreas Vörg; Martin Radetzki and Wolfgang Rosenstiel. In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, 2004, pp. 996--1001. DOI: https://doi.org/10.1109/DATE.2004.1269023
    18. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
    19. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
    20. The impact of clock gating schemes on the power dissipation of synthesizable register files. M. Mueller; A. Wortmann; S. Simon; M. Kugel and T. Schoenauer. In 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004, pp. II–609. DOI: https://doi.org/10.1109/ISCAS.2004.1329345
    21. Register Isolation for Synthesizable Register Files. M. Müller; A. Wortmann; D. Mader and S. Simon. 14th Int. Workshop, Power and Timing Modeling Optimization and Simulation, PATMOS (2004), pp. 228–237.
  18. 2003

    1. Test Engineering Education in Europe: the EuNICE-Test Project. Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Anton Biasizzo; Frank Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean-Pierre Van der Heyden. In Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE’03), Anaheim, California, USA, 2003, pp. 85--86. DOI: https://doi.org/10.1109/MSE.2003.1205266
    2. Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level. Yves Bertrand; Marie-Lise Flottes; Nicoleta Pricopi and Hans-Joachim Wunderlich. In 15th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’03), Timmendorfer Strand, Germany, 2003.
    3. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25--44. DOI: https://doi.org/10.1016/S0167-9260(03)00003-8
    4. Static timing analysis with rigorous exploitation of setup time margins. A. Wortmann; S. Simon; W. Bergholz; M. Muller and D. Mader. In 2003 46th Midwest Symposium on Circuits and Systems, 2003, pp. 1396- 1399 Vol. 3. DOI: https://doi.org/10.1109/MWSCAS.2003.1562556
    5. A power efficient register file architecture using master latch sharing. M. Wroblewski; M. Mueller; A. Wortmann; S. Simon; W. Pieper and J.A. Nossek. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ’03., 2003, pp. V–V. DOI: https://doi.org/10.1109/ISCAS.2003.1206291
    6. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
    7. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, 2003, pp. 11184--11185. DOI: https://doi.org/10.1109/DATE.2003.10051
    8. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. Jonathan Bradford; Hartmut Delong; Ilia Polian and Bernd Becker. J. Electronic Testing 19, 4 (2003), pp. 387--395. DOI: https://doi.org/10.1023/A:1024635824944
    9. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423
    10. sciPROVE: C++ Based Verification Environment for IP and SoC Design1. U. Badelt; H. Kühl and Martin Radetzki. In Forum on specification and Design Languages, FDL 2003, September 23-26, 2003, Frankfurt, Germany, Proceedings, 2003, pp. 617--627.
    11. Reducing ATE Cost in System-on-Chip Test. Ilia Polian and Bernd Becker. In IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 2003, pp. 337--342.
    12. On non-standard fault models for logic digital circuits. Ilia Polian. In Ausgezeichnete Informatikdissertationen 2003, 2003, pp. 169--178.
    13. Simulating Resistive Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 1051--1059. DOI: https://doi.org/10.1109/TEST.2003.1271093
    14. et. al., An IP Based Design Flow with ASIPs for the Design and Implementation of Digital Filters. S. Simon; H. Gryska and M. Müller. IP Based SoC Design, Grenoble (2003), pp. 1–6.
  19. 2002

    1. Adapting an SoC to ATE Concurrent Test Capabilities. Rainer Dorsch; Ramón Huerta Rivera; Hans-Joachim Wunderlich and Martin Fischer. In Proceedings of the 33rd International Test Conference (ITC’02), Baltimore, Maryland, USA, 2002, pp. 1169--1175. DOI: https://doi.org/10.1109/TEST.2002.1041875
    2. Efficient Online and Offline Testing of Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets and Vyacheslav N. Yarmolik. IEEE Transactions on Computers 51, 7 (July 2002), pp. 801--809. DOI: https://doi.org/10.1109/TC.2002.1017700
    3. Combining Deterministic Logic BIST with Test Point Insertion. Harald Vranken; Florian Meister and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW’02), Korfu, Greece, 2002, pp. 105--110. DOI: https://doi.org/10.1109/ETW.2002.1029646
    4. RESPIN++ - Deterministic Embedded Test. Lars Schäfer; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW’02), Korfu, Greece, 2002, pp. 37--44. DOI: https://doi.org/10.1109/ETW.2002.1029637
    5. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (April 2002), pp. 159--170. DOI: https://doi.org/10.1023/A:1014993509806
    6. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (April 2002), pp. 231--240. DOI: https://doi.org/10.1023/A:1014968930415
    7. Power Conscious BIST Approaches. Arnaud Virazel and Hans-Joachim Wunderlich. In 3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, 2002, pp. 128--135.
    8. A Mixed-Mode BIST Scheme Based on Folding Compression. Huaguo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Computer Science and Technology 17, 2 (March 2002), pp. 203–212. DOI: https://doi.org/10.1007/BF02962213
    9. High Defect Coverage with Low Power Test Sequences in a BIST Environment. Patrick Girard; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel and Hans-Joachim Wunderlich. IEEE Design & Test of Computers 19, 5 (2002), pp. 44--52. DOI: https://doi.org/10.1109/MDT.2002.1033791
    10. Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Ilia Polian; Irith Pomeranz and Bernd Becker. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002, pp. 2--14. DOI: https://doi.org/10.1109/ATS.2002.1181677
    11. Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. Ilia Polian; Piet Engelke and Bernd Becker. In 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, 2002, pp. 216--223. DOI: https://doi.org/10.1109/ISMVL.2002.1011092
    12. Low Power Register File Architectures for Application Specific DSPs. M. Müller; A. Wortmann and S. Simon et. al. IEEE International Symp. on Circuits and Systems (2002), pp. 89–92.
    13. Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbeschreibungen (Quality and Quality Assurance of Reusable Circuit Descriptions). Martin Radetzki. it+ti - Informationstechnik und Technische Informatik 44, 2 (2002), pp. 99--102. DOI: https://doi.org/10.1524/itit.2002.44.2.099
    14. Sequential n -Detection Criteria: Keep It Simple. Ilia Polian; Martin Keim; Nicolai Mallig and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 189. DOI: https://doi.org/10.1109/OLT.2002.1030213
    15. Stop & Go BIST. Ilia Polian and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 147--151. DOI: https://doi.org/10.1109/OLT.2002.1030198
    16. A Qualification Platform for Design Reuse. Ralf Seepold; Natividad Mart\’ınez Madrid; Andreas Vörg; Wolfgang Rosenstiel; Martin Radetzki; P. Neumann and J. Haase. In 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, 2002, pp. 75--80. DOI: https://doi.org/10.1109/ISQED.2002.996698
  20. 2001

    1. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (June 2001), pp. 341--349. DOI: https://doi.org/10.1023/A:1012279716236
    2. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (June 2001), pp. 351--362. DOI: https://doi.org/10.1023/A:1012283800306
    3. On Applying the Set Covering Model to Reseeding. Silvia Chiusano; Stefano Di Carlo; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE’01), Munich, Germany, 2001, pp. 156--160. DOI: https://doi.org/10.1109/DATE.2001.915017
    4. Circuit Partitioning for Efficient Logic BIST Synthesis. Alexander Irion; Gundolf Kiefer; Harald Vranken and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE’01), Munich, Germany, 2001, pp. 86--91. DOI: https://doi.org/10.1109/DATE.2001.915005
    5. Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability. Michael Kessler; Gundolf Kiefer; Jens Leenstra; Knut Schünemann; Thomas Schwarz and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 461--469. DOI: https://doi.org/10.1109/TEST.2001.966663
    6. Tailoring ATPG for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 530--537. DOI: https://doi.org/10.1109/TEST.2001.966671
    7. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 894--902. DOI: https://doi.org/10.1109/TEST.2001.966712
    8. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 6th European Test Workshop (ETW’01), Stockholm, Sweden, 2001, pp. 124--132. DOI: https://doi.org/10.1109/ETW.2001.946677
    9. A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. Patrick Girard; Lois Guiller; Christian Landrault; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 19th VLSI Test Symposium (VTS’01), Marina Del Rey, California, USA, 2001, pp. 306--311. DOI: https://doi.org/10.1109/VTS.2001.923454
    10. Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Meißen, Germany, February 19-21, 2001, 2001, pp. 111--120.
    11. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, 2001, pp. 88--93. DOI: https://doi.org/10.1109/VTS.2001.923423
    12. Efficient Pattern-Based Verification of Connections to IP Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001, pp. 443--448. DOI: https://doi.org/10.1109/ATS.2001.990324
  21. 2000

    1. Using Mission Logic for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In 1st IEEE International Workshop on Test Resource Partitioning (TRP’00), Atlantic City, New Jersey, USA, 2000.
    2. Non-Intrusive BIST for Systems-on-a-Chip. Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 644--651. DOI: https://doi.org/10.1109/TEST.2000.894259
    3. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 778--784. DOI: https://doi.org/10.1109/TEST.2000.894274
    4. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 105--114. DOI: https://doi.org/10.1109/TEST.2000.894197
    5. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (June 2000), pp. 169--177. DOI: https://doi.org/10.1023/A:1008374811502
    6. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (June 2000), pp. 203--212. DOI: https://doi.org/10.1023/A:1008383013319
    7. Optimal Hardware Pattern Generation for Functional BIST. Silvia Cataldo; Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 7th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Paris, France, 2000, pp. 292--297. DOI: https://doi.org/10.1109/DATE.2000.840286
    8. Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest. Rainer Dorsch and Hans-Joachim Wunderlich. In 12th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’00), Grassau, Germany, 2000, pp. 1--7.
    9. Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In 7th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 2000.
    10. Synthesis of digital circuits from object oriented specifications. Martin Radetzki. University of Oldenburg, Germany.2000.
    11. Low Power Transf. of Datapath Architectures with cyclic SFGs,. M. Wroblewski; S. Simon and J. A. Nossek. IEEE International Symp. on Circuits and Systems, ISCAS (2000), pp. 597–600.
  22. 1999

    1. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE International Test Conference (ITC’99), Atlantic City, New Jersey, USA, 1999, pp. 77--84. DOI: https://doi.org/10.1109/TEST.1999.805616
    2. Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms. Vyacheslav N. Yarmolik; I.V. Bykov; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 3rd European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999, pp. 339--350. DOI: https://doi.org/10.1007/3-540-48254-7_23
    3. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE European Test Workshop (ETW’99), Constance, Germany, 1999, pp. 110--117. DOI: https://doi.org/10.1109/ETW.1999.804415
    4. Error Detecting Refreshment for Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander Ivaniuk; Yuri Klimets and Vyacheslav N. Yarmolik. In Proceedings of the 17th IEEE VLSI Test Symposium (VTS’99), Dana Point, California, USA, 1999, pp. 384--390. DOI: https://doi.org/10.1109/VTEST.1999.766693
    5. Symmetric Transparent BIST for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702--707. DOI: https://doi.org/10.1109/DATE.1999.761206
    6. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 14, 1–2 (February 1999), pp. 85--93. DOI: https://doi.org/10.1023/A:1008353423305
    7. Exploiting Symmetries to Speed Up Transparent BIST. Sybille Hellebrand; Hans-Joachim Wunderlich and Vyacheslav N. Yarmolik. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 12--15.
    8. Minimum Scan Insertion for Generating Pipeline-Structured Modules. Gundolf Kiefer and Hans-Joachim Wunderlich. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 30--33.
    9. Data Type Analysis for Hardware Synthesis from Object-Oriented Models. Martin Radetzki; Ansgar Stammermann; Wolfram Putzke-Röming and Wolfgang Nebel. In 1999 Design, Automation and Test in Europe (DATE ’99), 9-12 March 1999, Munich, Germany, 1999, pp. 491. DOI: https://doi.org/10.1109/DATE.1999.761171
    10. Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. P. Rieder; S. Simon and C. Schimpfle. In Proceedings of the International Symposium on Circuits and Systems, 1999.
    11. Low Power Datapath Design Using Transf. Similar to Temporal Localization of SFGs. S. Simon and M. Wroblewski. 1999, pp. 59–61.
    12. High-level circuit modeling for power estimation. C.V. Schimpfle; S. Simon and J.A. Nossek. In ICECS’99. Proceedings of ICECS ’99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, pp. 807–810 vol.2. DOI: https://doi.org/10.1109/ICECS.1999.813231
    13. Device level based cell modeling for fast power estimation. C.V. Schimpfle; S. Simon and J.A. Nossek. In 1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, pp. 90–93 vol.1. DOI: https://doi.org/10.1109/ISCAS.1999.777812
  23. 1998

    1. BIST for Systems-on-a-Chip. Hans-Joachim Wunderlich. Integration, the VLSI Journal - Special issue on VLSI testing 26, 1–2 (1998), pp. 55--78. DOI: https://doi.org/10.1016/S0167-9260(98)00021-2
    2. Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Madhavi Karkala; Nur A. Touba and Hans-Joachim Wunderlich. In Proceedings of the 7th Asian Test Symposium (ATS’98), Singapore, 1998, pp. 492--499. DOI: https://doi.org/10.1109/ATS.1998.741662
    3. Accumulator Based Deterministic BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC’98), Washington, DC, USA, 1998, pp. 412--421. DOI: https://doi.org/10.1109/TEST.1998.743181
    4. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC’98), Washington, DC, USA, 1998, pp. 1057--1064. DOI: https://doi.org/10.1109/TEST.1998.743304
    5. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. Vyacheslav N. Yarmolik; Yuri Klimets; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the Design and Diagnostics of Electronic Circuits and Systems (DDECS’98), Szczyrk, Poland, 1998, pp. 27--33.
    6. Hardware-Optimal Test Register Insertion. Albrecht P. Stroele and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 17, 6 (June 1998), pp. 531--539. DOI: https://doi.org/10.1109/43.703833
    7. Low-Power Serial Built-In Self Test. Andre Hertwig and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’98), Sitges, Barcelona, Spain, 1998, pp. 51.
    8. Fast Self-Recovering Controllers. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE VLSI Test Symposium (VTS’98), Monterey, California, USA, 1998, pp. 296--302. DOI: https://doi.org/10.1109/VTEST.1998.670883
    9. Efficient Consistency Checking for Embedded Memories. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
    10. Pattern Selection for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
    11. Scan Path Design for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’98), Herrenberg, Germany, 1998.
    12. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173--179. DOI: https://doi.org/10.1109/DATE.1998.655853
    13. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. Journal of Electronic Testing: Theory and Applications (JETTA) 12, 1–2 (February 1998), pp. 127--138. DOI: https://doi.org/10.1023/A:1008294125692
    14. Synthesizing Fast, Online-Testable Control Units. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. IEEE Design & Test of Computers 15, 4 (1998), pp. 36--41. DOI: https://doi.org/10.1109/54.735925
    15. ATM Cell Modelling using Objective VHDL. Alberto Allara; Massimo Bombana; Patrizia Cavalloro; Wolfgang Nebel; Wolfram Putzke-Röming and Martin Radetzki. In Proceedings of the ASP-DAC ’98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, 1998, pp. 261--264. DOI: https://doi.org/10.1109/ASPDAC.1998.669461
    16. Übersetzung von Objektorientiertem VHDL nach Standard VHDL. Martin Radetzki; Wolfram Putzke-Röming and Wolfgang Nebel. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Paderborn, Germany, March 9-11, 1998, 1998, pp. 21--29.
    17. A Unified Approach to Object-Oriented VHDL. Martin Radetzki; Wolfram Putzke-Röming and Wolfgang Nebel. J. Inf. Sci. Eng. 14, 3 (1998), pp. 523--545.
    18. A Flexible Message Passing Mechanism for Objective VHDL. Wolfram Putzke-Röming; Martin Radetzki and Wolfgang Nebel. In 1998 Design, Automation and Test in Europe (DATE ’98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, 1998, pp. 242--249. DOI: https://doi.org/10.1109/DATE.1998.655863
    19. Test and Testable Design. Hans-Joachim Wunderlich. In Architecture Design and Validation Methods, Egon Börger (ed.). Springer-Verlag Heidelberg, 1998, pp. 141--190.
  24. 1997

    1. Using BIST Control for Pattern Generation. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 28th IEEE International Test Conference (ITC’97), Washington, DC, USA, 1997, pp. 347--355. DOI: https://doi.org/10.1109/TEST.1997.639636
    2. Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
    3. STARBIST: Scan Autocorrelated Random Pattern Generation. Kun-Han Tsai; Sybille Hellebrand; Janusz Rajski and Malgorzata Marek-Sadowska. In Proceedings of the 34th ACM/IEEE Design Automation Conference (DAC’97), Anaheim, California, USA, 1997, pp. 472--477. DOI: https://doi.org/10.1109/DAC.1997.597194
    4. Fast Controllers for Data Dominated Applications. Andre Hertwig and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC’97), Paris, France, 1997, pp. 84--89. DOI: https://doi.org/10.1109/EDTC.1997.582337
    5. Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand. Gundolf Kiefer and Hans-Joachim Wunderlich. In 9th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’97), Bremen, Germany, 1997, pp. 49--52.
    6. Low power CORDIC implementation using redundant number representation. C.V. Schimpfle; S. Simon and J.A. Nossek. In Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997, pp. 154–161. DOI: https://doi.org/10.1109/ASAP.1997.606822
    7. Optimal placement of registers in data paths for low power design. C.V. Schimpfle; S. Simon and J.A. Nossek. In 1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, pp. 2160–2163 vol.3. DOI: https://doi.org/10.1109/ISCAS.1997.621598
    8. Entwurf von Datenpfaden in schnellen integrierten Schaltungen. S. Simon. Dissertation (1997), pp. 141.
    9. Retiming of latches for power reduction of DSP designs. S. Simon; C.V. Schimpfle; M. Wroblewski and J.A. Nossek. In 1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, pp. 2168–2171 vol.3. DOI: https://doi.org/10.1109/ISCAS.1997.621600
    10. Optimizing Sequential Circuits for Minimum Glitching Activity. C. Schimpfle; S. Simon and J. A. Nossek. 1997, pp. 1–5.
    11. Estimation and Reduction of Spurious Switching Activities in Static CMOS Circuits. C. Schimpfle and S. Simon. AEÜ Int. Journal of Electronics and Communications 51, (1997), pp. 290.
  25. 1996

    1. Bit-Flipping BIST. Hans-Joachim Wunderlich and Gundolf Kiefer. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’96), San Jose, California, USA, 1996, pp. 337--343. DOI: https://doi.org/10.1109/ICCAD.1996.569803
    2. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In Proceedings of the 27th IEEE International Test Conference (ITC’96), Washington, DC, USA, 1996, pp. 195--204. DOI: https://doi.org/10.1109/TEST.1996.556962
    3. Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead. Hans-Joachim Wunderlich and Gundolf Kiefer. In IEEE European Test Workshop, Montpellier, France, 1996, pp. 60--64.
    4. Using Embedded Processors for BIST. Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1996.
    5. Deterministic Pattern Generation for Weighted Random Pattern Testing. Birgit Reeb and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC’96), Paris, France, 1996, pp. 30--36. DOI: https://doi.org/10.1109/EDTC.1996.494124
    6. Built-in self test architectures for multistage interconnection networks. E. Bernard; S. Simon and J.A. Nossek. In Proceedings ED&TC European Design and Test Conference, 1996, pp. 176–180. DOI: https://doi.org/10.1109/EDTC.1996.494145
    7. CORDIC-based architectures for the efficient implementation of discrete wavelet transforms. S. Simon; P. Rieder; C. Schimpfle and J.A. Nossek. In 1996 IEEE International Symposium on Circuits and Systems (ISCAS), 1996, pp. 77–80 vol.4. DOI: https://doi.org/10.1109/ISCAS.1996.541948
    8. Development of a Telephone Answering Machine in a Lab - FPGAs in Education. Guido Schumacher; Bernhard Josko; Gerhard Wagner and Martin Radetzki. In Field-Programmable Logic, Smart Applications, New Paradigms and Compilers,6th International Workshop on Field-Programmable Logic, FPL ’96,Darmstadt, Germany, September 23-25, 1996, Proceedings, 1996, pp. 400--404. DOI: https://doi.org/10.1007/3-540-61730-2_46
    9. Efficient VLSI suited architectures for discrete wavelet transforms. S. Simon; P. Rieder and J.A. Nossek. In VLSI Signal Processing, IX, 1996, pp. 388–397. DOI: https://doi.org/10.1109/VLSISP.1996.558371
  26. 1995

    1. Test Register Insertion with Minimum Hardware Cost. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’95), San Jose, California, USA, 1995, pp. 95--101. DOI: https://doi.org/10.1109/ICCAD.1995.479998
    2. Pattern Generation for a Deterministic BIST Scheme. Sybille Hellebrand; Birgit Reeb; Steffen Tarnick and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’95), San Jose, California, USA, 1995, pp. 88--94. DOI: https://doi.org/10.1109/ICCAD.1995.479997
    3. Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors. Hans-Joachim Wunderlich; M. Herzog; Joan Figueras; J.A. Carrasco and A. Calderón. In Proceedings of the European Design & Test Conference (ED&TC’95), Paris, France, 1995, pp. 573--580. DOI: https://doi.org/10.1109/EDTC.1995.470342
    4. Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest. Olaf Stern and Hans-Joachim and Wunderlich. In 7th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’95), Hannover, Germany, 1995.
    5. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. Sybille Hellebrand; Janusz Rajski; Steffen Tarnick; Srikanth Venkataraman and Bernard Courtois. IEEE Transactions on Computers 44, 2 (February 1995), pp. 223--233. DOI: https://doi.org/10.1109/12.364534
    6. Method Retiming Algorithm for Digital Circuits with Acyclic Circuit Graphs. S. Simon; J. Hofner and J. A. Nossek. In European Conference on Circuit Theory and Design, 1995, pp. 1–5.
    7. Retiming of circuits containing multiplexers. S. Simon; J. Hofner and J.A. Nossek. In 1995 IEEE International Symposium on Circuits and Systems (ISCAS), 1995, pp. 1736–1739 vol.3. DOI: https://doi.org/10.1109/ISCAS.1995.523748
    8. Retiming of synchronous circuits with variable topology. S. Simon; R. Bucher and J.A. Nossek. In Proceedings of the 8th International Conference on VLSI Design, 1995, pp. 130–134. DOI: https://doi.org/10.1109/ICVD.1995.512091
  27. 1994

    1. A Unified Method for Assembling Global Test Schedules. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 3rd Asian Test Symposium (ATS’94), Nara, Japan, 1994, pp. 268--273. DOI: https://doi.org/10.1109/ATS.1994.367220
    2. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), San Jose, California, USA, 1994, pp. 110--116. DOI: https://doi.org/10.1109/ICCAD.1994.629752
    3. Simulation Results of an Efficient Defect Analysis Procedure. Olaf Stern and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC’94), Washington, DC, USA, 1994, pp. 729--738. DOI: https://doi.org/10.1109/TEST.1994.528019
    4. Configuring Flip-Flops to BIST Registers. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC’94), Washington, DC, USA, 1994, pp. 939--948. DOI: https://doi.org/10.1109/TEST.1994.528043
    5. Synthese schneller selbsttestbarer Steuerwerke. Sybille Hellebrand and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 3--11.
    6. Testsynthese für Datenpfade. Albrecht P. Ströle and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 162--171.
    7. Synthesis for Testability - the ARCHIMEDES Approach. Sybille Hellebrand; J. P. Teixeira and Hans-Joachim and Wunderlich. In 1st IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1994.
    8. Ein Verfahren zur testfreundlichen Steuerwerkssynthese. Sybille Hellebrand and Hans-Joachim and Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    9. Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. Srikanth Venkataraman; Janusz and Rajski; Sybille and Hellebrand and Steffen and Tarnick. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    10. Analyse und Simulation realistischer Fehler. Olaf Stern; Wu and Hans-Joachim Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    11. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the European Design Automation Conference (EDAC/ETC/EuroAsic’94), Paris, France, 1994, pp. 580--585. DOI: https://doi.org/10.1109/EDTC.1994.326815
    12. A new retiming algorithm for circuit design. S. Simon; E. Bernard; M. Sauer and J.A. Nossek. In Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS ’94, 1994, pp. 35–38 vol.4. DOI: https://doi.org/10.1109/ISCAS.1994.409190
  28. 1993

    1. An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers. Srikanth Venkataraman; Janusz Rajski; Sybille Hellebrand and Steffen Tarnick. In Proceedings of the ACM/IEEE International Conference on CAD-93 (ICCAD’93), Santa Clara, California, USA, 1993, pp. 572--577. DOI: https://doi.org/10.1109/ICCAD.1993.580117
    2. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support,” Montpellier, France, 1993.
    3. Effiziente Erzeugung deterministischer Muster im Selbsttest. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’93), Holzhau, Germany, 1993.
  29. 1992

    1. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In Proceedings of the 23rd IEEE International Test Conference (ITC’92), Baltimore, Maryland, USA, 1992, pp. 120--129. DOI: https://doi.org/10.1109/TEST.1992.527812
    2. Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In Workshop on New Directions for Testing, Montreal, Canada, 1992.
    3. Generation of Test Patterns through Reseeding of Multiple-Polynomial LFSRs. Sybille Hellebrand; Steffen Tarnick; Janusz Rajski and Bernard Courtois. In IEEE Design for Testability Workshop, Vail, Colorado, USA, 1992.
    4. Efficient Test Set Evaluation. Hans-Joachim Wunderlich and M. Warnecke. In Proceedings of the 3rd European Conference on Design Automation (EDAC’92), Brussels, Belgium, 1992, pp. 428--433. DOI: https://doi.org/10.1109/EDAC.1992.205970
    5. Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen. Olaf Stern and Hans-Joachim Wunderlich. In 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, 1992, pp. 117--122. DOI: https://doi.org/10.18419/opus-7903
    6. Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich and Michael H. Schulz. Informatik-Spektrum 15, 1 (March 1992), pp. 23--32. DOI: https://doi.org/10.18419/opus-7897
    7. Optimized Synthesis Techniques for Testable Sequential Circuits. Bernhard Eschermann and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, 3 (March 1992), pp. 301--312. DOI: https://doi.org/10.1109/43.124417
    8. The Pseudoexhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, 1 (January 1992), pp. 26--33. DOI: https://doi.org/10.1109/43.108616
  30. 1991

    1. A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. Thomas Kropf and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE International Test Conference (ITC’91), Nashville, Tennessee, USA, 1991, pp. 57--66. DOI: https://doi.org/10.1109/TEST.1991.519494
    2. Emulation of Scan Paths in Sequential Circuit Synthesis. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 5th International GI/ITG/GMA Conference on Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment, Nürnberg, Germany, 1991, pp. 136--147. DOI: https://doi.org/10.18419/opus-7904
    3. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle and Hans-Joachim Wunderlich. IEEE Journal of Solid-State Circuits 26, 7 (July 1991), pp. 1056--1063. DOI: https://doi.org/10.1109/4.92026
    4. Signature Analysis and Test Scheduling for Self-Testable Circuits. Albrecht P. Ströle and Hans-Joachim Wunderlich. In Proceedings of the 21st International Symposium on Fault-Tolerant Computing (FTCS-21), Montreal, Canada, 1991, pp. 96--103. DOI: https://doi.org/10.1109/FTCS.1991.146640
    5. Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures. Hans-Joachim Wunderlich and Albrecht P. Ströle. In Proceedings of the IEEE International Sympoisum on Circuits and Systems (ISCAS’91), Singapur, 1991, pp. 1881--1884. DOI: https://doi.org/10.1109/ISCAS.1991.176774
    6. A Unified Approach for the Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC’91), San Francisco, California, USA, 1991, pp. 372--377. DOI: https://doi.org/10.1145/127601.127697
    7. Parallel Self-Test and the Synthesis of Control Units. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 2nd European Test Conference (ETC’91), Munich, Germany, 1991, pp. 73--82. DOI: https://doi.org/10.18419/opus-7920
    8. Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.1991.
    9. Synthese vollständig testbarer Schaltungen. Sybille Hellebrand (Ed.). VDI Verlag Düsseldorf.1991.
  31. 1990

    1. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 16th European Solid-State Circuits Conference (ESSCIRC’90), Grenoble, France, 1990, pp. 101--104. DOI: https://doi.org/10.18419/opus-7921
    2. Generating Pseudo-Exhaustive Vectors for External Testing. Sybille Hellebrand; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 21st IEEE International Test Conference (ITC’90), Washington, DC, USA, 1990, pp. 670--679. DOI: https://doi.org/10.1109/TEST.1990.114082
    3. Error Masking in Self-Testable Circuits. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International Test Conference (ITC’90), Washington, DC, USA, 1990, pp. 544--552. DOI: https://doi.org/10.1109/TEST.1990.114066
  32. 2016

    1. Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS’16), Amsterdam, The Netherlands, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
    2. Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS’16), Foz do Iguaçu, Brazil, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
    3. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
  33. 1990

    1. Optimized Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 20th International Symposium on Fault-Tolerant Computing (FTCS-20), Newcastle Upon Tyne, United Kingdom, 1990, pp. 390--397. DOI: https://doi.org/10.1109/FTCS.1990.89393
    2. An Analytical Approach to the Partial Scan Problem. Arno Kunzmann and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 1, 2 (June 1990), pp. 163--174. DOI: https://doi.org/10.1007/BF00137392
    3. Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 9, 6 (June 1990), pp. 584--593. DOI: https://doi.org/10.1109/43.55187
    4. The Effectiveness of Different Test Sets for PLAs. Peter C. Maxwell and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 628--632. DOI: https://doi.org/10.1109/EDAC.1990.136722
    5. A Synthesis Approach to Reduce Scan Design Overhead. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 671. DOI: https://doi.org/10.18419/opus-7927
    6. Tools and Devices Supporting the Pseudo-Exhaustive Test. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 13--17. DOI: https://doi.org/10.1109/EDAC.1990.136612
    7. Methoden der Testvorbereitung zum IC-Entwurf. Martin H. Schulz and Hans-Joachim Wunderlich. Mikroelektronik 4, 3 (1990), pp. 112--115. DOI: https://doi.org/10.18419/opus-7919
  34. 1989

    1. Methoden der Testvorbereitung. Hans-Joachim Wunderlich and Martin H. Schulz. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 55--62. DOI: https://doi.org/10.18419/opus-7932
    2. Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen. F. Kesel and Hans-Joachim Wunderlich. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 63--68. DOI: https://doi.org/10.18419/opus-7933
    3. The Pseudo-Exhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 20th IEEE International Test Conference (ITC’89), Washington, DC, USA, 1989, pp. 19--27. DOI: https://doi.org/10.1109/TEST.1989.82273
    4. The Design of Random-Testable Sequential Circuits. Hans-Joachim Wunderlich. In Proceedings of the 19th International Symposium on Fault-Tolerant Computing (FTCS-19), Chicago, Illinois, USA, 1989, pp. 110--117. DOI: https://doi.org/10.1109/FTCS.1989.105552
    5. The Synthesis of Self-Test Control Logic. Oliver F. Haberl and Hans-Joachim Wunderlich. In Proceedings of the CompEuro ’89., “VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks,” Hamburg, Germany, 1989, pp. 5/134--5/136. DOI: https://doi.org/10.1109/CMPEUR.1989.93499
    6. Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern. Frank Kesel and Hans-Joachim Wunderlich. In GMD Berichte, 4. E.I.S.-Workshop, Bonn, Germany, 1989, pp. 75--84. DOI: https://doi.org/10.18419/opus-7936
  35. 1988

    1. Automatisierung des Entwurfs vollständig testbarer Schaltungen. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 18. GI Jahrestagung II, Hamburg, Germany, 1988, pp. 145--159. DOI: https://doi.org/10.1007/978-3-642-74135-7_10
    2. Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE International Test Conference (ITC’88). New Frontiers in Testing, International, Washington, DC, USA, 1988, pp. 236--244. DOI: https://doi.org/10.1109/TEST.1988.207808
    3. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 18th International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, 1988, pp. 36--41. DOI: https://doi.org/10.1109/FTCS.1988.5294
    4. Weighted Random Patterns with Multiple Distributions. Hans-Joachim Wunderlich. In Proceedings of the 11th International Conference on Fault Tolerant Systems and Diagnostics, Suhl, German Democratic Republic, 1988, pp. 88--93. DOI: https://doi.org/10.18419/opus-7941
    5. Output-maximal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1988, pp. 1011--1020. DOI: https://doi.org/10.1080/00207728808547182
  36. 1987

    1. Integrated Tools for Automatic Design for Testability. D. Schmid; Hans-Joachim Wunderlich; F. Feldbusch; Sybille Hellebrand; J. Holzinger and Arno Kunzmann. In Proceedings of the IFIP WG 10.2 Workshop on Tool Integration and Design Environments, Paderborn, Germany, 1987, pp. 233--258. DOI: https://doi.org/10.18419/opus-7942
    2. The Random Pattern Testability of Programmable Logic Arrays. Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Computer Design (ICCD’87), Port Chester, New York, USA, 1987, pp. 682--685. DOI: https://doi.org/10.18419/opus-7944
    3. Self Test Using Unequiprobable Random Patterns. Hans-Joachim Wunderlich. In Proceedings of the 17th International Symposium on Fault-Tolerant Computing (FTCS-17), Pittsburgh, Pennsylvania, USA, 1987, pp. 258--263. DOI: https://doi.org/10.18419/opus-7946
    4. On Computing Optimized Input Probabilities for Random Tests. Hans-Joachim Wunderlich. In Proceedings of the 24th ACM/IEEE Design Automation Conference (DAC’87), Miami Beach, Florida, USA, 1987, pp. 392--398. DOI: https://doi.org/10.1145/37888.37947
    5. Probabilistische Verfahren für den Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich (Ed.). Springer-Verlag Heidelberg.1987.
  37. 1986

    1. The Integration of Test and High Level Synthesis in a General Design Environment. D. Schmid; R. Camposano; Arno Kunzmann; Wolfgang Rosenstiel and Hans-Joachim Wunderlich. In Proceedings of the Integrated Circuits Technology Conference (ICTC’86), Limerick, Ireland, 1986, pp. 317--331. DOI: https://doi.org/10.18419/opus-7947
    2. On Fault Modeling for Dynamic MOS Circuits. Hans-Joachim Wunderlich and Wolfgang Rosenstiel. In Proceedings of the 23rd ACM/IEEE Design Automation Conference (DAC’86), Las Vegas, Nevada, USA, 1986, pp. 540--546. DOI: https://doi.org/10.1145/318013.318100
  38. 1985

    1. Design Automation of Random Testable Circuits. Arno Kunzmann and Hans-Joachim Wunderlich. In Proceedings of the 11th European Solid-State Circuits Conference (ESSCIRC’85), Toulouse, France, 1985, pp. 277--285. DOI: https://doi.org/10.18419/opus-7949
    2. PROTEST: A Tool for Probabilistic Testability Analysis. Hans-Joachim Wunderlich. In Proceedings of the 22nd ACM/IEEE Design Automation Conference (DAC’85), Las Vegas, Nevada, USA, 1985, pp. 204--211. DOI: https://doi.org/10.1145/317825.317858
  39. 1984

    1. Time-optimal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1984, pp. 513--524. DOI: https://doi.org/10.1080/00207729408926580
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