DIADEM

DIADEM: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

Moderne Herstellungsprozesse und damit produzierte Schaltungen unterliegen starker Variation und sind empfindliche gegenüber äusseren Einflüssen. Dieses Projekt trägt dem Bedarf nach innovativen Diagnoselösungen Rechnung um Entwicklungszeit und -kosten für solche Systeme zu reduzieren.

06.2006 - 05.2009, DFG-Projekt: WU 245/4-1

Zusammenfassung

Ziel des Projekts ist die Entwicklung und Untersuchung innovativer eingebetteter Diagnoseverfahren für integrierte Systeme in Nanometer Technologie. Da hier mit sehr großen Prozeßschwankungen, anfänglich sehr geringen Ausbeuten und einer erhöhten Störanfälligkeit im Betrieb zu rechnen ist, sind effiziente Diagnoseverfahren unabdingbar, um integrierte Systeme mit vertretbaren Kosten schnell zur Marktreife zu bringen und einen stabilen, zuverlässigen Einsatz zu gewährleisten. Dazu müssen mehr als bisher Diagnoseeinrichtungen mit in das System integriert werden ("Built-in Diagnosis") und gegebenenfalls auch Reparaturmöglichkeiten vorgesehen werden ("Built-in Repair").

Im Rahmen des Projekts werden dazu für digitale Systemkomponenten die Grundlagen geschaffen. Startpunkt ist die Auswahl bzw. Entwicklung von geeigneten Fehlermodellen. Darauf aufbauend werden auf Software Seite Algorithmen zur Bestimmung diagnostischer Tests entworfen. Auf Hardware Seite werden die Bausteine für die Diagnoseinfrastruktur auf dem Chip ("Infrastructure IP") entworfen und Module zur Erzeugung der Diagnosestimuli, zur Auswertung der Antworten und zur Analyse von Reparaturmöglichkeiten entwickelt.

Zur Projektseite

Journale und Tagungsberichte

2009
1. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
  Zusammenfassung
  Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process. This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.
  BibTeX
  @inproceedings{KochtHEW2009, abstract = {Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process. This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.}, abteilung = {ra}, address = {Sevilla, Spain}, author = {Kochte, Michael A. and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 14th IEEE European Test Symposium (ETS'09)}, citeseerurl = {IEEE Computer Society Order Number: P3703}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {25--29}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2009.22}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-0-7695-3703-0}, issn = {1530-1877}, language = {English}, location = {Sevilla, Spain}, month = {05}, owner = {Thomas}, pages = {155--160}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{Test Encoding for Extreme Response Compaction}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtHEW2009.pdf}, year = 2009 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtHEW2009.pdf
  DOI
  10.1109/ETS.2009.22
2. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
  Zusammenfassung
  Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process. This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.
  BibTeX
  @inproceedings{KochtHEW2009, abstract = {Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process. This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.}, abteilung = {ra}, address = {Sevilla, Spain}, author = {Kochte, Michael A. and Holst, Stefan and Elm, Melanie and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 14th IEEE European Test Symposium (ETS'09)}, citeseerurl = {IEEE Computer Society Order Number: P3703}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {25--29}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2009.22}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-0-7695-3703-0}, issn = {1530-1877}, language = {English}, location = {Sevilla, Spain}, month = {05}, owner = {Thomas}, pages = {155--160}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{Test Encoding for Extreme Response Compaction}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtHEW2009.pdf}, year = 2009 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/ETS_KochtHEW2009.pdf
  DOI
  10.1109/ETS.2009.22
3. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
  Zusammenfassung
  During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact shows, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.
  BibTeX
  @inproceedings{HolstW2009, abstract = {During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact shows, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.}, abteilung = {ra}, address = {Nice, France}, author = {Holst, Stefan and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09)}, comment = {IEEE Catalog Number: CFP09162-DVD}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {20--24}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/DATE.2009.5090875}, ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090875}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-1-4244-3781-8}, issn = {1530-1591}, language = {English}, location = {Nice, France}, month = {04}, owner = {Thomas}, pages = {1355--1360}, privnote = {IEEE Catalog Number: CFP09162-DVD}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{A Diagnosis Algorithm for Extreme Space Compaction}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/DATE_HolstW2009.pdf}, year = 2009 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/DATE_HolstW2009.pdf
  DOI
  10.1109/DATE.2009.5090875
4. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (August 2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
  Zusammenfassung
  Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for 'Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.
  BibTeX
  @article{HolstW2009a, abstract = {Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for 'Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.}, abteilung = {ra}, author = {Holst, Stefan and Wunderlich, Hans-Joachim}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1007/s10836-009-5109-3}, file = {Article:/fileadmin/rami/files/publications/2009/JETTA_HolstW2009a.pdf}, issn = {0923-8174}, journal = {Journal of Electronic Testing: Theory and Applications (JETTA)}, language = {English}, month = {08}, number = {4-5}, owner = {Thomas}, pages = {259--268}, project = {DIADEM}, publisher = {Springer-Verlag}, title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}}, type = {Artikel in Zeitschrift}, url = {http://dl.acm.org/citation.cfm?id=1644216.1644221}, volume = 25, year = 2009 }
  Link
  http://dl.acm.org/citation.cfm?id=1644216.1644221
  DOI
  10.1007/s10836-009-5109-3
5. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (August 2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
  Zusammenfassung
  Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for 'Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.
  BibTeX
  @article{HolstW2009a, abstract = {Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach is named POINTER for 'Partially Overlapping Impact couNTER' and combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. In addition, even without additional patterns this analysis method provides good resolution for volume diagnosis, too.}, abteilung = {ra}, author = {Holst, Stefan and Wunderlich, Hans-Joachim}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, department = {Universität Stuttgart, Institut für Technische Informatik, Rechnerarchitektur}, doi = {10.1007/s10836-009-5109-3}, file = {Article:/fileadmin/rami/files/publications/2009/JETTA_HolstW2009a.pdf}, issn = {0923-8174}, journal = {Journal of Electronic Testing: Theory and Applications (JETTA)}, language = {English}, month = {08}, number = {4-5}, owner = {Thomas}, pages = {259--268}, project = {DIADEM}, publisher = {Springer-Verlag}, title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}}, type = {Artikel in Zeitschrift}, url = {http://dl.acm.org/citation.cfm?id=1644216.1644221}, volume = 25, year = 2009 }
  Link
  http://dl.acm.org/citation.cfm?id=1644216.1644221
  DOI
  10.1007/s10836-009-5109-3
6. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
  Zusammenfassung
  During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact shows, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.
  BibTeX
  @inproceedings{HolstW2009, abstract = {During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact shows, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.}, abteilung = {ra}, address = {Nice, France}, author = {Holst, Stefan and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE'09)}, comment = {IEEE Catalog Number: CFP09162-DVD}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {20--24}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/DATE.2009.5090875}, ee = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5090875}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-1-4244-3781-8}, issn = {1530-1591}, language = {English}, location = {Nice, France}, month = {04}, owner = {Thomas}, pages = {1355--1360}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{A Diagnosis Algorithm for Extreme Space Compaction}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/DATE_HolstW2009.pdf}, year = 2009 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2009/DATE_HolstW2009.pdf
  DOI
  10.1109/DATE.2009.5090875
2008
1. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
  Zusammenfassung
  Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.
  BibTeX
  @inproceedings{ElmW2008, abstract = {Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.}, abteilung = {ra}, address = {Munich, Germany}, author = {Elm, Melanie and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE'08)}, comment = {IEEE Catalog Number: CFP08162-DVD}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {10--14}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/DATE.2008.4484725}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-3-9810801-3-1}, language = {English}, location = {Munich, Germany}, month = {03}, owner = {Thomas}, pages = {468--473}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{Scan Chain Organization for Embedded Diagnosis}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/DATE_ElmW2008.pdf}, year = 2008 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/DATE_ElmW2008.pdf
  DOI
  10.1109/DATE.2008.4484725
2. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
  Zusammenfassung
  Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.
  BibTeX
  @inproceedings{ElmW2008, abstract = {Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.}, abteilung = {ra}, address = {Munich, Germany}, author = {Elm, Melanie and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE'08)}, comment = {IEEE Catalog Number: CFP08162-DVD}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {10--14}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/DATE.2008.4484725}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-3-9810801-3-1}, language = {English}, location = {Munich, Germany}, month = {03}, owner = {Thomas}, pages = {468--473}, privnote = {IEEE Catalog Number: CFP08162-DVD}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{Scan Chain Organization for Embedded Diagnosis}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/DATE_ElmW2008.pdf}, year = 2008 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2008/DATE_ElmW2008.pdf
  DOI
  10.1109/DATE.2008.4484725
2007
1. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 91--96. DOI: https://doi.org/10.1109/ETS.2007.10
  Zusammenfassung
  An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.
  BibTeX
  @inproceedings{OehleHW2007, abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.}, abteilung = {ra}, address = {Freiburg, Germany}, author = {Öhler, Phillip and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 12th IEEE European Test Symposium (ETS'07)}, comment = {IEEE Computer Society Order Number: P2827}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {20--24}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2007.10}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {0-7695-2827-9}, issn = {1530-1877}, language = {English}, location = {Freiburg, Germany}, month = {05}, owner = {Thomas}, pages = {91--96}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_OehleHW2007.pdf}, year = 2007 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_OehleHW2007.pdf
  DOI
  10.1109/ETS.2007.10
2. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 91--96. DOI: https://doi.org/10.1109/ETS.2007.10
  Zusammenfassung
  An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.
  BibTeX
  @inproceedings{OehleHW2007, abstract = {An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with spare rows and columns (2D redundancy). Although exact algorithms are available for offline repair analysis, they cannot be directly applied on-chip because of the prohibitive storage requirements for failture bitmaps and the complex data structures inherent in the algorithms. Existing heuristics for built-in repair analysis (BIRA) try to circumvent this problem either by very simple search strategies or by restricting the search to smaller local bitmaps. Exact BIRA algorithms work with sub analyzers for each possible repair combination. While a parallel implementation suffers from a high hardware overhead, a serial implementation leads to high test times. The integrated built-in test and repair approach proposed in this paper interleaves test and repair analysis and supports an exact solution without failure bitmap. The search can be implemented with a stack, which is limited by the number of redundant elements. The basic search procedure is combined with an efficient technique to continuously reduce the problem complexity and keep the test and analysis time low.}, abteilung = {ra}, address = {Freiburg, Germany}, author = {Öhler, Phillip and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 12th IEEE European Test Symposium (ETS'07)}, comment = {IEEE Computer Society Order Number: P2827}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {20--24}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2007.10}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {0-7695-2827-9}, issn = {1530-1877}, language = {English}, location = {Freiburg, Germany}, month = {05}, owner = {Thomas}, pages = {91--96}, privnote = {IEEE Computer Society Order Number: P2827}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_OehleHW2007.pdf}, year = 2007 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_OehleHW2007.pdf
  DOI
  10.1109/ETS.2007.10
3. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 7--12. DOI: https://doi.org/10.1109/ETS.2007.9
  Zusammenfassung
  Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circiut, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.
  BibTeX
  @inproceedings{HolstW2007, abstract = {Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies possible faulty regions in a combinational circiut, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.}, abteilung = {ra}, address = {Freiburg, Germany}, author = {Holst, Stefan and Wunderlich, Hans-Joachim}, award = {Best paper award}, booktitle = {Proceedings of the 12th IEEE European Test Symposium (ETS'07)}, comment = {IEEE Computer Society Order Number: P2827 Best paper award: http://www.cad.polito.it/%7Eets08/}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {20--24}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, doi = {10.1109/ETS.2007.9}, ee = {http://www.cad.polito.it/~ets08/}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {0-7695-2827-9}, issn = {1530-1877}, language = {English}, location = {Freiburg, Germany}, month = {05}, owner = {Thomas}, pages = {7--12}, project = {DIADEM}, publisher = {IEEE Computer Society}, title = {{Adaptive Debug and Diagnosis Without Fault Dictionaries}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_HolstW2007.pdf}, year = 2007 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/ETS_HolstW2007.pdf
  DOI
  10.1109/ETS.2007.9
4. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (December 2007), pp. 235--243.
  Zusammenfassung
  Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.
  BibTeX
  @article{WundeEH2007a, abstract = {Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.}, abteilung = {ra}, address = {Ljubljana}, author = {Wunderlich, Hans-Joachim and Elm, Melani and Holst, Stefan}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, file = {Article:/fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf}, issn = {0352-9045}, journal = {Informacije MIDEM}, language = {English}, month = {12}, number = {4(124)}, owner = {Thomas}, pages = {235--243}, project = {DIADEM}, publisher = {MIDEM}, title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip}}, type = {Artikel in Zeitschrift}, url = {http://www.midem-drustvo.si/journal.htm}, volume = 37, year = 2007 }
  Link
  http://www.midem-drustvo.si/journal.htm
5. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (December 2007), pp. 235--243.
  Zusammenfassung
  Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.
  BibTeX
  @article{WundeEH2007a, abstract = {Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.}, abteilung = {ra}, address = {Ljubljana}, author = {Wunderlich, Hans-Joachim and Elm, Melani and Holst, Stefan}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, file = {Article:/fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf}, issn = {0352-9045}, journal = {Informacije MIDEM}, language = {English}, month = {12}, number = {4(124)}, owner = {Thomas}, pages = {235--243}, project = {DIADEM}, publisher = {MIDEM}, title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip}}, type = {Artikel in Zeitschrift}, url = {http://www.midem-drustvo.si/journal.htm}, volume = 37, year = 2007 }
  Link
  http://www.midem-drustvo.si/journal.htm
6. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
  Zusammenfassung
  Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.
  BibTeX
  @inproceedings{WundeEH2007, abstract = {Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.}, abteilung = {ra}, address = {Bled, Slovenia}, author = {Wunderlich, Hans-Joachim and Elm, Melani and Holst, Stefan}, booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07)}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {12--14}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-961-91023-7-4}, language = {English}, location = {Bled, Slovenia}, month = {09}, owner = {Thomas}, pages = {27--36}, project = {DIADEM}, publisher = {MIDEM}, title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf}, year = 2007 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf
7. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
  Zusammenfassung
  Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.
  BibTeX
  @inproceedings{WundeEH2007, abstract = {Rising design complexity and shrinking structures pose new challenges for debug and diagnosis. Finding bugs and defects quickly during the whole life cycle of a product is crucial for time to market, time to volume and improved product quality. Debug of design errors and diagnosis of defects have many common aspects. In this paper we give an overview of state of the art algorithms, which tackle both tasks, and present an adaptive approach to design debug and logic diagnosis. Special design for diagnosis is needed to maintain visibility of internal states and diagnosability of deeply embedded cores. This article discusses current approaches to design for diagnosis to support all debug tasks from first silicon to the system level.}, abteilung = {ra}, address = {Bled, Slovenia}, author = {Wunderlich, Hans-Joachim and Elm, Melani and Holst, Stefan}, booktitle = {Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07)}, cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance}, day = {12--14}, department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur}, institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany}, isbn = {978-961-91023-7-4}, language = {English}, location = {Bled, Slovenia}, month = {09}, owner = {Thomas}, pages = {27--36}, project = {DIADEM}, publisher = {MIDEM}, title = {{Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper)}}, type = {Konferenz-Beitrag}, url = {https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf}, year = 2007 }
  Link
  https://www.iti.uni-stuttgart.de//fileadmin/rami/files/publications/2007/MIDEM_WundeEH2007.pdf

Dieses Bild zeigt Hans-Joachim Wunderlich

DIADEM

DIADEM: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

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Hans-Joachim Wunderlich

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