Incremental Computation of Delay Fault Detection Probability for
Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In
Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI:
https://doi.org/10.1109/ETS.2014.6847805 Zusammenfassung
Large process variations in recent technology nodes
present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay
test generation method must therefore rely on the probability of
detecting a target delay fault with the currently chosen test vector
pairs. However, the huge number of probability evaluations in
practical applications creates a large computational overhead.
To address this issue, this paper presents the first incremental
delay fault detection probability computation algorithm in the
literature, which is suitable for the inner loop of automatic test
pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently
shows a very large speedup and only a small approximation error.BibTeX
Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In
Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI:
https://doi.org/10.1109/ETS.2014.6847796 Zusammenfassung
Defects cluster, and the probability of a multiple
fault is significantly higher than just the product of the single
fault probabilities. While this observation is beneficial for high
yield, it complicates fault diagnosis. Multiple faults will occur
especially often during process learning, yield ramp-up and field
return analysis.
In this paper, a logic diagnosis algorithm is presented which
is robust against multiple faults and which is able to diagnose
multiple faults with high accuracy even on compressed test
responses as they are produced in embedded test and built-in
self-test. The developed solution takes advantage of the linear
properties of a MISR compactor to identify a set of faults likely
to produce the observed faulty signatures. Experimental results
show an improvement in accuracy of up to 22 % over traditional
logic diagnosis solutions suitable for comparable compaction
ratios.BibTeX
Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In
Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI:
https://doi.org/10.1109/ETS.2014.6847796 Zusammenfassung
Defects cluster, and the probability of a multiple
fault is significantly higher than just the product of the single
fault probabilities. While this observation is beneficial for high
yield, it complicates fault diagnosis. Multiple faults will occur
especially often during process learning, yield ramp-up and field
return analysis.
In this paper, a logic diagnosis algorithm is presented which
is robust against multiple faults and which is able to diagnose
multiple faults with high accuracy even on compressed test
responses as they are produced in embedded test and built-in
self-test. The developed solution takes advantage of the linear
properties of a MISR compactor to identify a set of faults likely
to produce the observed faulty signatures. Experimental results
show an improvement in accuracy of up to 22 % over traditional
logic diagnosis solutions suitable for comparable compaction
ratios.BibTeX
Incremental Computation of Delay Fault Detection Probability for
Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In
Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI:
https://doi.org/10.1109/ETS.2014.6847805 Zusammenfassung
Large process variations in recent technology nodes
present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay
test generation method must therefore rely on the probability of
detecting a target delay fault with the currently chosen test vector
pairs. However, the huge number of probability evaluations in
practical applications creates a large computational overhead.
To address this issue, this paper presents the first incremental
delay fault detection probability computation algorithm in the
literature, which is suitable for the inner loop of automatic test
pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently
shows a very large speedup and only a small approximation error.BibTeX
