INTESYS

2014

1. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
   • Zusammenfassung
   • BibTeX
   • Link
   • DOI

   Zusammenfassung

   Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.

   BibTeX

   @inproceedings{WagneW2014, abstract = {Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.}, abteilung = {ra}, address = {Paderborn, Germany}, author = {Wagner, Marcus and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, day = {26--30}, doi = {10.1109/ETS.2014.6847805}, location = {Paderborn, Germany}, month = {05}, owner = {haefneht}, pages = { 81--86 }, project = {INTESYS}, title = {{Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_WagneW2014.pdf}, year = 2014 }

   Link

   https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_WagneW2014.pdf

   DOI

   10.1109/ETS.2014.6847805
2. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
   • Zusammenfassung
   • BibTeX
   • Link
   • DOI

   Zusammenfassung

   Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.

   BibTeX

   @inproceedings{CookW2014, abstract = {Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.}, abteilung = {ra}, address = {Paderborn, Germany}, author = {Cook, Alejandro and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, day = {26--30}, doi = {10.1109/ETS.2014.6847796}, location = {Paderborn, Germany}, month = {05}, owner = {haefneht}, pages = { 27--30 }, project = {INTESYS}, title = {{Diagnosis of Multiple Faults with Highly Compacted Test Responses}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_CookW2014.pdf}, year = 2014 }

   Link

   https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_CookW2014.pdf

   DOI

   10.1109/ETS.2014.6847796
3. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
   • Zusammenfassung
   • BibTeX
   • Link
   • DOI

   Zusammenfassung

   Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.

   BibTeX

   @inproceedings{CookW2014, abstract = {Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.}, abteilung = {ra}, address = {Paderborn, Germany}, author = {Cook, Alejandro and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, day = {26--30}, doi = {10.1109/ETS.2014.6847796}, location = {Paderborn, Germany}, month = {05}, owner = {haefneht}, pages = { 27--30 }, project = {INTESYS}, title = {{Diagnosis of Multiple Faults with Highly Compacted Test Responses}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_CookW2014.pdf}, year = 2014 }

   Link

   https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_CookW2014.pdf

   DOI

   10.1109/ETS.2014.6847796
4. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
   • Zusammenfassung
   • BibTeX
   • Link
   • DOI

   Zusammenfassung

   Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.

   BibTeX

   @inproceedings{WagneW2014, abstract = {Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.}, abteilung = {ra}, address = {Paderborn, Germany}, author = {Wagner, Marcus and Wunderlich, Hans-Joachim}, booktitle = {Proceedings of the 19th IEEE European Test Symposium (ETS'14)}, day = {26--30}, doi = {10.1109/ETS.2014.6847805}, location = {Paderborn, Germany}, month = {05}, owner = {haefneht}, pages = { 81--86 }, project = {INTESYS}, title = {{Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation}}, url = {https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_WagneW2014.pdf}, year = 2014 }

   Link

   https://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ETS_WagneW2014.pdf

   DOI

   10.1109/ETS.2014.6847805