Herr Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Leitung der Forschungsgruppe Rechnerarchitektur
Institut für Technische Informatik
Rechnerarchitektur

Kontakt

+49 711 685-88391
+49 711 685-88288

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 2.170

  1. 2020

    1. GPU-accelerated Time Simulation of  Systems with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In to appear in Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6.
    2. Variation-Aware Defect Characterization at Cell Level. Zahra Najafi Haghi; Marzieh Hashemipour Nazari and Hans-Joachim Wunderlich. In to appear in Proceedings of the 25th IEEE European Test Symposium (ETS’20), Tallinn, Estonia, 2020, pp. 1--6.
    3. Using Programmable Delay Monitors for  Wear-Out and Early Life Failure Prediction. Chang Liu; Eric Schneider and Hans-Joachim. Wunderlich. In to appear in Proceedings of the ACM/IEEEConference  on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6.
    4. Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. Eric Schneider and Hans-Joachim Wunderlich. In to appear in Proceedings of the  IEEE VLSI TestSymposium (VTS’20), San Diego, US, 2020, pp. 1--6.
    5. Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In to appear in Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6.
  2. 2019

    1. Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019.
    2. On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’19), Florence, Italy, 2019, pp. 1016--1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
    3. Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019.
    4. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems (TCAD) 38, 10 (2019), pp. 1956–1968. DOI: https://doi.org/10.1109/TCAD.2018.2864255
    5. Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (2019), pp. 78--91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
  3. 2018

    1. Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2018.8400685
    2. Device aging: A reliability and security concern. Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit Singh; Hans-Joachim Wunderlich and Naghmeh Karimi. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2018.8400702
    3. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
    4. Detecting and Resolving Security Violations in Reconfigurable Scan Networks. Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the 24th IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’18), Platja d’Aro, Spain, 2018, pp. 91--96. DOI: https://doi.org/10.1109/IOLTS.2018.8474188
    5. Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, 1 (2018), pp. 1--1. DOI: https://doi.org/10.1109/LES.2018.2789942
    6. Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, 3 (2018), pp. 5--6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
  4. 2017

    1. Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’17), Thessaloniki, Greece, 2017, pp. 237--239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
    2. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
    3. Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
    4. Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968247
    5. Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1--6. DOI: https://doi.org/10.1109/VTS.2017.7928921
    6. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (2017), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    7. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    8. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Transactions on Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    9. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Trans. Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
  5. 2016

    1. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    2. Fault Tolerance of Approximate Compute Algorithms. Hans-Joachim Wunderlich; Claus Braun and Alexander Schöll. In Proceedings of the 34th VLSI Test Symposium (VTS’16), Caesars Palace, Las Vegas, Nevada, USA, 2016. DOI: https://doi.org/10.1109/VTS.2016.7477307
    3. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16), Toulouse, France, 2016, pp. 251--262. DOI: https://doi.org/10.1109/DSN.2016.31
    4. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    5. SHIVA: Sichere Hardware in der Informationsverarbeitung. Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the ITG/GI/GMM edaWorkshop 2016, Hannover, Germany, 2016.
    6. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    7. Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
    8. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
    9. Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS’16), Foz do Iguaçu, Brazil, 2016, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
    10. Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 246--251. DOI: https://doi.org/10.1109/ATS.2016.18
    11. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
  6. 2015

    1. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    2. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    3. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    4. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
    5. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, 2015, pp. 5:1--5:8. DOI: https://doi.org/10.1145/2786572.2788708
    6. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI  and Nanotechnology Systems (DFT’15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
    7. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    8. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD’15), Austin, Texas, USA, 2015, pp. 38–45.
    9. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate  Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 95--100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
    10. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    11. On-Line Prediction of NBTI-induced Aging Rates. Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu; Mehdi Tahoori and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 589--592. DOI: https://doi.org/10.7873/DATE.2015.0940
    12. Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, 3 (2015), pp. 149--158. DOI: https://doi.org/10.1515/itit-2014-1082
    13. High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 3 (2015), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2714564
    14. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
    15. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
  7. 2014

    1. Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’14), Belfast, United Kingdom, 2014, pp. 424--431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
    2. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    3. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--6. DOI: https://doi.org/10.1145/2593069.2593146
    4. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
    5. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23. DOI: https://doi.org/10.1109/ICCAD.2014.7001324
    6. Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures. Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.373
    7. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    8. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    9. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2014.7035360
    10. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
    11. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE’14 Conference, Dresden, Germany, 2014.
    12. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    13. Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the Design, Automation and Test in Europe (DATE’14), Dresden, Germany, 2014. DOI: https://doi.org/10.7873/DATE.2014.206
    14. A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’14), Atlanta, Georgia, USA, 2014, pp. 443--454. DOI: https://doi.org/10.1109/DSN.2014.48
    15. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
    16. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262--285.
    17. Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 5 (2014), pp. 527--540. DOI: https://doi.org/10.1007/s10836-014-5477-1
    18. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    19. Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 3 (2014), pp. 28:1--28:17. DOI: https://doi.org/10.1145/2611760
    20. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 4 (2014), pp. 401--413. DOI: https://doi.org/10.1007/s10836-014-5459-3
    21. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 4 (2014), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2647955
    22. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, 6--7 (2014), pp. 1066--1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
    23. SAT-Based ATPG beyond Stuck-at Fault Testing. Sybille Hellebrand and Hans-Joachim Wunderlich. it - Information Technology 56, 4 (2014), pp. 165--172. DOI: https://doi.org/10.1515/itit-2013-1043
  8. 2013

    1. Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS’13), Crete, Greece, 2013, pp. 240--243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
    2. Scan Pattern Retargeting and Merging with Reduced Access Time. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE European Test Symposium (ETS’13), Avignon, France, 2013, pp. 39--45. DOI: https://doi.org/10.1109/ETS.2013.6569354
    3. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI: https://doi.org/10.1109/DFT.2013.6653580
    4. Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW’13), Cordoba, Argentina, 2013.
    5. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    6. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    7. Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
    8. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
  9. 2012

    1. Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012, pp. 37--42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
    2. Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 155--160. DOI: https://doi.org/10.1109/ATS.2012.23
    3. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’12), Philadelphia, Pennsylvania, USA, 2012, pp. 1--6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
    4. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
    5. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW’12), Quito, Ecuador, 2012, pp. 1--4. DOI: https://doi.org/10.1109/LATW.2012.6261229
    6. Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 214--219. DOI: https://doi.org/10.1109/ATS.2012.32
    7. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12), Montreal, Canada, 2012, pp. 207--212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
    8. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, Germany, 2012, pp. 38--45. DOI: https://doi.org/10.1109/AHS.2012.6268667
    9. Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 98--103. DOI: https://doi.org/10.1109/ETS.2012.6233017
    10. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS’12), Hyatt Maui, Hawaii, USA, 2012, pp. 50--55. DOI: https://doi.org/10.1109/VTS.2012.6231079
    11. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    12. Efficient System-Level Aging Prediction. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 164--169. DOI: https://doi.org/10.1109/ETS.2012.6233028
    13. Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
    14. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
    15. Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, 12 (2012), pp. 1908--1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
  10. 2011

    1. Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 383--388. DOI: https://doi.org/10.1109/ATS.2011.52
    2. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
    3. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011, pp. 1303--1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
    4. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    5. Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS’11), Taipei, Taiwan, 2011, pp. 69--78. DOI: https://doi.org/10.1145/2039370.2039384
    6. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011, pp. 55--58.
    7. P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
    8. Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 76--83.
    9. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 111--116. DOI: https://doi.org/10.1109/ETS.2011.25
    10. Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 285--290. DOI: https://doi.org/10.1109/ATS.2011.55
    11. SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures. Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, 2011, pp. 33--38. DOI: https://doi.org/10.1109/ISLPED.2011.5993600
    12. Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 169--174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
    13. Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 278--283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
    14. Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 43--47.
    15. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 183--188. DOI: https://doi.org/10.1109/ETS.2011.33
    16. Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 213--218. DOI: https://doi.org/10.1109/ATS.2011.60
    17. Robuster Selbsttest mit Diagnose. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 48--53.
    18. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    19. Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults. Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich and Christian G. Zoellin. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1784--1796. DOI: https://doi.org/10.1007/s11432-011-4366-9
  11. 2010

    1. Parity Prediction Synthesis for Nano-Electronic Gate Designs. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699312
    2. Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS’10), Praha, Czech Republic, 2010, pp. 253--253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
    3. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T’10), Austin, Texas, USA, 2010.
    4. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 3--8. DOI: https://doi.org/10.1109/ATS.2010.10
    5. Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC’10), Anaheim, California, USA, 2010, pp. 380--385. DOI: https://doi.org/10.1145/1837274.1837369
    6. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
    7. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    8. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 2010.
    9. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’10), Wildbad Kreuth, Germany, 2010, pp. 25--32.
    10. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS’10), Santa Cruz, California, USA, 2010, pp. 93--98. DOI: https://doi.org/10.1109/VTS.2010.5469607
    11. Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    12. BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 1243--1248.
    13. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    14. Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133--155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
    15. Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187--215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
    16. Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117--146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
    17. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen;  Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, 4 (2010), pp. 209--215. DOI: https://doi.org/10.1524/itit.2010.0593
    18. Efficient Concurrent Self-Test with Partially Specified Patterns. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 26, 5 (2010), pp. 581--594. DOI: https://doi.org/10.1007/s10836-010-5167-6
  12. 2009

    1. Test exploration and validation using transaction level models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    2. Modellierung der Testinfrastruktur auf der Transaktionsebene. Michael A. Kochte; Christian Zöllin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In 21th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 61--66.
    3. Restrict Encoding for Mixed-Mode BIST. Abdul-Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke and Andreas Glowatz. In Proceedings of the 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, California, USA, 2009, pp. 179--184. DOI: https://doi.org/10.1109/VTS.2009.43
    4. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
    5. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’09), Stuttgart, Germany, 2009, pp. 21--28.
    6. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 53--58. DOI: https://doi.org/10.1109/ETS.2009.26
    7. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
    8. Diagnose mit extrem kompaktierten Fehlerdaten. Stefan Holst and Hans-Joachim Wunderlich. In 21. ITG/GI/GMM Workshop “Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 15--20.
    9. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen. Hans-Joachim Wunderlich; Melanie Elm and Michael A. Kochte. In Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertungin frühen Entwicklungsphasen, Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (eds.). Springer-Verlag Heidelberg, 2009, pp. 391--464. DOI: https://doi.org/10.1007/978-3-540-85091-5_8
    10. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
  13. 2008

    1. Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008.
    2. Test Set Stripping Limiting the Maximum Number of Specified Bits. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), Hong Kong, China, 2008, pp. 581--586. DOI: https://doi.org/10.1109/DELTA.2008.64
    3. Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. Torsten Coym; Sybille Hellebrand; Stefan Ludwig; Bernd Straube; Hans-Joachim Wunderlich and Christian Zöllin. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 153--157.
    4. Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information. Michael E. Imhof; Hans-Joachim Wunderlich; Christian Zöllin; Jens Leenstra and Nicolas Maeding. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 137--141.
    5. Zur Zuverlässigkeitsmodellierung von Hardware-Software-Systemen;  On the Reliability Modeling of Hardware-Software-Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 83--90.
    6. Scan Chain Clustering for Test Power Reduction. Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra and Nicolas Maeding. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08), Anaheim, California, USA, 2008, pp. 828--833. DOI: https://doi.org/10.1145/1391469.1391680
    7. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian Zöllin. In 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR’08), Verbania, Italy, 2008.
    8. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
    9. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    10. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS’08), Rhodes, Greece, 2008, pp. 59--64. DOI: https://doi.org/10.1109/IOLTS.2008.31
    11. On the Reliability Modeling of Embedded Hardware-Software Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 1st IEEE Workshop on Design for Reliability and Variability (DRV’08), Santa Clara, California, USA, 2008.
    12. Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung. Melanie Elm and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 7--11.
    13. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung;  Detection of transient faults in circuits with reduced power dissipation. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 107--114.
    14. Signature Rollback – A Technique for Testing Robust Circuits. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, 2008, pp. 125--130. DOI: https://doi.org/10.1109/VTS.2008.34
  14. 2007

    1. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian Zöllin; Andreas Glowatz; Jürgen Schlöffel and Friedrich Hapke. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 61--65.
    2. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Juergen Schloeffel and Laurent Souef. In Proceedings of the International Test Conference (ITC’07), Santa Clara, California, USA, 2007, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2007.4437611
    3. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute. Michael E. Imhof; Christian G. Zöllin; Hans-Joachim Wunderlich; Nicolas Mäding and Jens Leenstra. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 69--76.
    4. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 82--86.
    5. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, 2007, pp. 50--58. DOI: https://doi.org/10.1109/DFT.2007.43
    6. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    7. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
    8. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 91--96. DOI: https://doi.org/10.1109/ETS.2007.10
    9. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper). Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 3--10.
    10. Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen. Michael Wedel; Peter Göhner; Jochen Gäng; Bernd Bertsche; Talal Arnaout and Hans-Joachim Wunderlich. In 5. Paderborner Workshop “Entwurf mechatronischer Systeme,” Paderborn, Germany, 2007, pp. 257--272.
    11. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (2. Auflage), Christian Siemers and Axel Sikora (eds.). Fachbuchverlag Leipzig im Carl Hanser Verlag, 2007, pp. 267--290.
    12. Academic Network for Microelectronic Test Education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean Pierre Van Der Heyden. The International Journal of Engineering Education 23, 6 (2007), pp. 1245--1253.
    13. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (2007), pp. 235--243.
    14. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. IET Computers & Digital Techniques 1, 3 (2007), pp. 180--186. DOI: http://digital-library.theiet.org/content/journals/10.1049/iet-cdt_20060131
  15. 2006

    1. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zöllin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 101--103.
    2. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS’06), Tunis, Tunisia, 2006, pp. 359--364. DOI: https://doi.org/10.1109/DTIS.2006.1708693
    3. Software-Based Self-Test of Processors under Power Constraints. Jun Zhou and Hans-Joachim Wunderlich. In Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE’06), Munich, Germany, 2006, pp. 430--436. DOI: https://doi.org/10.1109/DATE.2006.243798
    4. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. In Proceedings of the 11th European Test Symposium (ETS’06), Southampton, United Kingdom, 2006, pp. 123--130. DOI: https://doi.org/10.1109/ETS.2006.12
    5. Structural-based Power-aware Assignment of Don’t Cares for Peak Power Reduction during Scan Testing. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Virazel Arnaud and Hans-Joachim Wunderlich. In Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, 2006, pp. 403--408. DOI: https://doi.org/10.1109/VLSISOC.2006.313222
    6. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 95--100.
    7. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the International Test Conference (ITC’06), Santa Clara, California, USA, 2006, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2006.297695
    8. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    9. X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilian Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
  16. 2005

    1. Implementing a Scheme for External Deterministic Self-Test. Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS’05), Palm Springs, California, USA, 2005, pp. 101--106. DOI: https://doi.org/10.1109/VTS.2005.50
    2. Development of an Audio Player as System-on-a-Chip using an Open Source Platform. Kiatisevi Pattara; Luis Azuara; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’05), Kobe, Japan, 2005, pp. 2935--2938. DOI: https://doi.org/10.1109/ISCAS.2005.1465242
    3. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilian Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 16--20.
    4. From Embedded Test to Embedded Diagnosis. Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE European Test Sypmposium (ETS’05), Tallinn, Estonia, 2005, pp. 216--221. DOI: https://doi.org/10.1109/ETS.2005.26
    5. Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. Jun Zhou and Hans-Joachim Wunderlich. In INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 2005, pp. 441--441.
    6. On the Reliability Evaluation of SRAM-based FPGA Designs. Oliver Héron; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, 2005, pp. 403--408. DOI: https://doi.org/10.1109/FPL.2005.1515755
    7. DLBIST for Delay Testing. Michael Garbers; Jürgen Schlöffel; Valentin Gherman and Hans-Joachim Wunderlich. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 39--43.
    8. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
  17. 2004

    1. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke and Michael Garbers. In Proceedings of the 35th IEEE International Test Conference (ITC’04), Charlotte, New York, USA, 2004, pp. 48--56. DOI: https://doi.org/10.1109/TEST.2004.1386936
    2. Reliability Considerations for Mechatronic Systems on the Basis of a State Model. Peter Göhner; Eduard Zimmer; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 17th International Conference on Architecture of Computing Systems (ARCS’04) - Organic and Pervasive Computing, Augsburg, Germany, 2004, pp. 106--112.
    3. Masking X-Responses During Deterministic Self-Test. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Garbers and Jürgen Schlöffel. In 16th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’04), Dresden, Germany, 2004, pp. 13--19.
    4. EuNICE-Test: European network for test education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’04), Tatranska Lomnica, Slovakia, 2004.
    5. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    6. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke and Michael Wittke. In Proceedings of the 9th IEEE European Test Sypmposium (ETS’04), Ajaccio, Corsica, France, 2004, pp. 327--332.
    7. Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE International Workshop on Electronic Design, Test and Applications (DELTA’04), Perth, Australia, 2004, pp. 135--140.
    8. X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In 5th IEEE International Workshop on Test Resource Partitioning (TRP’04), Napa Valley, California, USA, 2004, pp. 442--451.
  18. 2003

    1. Test Engineering Education in Europe: the EuNICE-Test Project. Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Anton Biasizzo; Frank Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean-Pierre Van der Heyden. In Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE’03), Anaheim, California, USA, 2003, pp. 85--86. DOI: https://doi.org/10.1109/MSE.2003.1205266
  19. 2002

    1. Combining Deterministic Logic BIST with Test Point Insertion. Harald Vranken; Florian Meister and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW’02), Korfu, Greece, 2002, pp. 105--110. DOI: https://doi.org/10.1109/ETW.2002.1029646
    2. RESPIN++ - Deterministic Embedded Test. Lars Schäfer; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW’02), Korfu, Greece, 2002, pp. 37--44. DOI: https://doi.org/10.1109/ETW.2002.1029637
    3. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (2002), pp. 231--240. DOI: https://doi.org/10.1023/A:1014968930415
    4. A Mixed-Mode BIST Scheme Based on Folding Compression. Huaguo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Computer Science and Technology 17, 2 (2002), pp. 203–212. DOI: https://doi.org/10.1007/BF02962213
    5. Efficient Online and Offline Testing of Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets and Vyacheslav N. Yarmolik. IEEE Transactions on Computers 51, 7 (2002), pp. 801--809. DOI: https://doi.org/10.1109/TC.2002.1017700
    6. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (2002), pp. 159--170. DOI: https://doi.org/10.1023/A:1014993509806
    7. High Defect Coverage with Low Power Test Sequences in a BIST Environment. Patrick Girard; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel and Hans-Joachim Wunderlich. IEEE Design & Test of Computers 19, 5 (2002), pp. 44--52. DOI: https://doi.org/10.1109/MDT.2002.1033791
  20. 2001

    1. Circuit Partitioning for Efficient Logic BIST Synthesis. Alexander Irion; Gundolf Kiefer; Harald Vranken and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE’01), Munich, Germany, 2001, pp. 86--91. DOI: https://doi.org/10.1109/DATE.2001.915005
    2. A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. Patrick Girard; Lois Guiller; Christian Landrault; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 19th VLSI Test Symposium (VTS’01), Marina Del Rey, California, USA, 2001, pp. 306--311. DOI: https://doi.org/10.1109/VTS.2001.923454
    3. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In European Test Workshop (ETW’01), Stockholm, Sweden, 2001, pp. 307--315.
    4. Tailoring ATPG for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 530--537. DOI: https://doi.org/10.1109/TEST.2001.966671
    5. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 6th European Test Workshop (ETW’01), Stockholm, Sweden, 2001, pp. 124--132. DOI: https://doi.org/10.1109/ETW.2001.946677
    6. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (2001), pp. 341--349. DOI: https://doi.org/10.1023/A:1012279716236
    7. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (2001), pp. 351--362. DOI: https://doi.org/10.1023/A:1012283800306
  21. 2000

    1. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 105--114. DOI: https://doi.org/10.1109/TEST.2000.894197
    2. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 778--784. DOI: https://doi.org/10.1109/TEST.2000.894274
    3. Non-Intrusive BIST for Systems-on-a-Chip. Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 31st IEEE International Test Conference (ITC’00), Atlantic City, New Jersey, USA, 2000, pp. 644--651. DOI: https://doi.org/10.1109/TEST.2000.894259
    4. Using Mission Logic for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In 1st IEEE International Workshop on Test Resource Partitioning (TRP’00), Atlantic City, New Jersey, USA, 2000.
    5. Optimal Hardware Pattern Generation for Functional BIST. Silvia Cataldo; Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 7th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Paris, France, 2000, pp. 292--297. DOI: https://doi.org/10.1109/DATE.2000.840286
    6. Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In 7th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 2000.
    7. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (2000), pp. 203--212. DOI: https://doi.org/10.1023/A:1008383013319
    8. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (2000), pp. 169--177. DOI: https://doi.org/10.1023/A:1008374811502
  22. 1999

    1. Symmetric Transparent BIST for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 2nd Conference on Design, Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702--707. DOI: https://doi.org/10.1109/DATE.1999.761206
    2. Exploiting Symmetries to Speed Up Transparent BIST. Sybille Hellebrand; Hans-Joachim Wunderlich and Vyacheslav N. Yarmolik. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 12--15.
    3. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE European Test Workshop (ETW’99), Constance, Germany, 1999, pp. 110--117. DOI: https://doi.org/10.1109/ETW.1999.804415
    4. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE International Test Conference (ITC’99), Atlantic City, New Jersey, USA, 1999, pp. 77--84. DOI: https://doi.org/10.1109/TEST.1999.805616
    5. Transparent Word-oriented Memory BIST Based on Symmetric March Algorithms. Vyacheslav N. Yarmolik; I.V. Bykov; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 3rd European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999, pp. 339--350. DOI: https://doi.org/10.1007/3-540-48254-7_23
    6. Minimum Scan Insertion for Generating Pipeline-Structured Modules. Gundolf Kiefer and Hans-Joachim Wunderlich. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 30--33.
    7. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 14, 1–2 (1999), pp. 85--93. DOI: https://doi.org/10.1023/A:1008353423305
  23. 1998

    1. Accumulator Based Deterministic BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC’98), Washington, DC, USA, 1998, pp. 412--421. DOI: https://doi.org/10.1109/TEST.1998.743181
    2. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173--179. DOI: https://doi.org/10.1109/DATE.1998.655853
    3. Efficient Consistency Checking for Embedded Memories. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’98), Herrenberg, Germany, 1998.
    4. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’98), Sitges, Barcelona, Spain, 1998, pp. 39--43.
    5. Pattern Selection for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
    6. Scan Path Design for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’98), Herrenberg, Germany, 1998.
    7. Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Madhavi Karkala; Nur A. Touba and Hans-Joachim Wunderlich. In Proceedings of the 7th Asian Test Symposium (ATS’98), Singapore, 1998, pp. 492--499. DOI: https://doi.org/10.1109/ATS.1998.741662
    8. Fast Self-Recovering Controllers. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE VLSI Test Symposium (VTS’98), Monterey, California, USA, 1998, pp. 296--302. DOI: https://doi.org/10.1109/VTEST.1998.670883
    9. Low-Power Serial Built-In Self Test. Andre Hertwig and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’98), Sitges, Barcelona, Spain, 1998, pp. 51.
    10. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC’98), Washington, DC, USA, 1998, pp. 1057--1064. DOI: https://doi.org/10.1109/TEST.1998.743304
    11. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In On-Line Testing for VLSI, Michael Nicolaidis; Yervant Zorian and Dhiraj K. Pradhan (eds.). Kluwer Academic Publishers, 1998.
    12. Test and Testable Design. Hans-Joachim Wunderlich. In Architecture Design and Validation Methods, Egon Börger (ed.). Springer-Verlag Heidelberg, 1998, pp. 141--190.
    13. BIST for Systems-on-a-Chip. Hans-Joachim Wunderlich. Integration, the VLSI Journal - Special issue on VLSI testing 26, 1–2 (1998), pp. 55--78. DOI: https://doi.org/10.1016/S0167-9260(98)00021-2
    14. Hardware-Optimal Test Register Insertion. Albrecht P. Stroele and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 17, 6 (1998), pp. 531--539. DOI: https://doi.org/10.1109/43.703833
  24. 1997

    1. Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
    2. Fast Controllers for Data Dominated Applications. Andre Hertwig and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC’97), Paris, France, 1997, pp. 84--89. DOI: https://doi.org/10.1109/EDTC.1997.582337
    3. Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand. Gundolf Kiefer and Hans-Joachim Wunderlich. In 9th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’97), Bremen, Germany, 1997, pp. 49--52.
    4. Using BIST Control for Pattern Generation. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop, Cagliari, Italy, 1997.
  25. 1996

    1. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In Proceedings of the 27th IEEE International Test Conference (ITC’96), Washington, DC, USA, 1996, pp. 195--204. DOI: https://doi.org/10.1109/TEST.1996.556962
    2. Using Embedded Processors for BIST. Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1996.
    3. Bit-Flipping BIST. Hans-Joachim Wunderlich and Gundolf Kiefer. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’96), San Jose, California, USA, 1996, pp. 337--343. DOI: https://doi.org/10.1109/ICCAD.1996.569803
    4. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In 2nd IEEE International On-Line Testing Workshop, Biarritz, France, 1996.
  26. 1995

    1. Pattern Generation for a Deterministic BIST Scheme. Sybille Hellebrand; Birgit Reeb; Steffen Tarnick and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’95), San Jose, California, USA, 1995, pp. 88--94. DOI: https://doi.org/10.1109/ICCAD.1995.479997
    2. Test Register Insertion with Minimum Hardware Cost. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’95), San Jose, California, USA, 1995, pp. 95--101. DOI: https://doi.org/10.1109/ICCAD.1995.479998
    3. Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest. Olaf Stern and Hans-Joachim and Wunderlich. In 7th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’95), Hannover, Germany, 1995.
  27. 1994

    1. Configuring Flip-Flops to BIST Registers. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC’94), Washington, DC, USA, 1994, pp. 939--948. DOI: https://doi.org/10.1109/TEST.1994.528043
    2. Synthese schneller selbsttestbarer Steuerwerke. Sybille Hellebrand and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 3--11.
    3. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), San Jose, California, USA, 1994, pp. 110--116. DOI: https://doi.org/10.1109/ICCAD.1994.629752
    4. Ein Verfahren zur testfreundlichen Steuerwerkssynthese. Sybille Hellebrand and Hans-Joachim and Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    5. A Unified Method for Assembling Global Test Schedules. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 3rd Asian Test Symposium (ATS’94), Nara, Japan, 1994, pp. 268--273. DOI: https://doi.org/10.1109/ATS.1994.367220
    6. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the European Design Automation Conference (EDAC/ETC/EuroAsic’94), Paris, France, 1994, pp. 580--585. DOI: https://doi.org/10.1109/EDTC.1994.326815
    7. Synthesis for Testability - the ARCHIMEDES Approach. Sybille Hellebrand; J. P. Teixeira and Hans-Joachim and Wunderlich. In 1st IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1994.
    8. Analyse und Simulation realistischer Fehler. Olaf Stern; Wu and Hans-Joachim Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    9. Testsynthese für Datenpfade. Albrecht P. Ströle and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 162--171.
  28. 1993

    1. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support,” Montpellier, France, 1993.
  29. 1992

    1. Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen. Olaf Stern and Hans-Joachim Wunderlich. In 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, 1992, pp. 117--122. DOI: https://doi.org/10.18419/opus-7903
    2. The Pseudoexhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, 1 (1992), pp. 26--33. DOI: https://doi.org/10.1109/43.108616
    3. Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich and Michael H. Schulz. Informatik-Spektrum 15, 1 (1992), pp. 23--32. DOI: https://doi.org/10.18419/opus-7897
    4. Optimized Synthesis Techniques for Testable Sequential Circuits. Bernhard Eschermann and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, 3 (1992), pp. 301--312. DOI: https://doi.org/10.1109/43.124417
  30. 1991

    1. Parallel Self-Test and the Synthesis of Control Units. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 2nd European Test Conference (ETC’91), Munich, Germany, 1991, pp. 73--82. DOI: https://doi.org/10.18419/opus-7920
    2. Emulation of Scan Paths in Sequential Circuit Synthesis. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 5th International GI/ITG/GMA Conference on Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment, Nürnberg, Germany, 1991, pp. 136--147. DOI: https://doi.org/10.18419/opus-7904
    3. Signature Analysis and Test Scheduling for Self-Testable Circuits. Albrecht P. Ströle and Hans-Joachim Wunderlich. In Proceedings of the 21st International Symposium on Fault-Tolerant Computing (FTCS-21), Montreal, Canada, 1991, pp. 96--103. DOI: https://doi.org/10.1109/FTCS.1991.146640
    4. Maximizing the Fault Coverage in Complex Circuits by Minimal Number of Signatures. Hans-Joachim Wunderlich and Albrecht P. Ströle. In Proceedings of the IEEE International Sympoisum on Circuits and Systems (ISCAS’91), Singapur, 1991, pp. 1881--1884. DOI: https://doi.org/10.1109/ISCAS.1991.176774
    5. A Unified Approach for the Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC’91), San Francisco, California, USA, 1991, pp. 372--377. DOI: https://doi.org/10.1145/127601.127697
    6. A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. Thomas Kropf and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE International Test Conference (ITC’91), Nashville, Tennessee, USA, 1991, pp. 57--66. DOI: https://doi.org/10.1109/TEST.1991.519494
    7. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle and Hans-Joachim Wunderlich. IEEE Journal of Solid-State Circuits 26, 7 (1991), pp. 1056--1063. DOI: https://doi.org/10.1109/4.92026
  31. 1990

    1. Error Masking in Self-Testable Circuits. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International Test Conference (ITC’90), Washington, DC, USA, 1990, pp. 544--552. DOI: https://doi.org/10.1109/TEST.1990.114066
    2. The Effectiveness of Different Test Sets for PLAs. Peter C. Maxwell and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 628--632. DOI: https://doi.org/10.1109/EDAC.1990.136722
    3. A Synthesis Approach to Reduce Scan Design Overhead. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 671. DOI: https://doi.org/10.18419/opus-7927
    4. Optimized Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 20th International Symposium on Fault-Tolerant Computing (FTCS-20), Newcastle Upon Tyne, United Kingdom, 1990, pp. 390--397. DOI: https://doi.org/10.1109/FTCS.1990.89393
    5. Tools and Devices Supporting the Pseudo-Exhaustive Test. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 13--17. DOI: https://doi.org/10.1109/EDAC.1990.136612
    6. Generating Pseudo-Exhaustive Vectors for External Testing. Sybille Hellebrand; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 21st IEEE International Test Conference (ITC’90), Washington, DC, USA, 1990, pp. 670--679. DOI: https://doi.org/10.1109/TEST.1990.114082
    7. TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control. Albrecht P. Ströle; Hans-Joachim Wunderlich and Oliver F. Haberl. In Proceedings of the 16th European Solid-State Circuits Conference (ESSCIRC’90), Grenoble, France, 1990, pp. 101--104. DOI: https://doi.org/10.18419/opus-7921
    8. Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 9, 6 (1990), pp. 584--593. DOI: https://doi.org/10.1109/43.55187
    9. Methoden der Testvorbereitung zum IC-Entwurf. Martin H. Schulz and Hans-Joachim Wunderlich. Mikroelektronik 4, 3 (1990), pp. 112--115. DOI: https://doi.org/10.18419/opus-7919
    10. An Analytical Approach to the Partial Scan Problem. Arno Kunzmann and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 1, 2 (1990), pp. 163--174. DOI: https://doi.org/10.1007/BF00137392
  32. 1989

    1. The Design of Random-Testable Sequential Circuits. Hans-Joachim Wunderlich. In Proceedings of the 19th International Symposium on Fault-Tolerant Computing (FTCS-19), Chicago, Illinois, USA, 1989, pp. 110--117. DOI: https://doi.org/10.1109/FTCS.1989.105552
    2. Methoden der Testvorbereitung. Hans-Joachim Wunderlich and Martin H. Schulz. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 55--62. DOI: https://doi.org/10.18419/opus-7932
    3. The Synthesis of Self-Test Control Logic. Oliver F. Haberl and Hans-Joachim Wunderlich. In Proceedings of the CompEuro ’89., “VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks,” Hamburg, Germany, 1989, pp. 5/134--5/136. DOI: https://doi.org/10.1109/CMPEUR.1989.93499
    4. The Pseudo-Exhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 20th IEEE International Test Conference (ITC’89), Washington, DC, USA, 1989, pp. 19--27. DOI: https://doi.org/10.1109/TEST.1989.82273
    5. Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen. F. Kesel and Hans-Joachim Wunderlich. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 63--68. DOI: https://doi.org/10.18419/opus-7933
    6. Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern. Frank Kesel and Hans-Joachim Wunderlich. In GMD Berichte, 4. E.I.S.-Workshop, Bonn, Germany, 1989, pp. 75--84. DOI: https://doi.org/10.18419/opus-7936
  33. 1988

    1. Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE International Test Conference (ITC’88). New Frontiers in Testing, International, Washington, DC, USA, 1988, pp. 236--244. DOI: https://doi.org/10.1109/TEST.1988.207808
    2. Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 18th International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, 1988, pp. 36--41. DOI: https://doi.org/10.1109/FTCS.1988.5294
    3. Automatisierung des Entwurfs vollständig testbarer Schaltungen. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 18. GI Jahrestagung II, Hamburg, Germany, 1988, pp. 145--159. DOI: https://doi.org/10.1007/978-3-642-74135-7_10
    4. Weighted Random Patterns with Multiple Distributions. Hans-Joachim Wunderlich. In Proceedings of the 11th International Conference on Fault Tolerant Systems and Diagnostics, Suhl, German Democratic Republic, 1988, pp. 88--93. DOI: https://doi.org/10.18419/opus-7941
    5. Output-maximal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1988, pp. 1011--1020. DOI: https://doi.org/10.1080/00207728808547182
  34. 1987

    1. Integrated Tools for Automatic Design for Testability. D. Schmid; Hans-Joachim Wunderlich; F. Feldbusch; Sybille Hellebrand; J. Holzinger and Arno Kunzmann. In Proceedings of the IFIP WG 10.2 Workshop on Tool Integration and Design Environments, Paderborn, Germany, 1987, pp. 233--258. DOI: https://doi.org/10.18419/opus-7942
    2. Self Test Using Unequiprobable Random Patterns. Hans-Joachim Wunderlich. In Proceedings of the 17th International Symposium on Fault-Tolerant Computing (FTCS-17), Pittsburgh, Pennsylvania, USA, 1987, pp. 258--263. DOI: https://doi.org/10.18419/opus-7946
  35. 1986

    1. The Integration of Test and High Level Synthesis in a General Design Environment. D. Schmid; R. Camposano; Arno Kunzmann; Wolfgang Rosenstiel and Hans-Joachim Wunderlich. In Proceedings of the Integrated Circuits Technology Conference (ICTC’86), Limerick, Ireland, 1986, pp. 317--331. DOI: https://doi.org/10.18419/opus-7947
    2. On Fault Modeling for Dynamic MOS Circuits. Hans-Joachim Wunderlich and Wolfgang Rosenstiel. In Proceedings of the 23rd ACM/IEEE Design Automation Conference (DAC’86), Las Vegas, Nevada, USA, 1986, pp. 540--546. DOI: https://doi.org/10.1145/318013.318100
  36. 1985

    1. Design Automation of Random Testable Circuits. Arno Kunzmann and Hans-Joachim Wunderlich. In Proceedings of the 11th European Solid-State Circuits Conference (ESSCIRC’85), Toulouse, France, 1985, pp. 277--285. DOI: https://doi.org/10.18419/opus-7949
  37. 1984

    1. Time-optimal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1984, pp. 513--524. DOI: https://doi.org/10.1080/00207729408926580

Ausbildung

Wissenschaftliche Prüfungen

07.1990

Abschluss des Habilitationsverfahrens und Erteilung der Lehrbefugnis für das Fach Informatik, Habilitationsschrift über „Rechnergestützte Verfahren für den prüfgerechten Entwurf und Test hochintegrierter Schaltungen“

12.1986

Promotion zum Dr. rer. nat. an der Fakultät für Informatik der Universität Karlsruhe
(„Mit Auszeichnung“) über „Probabilistische Verfahren zur Verbesserung der Testbarkeit hochintegrierter Schaltungen“

10.1981

Diplom in Mathematik mit Nebenfach Philosophie an der Universität Freiburg

1979-1981

Studium der Mathematik und der Philosophie an der Universität Freiburg

1975-1979

Studium der Mathematik und der Philosophie an der Universität Konstanz

Berufliche Laufbahn

seit 10.2019

Leitung der Forschungsgruppe „Rechnerarchitektur“ am Institut für Technische Informatik der Universität Stuttgart

10.2017 - 09.2019

Leiter der Abteilung „Rechnerarchitektur“ des Instituts für Technische Informatik an der Universität Stuttgart

09.2002 - 09.2017

Geschäftsführender Direktor des Instituts für Technische Informatik an der Universität Stuttgart

10.2010 - 09.2013

Prodekan der Fakultät 5 für Informatik, Elektrotechnik und Informationstechnik

10.1996 - 09.2019

Ordentlicher Universitätsprofessor (C4) für „Technische Informatik“ an der Universität Stuttgart, Leiter der Abteilung „Rechnerarchitektur“

12.1991 - 09.1996

Ordentlicher Universitätsprofessor (C4) für „Technische Informatik“ an der Universität/GHS Siegen, Leiter der Fachgruppe „Rechnerstrukturen“

01.1991

Ernennung zum Hochschuldozenten (C2) an der Universität Karlsruhe

10.1990 - 03.1991

Vertretung einer C4-Professur an der Universität/GHS Duisburg für das Fach Informatik

09.1982 - 01.1991

Wissenschaftlicher Angestellter an der Universität Karlsruhe

1982

Freier Mitarbeiter am Fraunhofer Institut für Arbeitswirtschaft und Organisation (IAO) in Stuttgart

Längerfristige wissenschaftliche Tätigkeiten im Ausland

04.2010 - 05.2010

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

04.2005 - 08.2005

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

01.2000 - 03.2000

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

08.1999 - 10.1999

LogicVision Inc., San Jose, CA, USA

01.1996 - 02.1996

Mentor Graphics Corporation, Portland, OR, USA

08.1995 - 03.1996

Visiting Professor am „Center of Reliable Computing“, Stanford University, Stanford, CA, USA

03.1988

Ruf als Visiting Assistant Professor an die McGill University, Montreal, Canada

 

2015

IEEE Computer Society, Test Technology Technical Council: Distinguished Service Award for many years of dedicated distinguishing service in creating, organizing, growing and steering ETS

2014

Guest Professor at Hefei University of Technology, Hefei, China

2009

IEEE Fellow for contributions to very-large-scale-integration circuit testing and fault tolerance

2006

IEEE Computer Society Golden Core Member

2005

IEEE Computer Society Meritorious Service Award

1998 - 2008

IEEE Certificates of Appreciation

2001

Ruf an die TU Wien, Professur: Embedded Computing Systems

2000

Landeslehrpreis 1999 des Landes Baden-Württemberg für das Hardware-Praktikum

Best Paper Awards

  • Schöll, A., Braun, C. und Wunderlich, H.-J.
    "Applying Efficient Fault Tolerance to Enable the Preconditioned Conjugate Gradient Solver on Approximate Computing Hardware"
    Best paper award IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'16), University of Connecticut, USA, 19-20 September 2016
  • Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. und Qian, J.
    "Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch"
    Best paper award 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015
  • Baranowski, R., Kochte, M. A. und Wunderlich, H.-J.
    "Access Port Protection for Reconfigurable Scan Networks"
    Best paper award Journal of Electronic Testing: Theory and Applications (JETTA: best paper of the year 2014), Vol. 30(6), 5 December 2014, pp. 711-723
  • Sauer, M., Polian, I., Imhof, M.E., Mumtaz, A., Schneider, E., Czutro, A., Wunderlich, H.-J. und Becker, B.:
    "Variation-Aware Deterministic ATPG",
    Best paper award 19th IEEE European Test Symposium (ETS), Paderborn, Germany, May 26-30, 2014
  • Elm, M. und Wunderlich, H.-J.:
    "XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad",
    Best paper award VDE Tagung "Zuverlässigkeit und Entwurf" (ZuE), Stuttgart, Germany, September 21-23, 2009.
  • Kochte, M.A., Zoellin, C.G., Imhof, M.E. und Wunderlich, H.-J.:
    "Test Set Stripping Limiting the Maximum Number of Specified Bits,"
    Best paper award 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008.
  • Holst, S. und Wunderlich, H.-J.:
    "Adaptive Debug and Diagnosis without Fault Dictionaries,"
    Best paper award 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007.
  • Öhler, P., Hellebrand, S. und Wunderlich, H.-J.:
    "Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair,"
    Best paper award 10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007

 

2019

Eric Schneider:

"Multi-Level Simulation of Nano-Electronic Digital Circuits on GPUs"

2018

Alexander Schöll:

"Efficient Fault Tolerance for Selected Scientific Computing Algorithms on Heterogeneous and Approximate Computer Architectures"

2017

Chang Liu:

“Improvement of Hardware Reliability with Aging Monitors”

2017

Laura Rodríguez Gómez:

“Machine Learning Support for Logic Diagnosis”

2016

Marcus Wagner:

“Efficient Algorithms for Fundamental Statistical Timing Analysis Problems
in Delay Test Applications of VLSI Circuits”

2015

Michael Imhof:

“Fault Tolerance Infrastructure and its Reuse for Offline Testing”

2015

Atefe Dalirsani:

“Self-Diagnosis in Network-on-Chips”

2015

Claus Braun:

“Algorithm-Based Fault Tolerance for Matrix Operations on Graphics Processing
Units: Analysis and Extension to Autonomous Operation”

2014

Michael Kochte:

“Boolean Reasoning for Digital Circuits in Presence of Unknown Values”

2014

Alejandro Cook:

“In-Field Structural Methods for End-to-End Automotive Digital Diagnosis”

2014

Nadereh Hatami:

“Multi-level Analysis of Non-Functional Properties”

2014

Christian Zöllin:

“Test Planning for Low-Power Built-In Self-Test”

2014

Rafal Baranowski:

“Reconfigurable scan networks : formal verification, access optimization,
and protection”

2012

Stefan Holst:

“Efficient Location–Based Logic Diagnosis of Digital Circuits”

2011

Melanie Elm:

“Embedded Hardware Structures for Efficient Volume and In-Field Diagnosis
of Random Logic Circuits”

2010

Abdul-Wahid Hakmi:

“Efficient Programmable Deterministic Self-Test”

2009

Jun Zhou:

“Software-Based Self-Test under Memory, Time, and Power Constraints”

2006

Valentin Gherman:

“Scalable Deterministic Logic Built-In Self-Test”

2003

Huaguo Liang:

“A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST)“

2002

Rainer Dorsch:

“Testverfahren für digitale eingebettete Ein-Chip-Systeme“

1996

Olaf Stern:

“Effiziente Erfassung von realistischen Fehlern in hochintegrierten Schaltungen“

 

Tagungsleitung (Auszug)

  • IEEE European Test Symposium (ETS)
    2008 - 2014 Vorsitzender des Steering Committee
    seit 2015 Mitglied des Steering Committee
    Program Chair: 1996 Montpellier (FRA), 1997 Cagliari (ITA), 2001 Stockholm (SWE)
    General Chair: 1999 Konstanz (GER)
    Vice General Chair: 1998 Sitges (ESP)
    Vice Program Chair: 2006 Southampton (GBR), 2007 Freiburg (GER)
    Member of the organization committee: 1996 - 2009
  • IEEE International Test Conference in Asia (ITC-Asia)
    2017 Taipei City (TW)
  • <