Research Projects

This project aims at developing methods to realize low-cost and power-efficient hardware circuits for near-sensor computing following the Stochastic Computing paradigm. Stochastic computing provides extremely compact, error-tolerant and low-power implementations of complex functions, but at the expense of longer computation times and some degree of inaccuracy. This makes stochastic circuits (SCs) especially attractive for near-sensor computing, where the processed sensor data are inaccurate anyway and computations tend to occur infrequently. A special focus of this project will be the SC realization of neural networks (NNs) used for classification tasks, from lightweight NNs to fully-fledged convolutional NNs for deep learning.

Technology scaling makes it possible to implement systems with hundreds of processing cores, and thousands in the future, on a single chip. The communication in such systems is enabled by Networks-on-Chips (NoCs). Homogeneous systems, resulting from the repetition of same-sized processing units, are well researched with respect to suitable network topologies (e.g. mesh), deadlock-free routing methods (e.g. turn models) and fault tolerance techniques (exploitation of path diversity). Heterogeneous systems, however, integrate processor components of varying size in an non-regular arrangement (floorplan). Suitable network topologies, routing methods, optimized mapping of application tasks onto the various processors, and fault tolerance were so far synthesized or manually developed in isolation of each other, often resulting in solutions that are globally suboptimal with respect to criteria such as cost, absence of deadlocks, and performance. Instead, we take an integrated view of all system-level design dimensions and research automated methods that generate optimal solutions with respect to user-defined objectives. We aim at finding mathematical formulations that can be solved to obtain guaranteed optimal solutions for systems of limited complexity. These shall be combined with heuristics so as to get good results for larger systems. The synthetesized Networks-on-Chip are to be verified using analytical and simulatation-based methods. For proof of practicability, we design network components to implement the synthesized structures and methods all the way down to the digital circuit level.