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Elhamawy, Nourhan

Nourhan Elhamawy

M.Sc.

Research Assistant
Institute of Computer Architecture and Computer Engineering
Hardware Oriented Computer Science

Contact

+49 711 685 61706
+49 711 685 67222
Email

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Room: 4.275

Publications

2024
1. Scenario-based Test Content Optimization: Scan Test vs. System-Level Test. Nourhan Elhamawy; Jens Anders; Ilia Polian and Matthias Sauer. In 2024 IEEE 42nd VLSI Test Symposium (VTS), 2024, pp. 1–7. DOI: https://doi.org/10.1109/VTS60656.2024.10538586
  Abstract
  Test application to state-of-the-art integrated circuits usually consists of multiple test insertions: wafer sort, final test and system-level test (SLT). This paper considers optimization of test content, taking requirements of specific scenarios, such as expected yield levels, test costs and criticality of test escapes, into account. An integrated cost model is proposed and applied to four different test setups on a medium-complexity RISC-V microprocessor. Our results indicate opportunities for up to ~ 40% total cost reduction compared to today’s industrial practice. They also provide insights on the relative importance of various cost contributors, such as the number of available scan test insertions or the specific SLT workload used.
  BibTeX
  @inproceedings{10538586, abstract = {Test application to state-of-the-art integrated circuits usually consists of multiple test insertions: wafer sort, final test and system-level test (SLT). This paper considers optimization of test content, taking requirements of specific scenarios, such as expected yield levels, test costs and criticality of test escapes, into account. An integrated cost model is proposed and applied to four different test setups on a medium-complexity RISC-V microprocessor. Our results indicate opportunities for up to ~ 40% total cost reduction compared to today’s industrial practice. They also provide insights on the relative importance of various cost contributors, such as the number of available scan test insertions or the specific SLT workload used.}, abteilung = {hocos}, author = {Elhamawy, Nourhan and Anders, Jens and Polian, Ilia and Sauer, Matthias}, booktitle = {2024 IEEE 42nd VLSI Test Symposium (VTS)}, doi = {10.1109/VTS60656.2024.10538586}, issn = {2375-1053}, month = {04}, pages = {1-7}, title = {Scenario-based Test Content Optimization: Scan Test vs. System-Level Test}, year = 2024 }
  DOI
  10.1109/VTS60656.2024.10538586
2023
1. A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. Jens Anders; Pablo Andreu; Bernd Becker; Steffen Becker; Riccardo Cantoro; Nikolaos I. Deligiannis; Nourhan Elhamawy; Tobias Faller; Carles Hernandez; Nele Mentens; Mahnaz Namazi Rizi; Ilia Polian; Abolfazl Sajadi; Mathias Sauer; Denis Schwachhofer; Matteo Sonza Reorda; Todor Stefanov; Ilya Tuzov; Stefan Wagner and Nuša Zidarič. In 2023 IEEE European Test Symposium (ETS), Venice, Italy, 2023, pp. 1–10. DOI: https://doi.org/10.1109/ETS56758.2023.10174099
  - BibTeX
  - DOI
  BibTeX
  @inproceedings{10174099, abteilung = {hocos}, author = {Anders, Jens and Andreu, Pablo and Becker, Bernd and Becker, Steffen and Cantoro, Riccardo and Deligiannis, Nikolaos I. and Elhamawy, Nourhan and Faller, Tobias and Hernandez, Carles and Mentens, Nele and Rizi, Mahnaz Namazi and Polian, Ilia and Sajadi, Abolfazl and Sauer, Mathias and Schwachhofer, Denis and Reorda, Matteo Sonza and Stefanov, Todor and Tuzov, Ilya and Wagner, Stefan and Zidarič, Nuša}, booktitle = {2023 IEEE European Test Symposium (ETS)}, day = {22--26}, doi = {10.1109/ETS56758.2023.10174099}, location = {Venice, Italy}, month = {05}, pages = {1-10}, title = {A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors}, year = 2023 }
  DOI
  10.1109/ETS56758.2023.10174099
2022
1. Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
  - BibTeX
  BibTeX
  @inproceedings{date2022GS, abteilung = {star,hocos,ra}, author = {Amrouch, Hussam and Anders, Jens and Becker, Steffen and Betka, Maik and Bleher, Gerd and Domanski, Peter and Elhamawy, Nourhan and Ertl, Thomas and Gatzastras, Athanasios and Genssler, Paul R. and Hasler, Sebastian and Heinrich, Martin and Hoorn, André van and Jafarzadeh, Hanieh and Kallfass, Ingmar and Klemme, Florian and Koch, Steffen and Küsters, Ralf and Lalama, Andrés and Latty, Raphael and Liao, Yiwen and Lylina, Natalia and Najafi-Haghi, Zahra Paria and Pflüger, Dirk and Polian, Ilia and Rivoir, Jochen and Sauer, Matthias and Schwachhofer, Denis and Templin, Steffen and Volmer, Christian and Wagner, Stefan and Weiskopf, Daniel and Wunderlich, Hans-Joachim and Yang, Bin and Zimmermann, Martin}, booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2022}, month = {03}, pages = {1–6}, place = {Antwerp, Belgium}, title = {Intelligent Methods for Test and Reliability}, year = 2022 }
2021
1. Security, Reliability and Test Aspects of the RISC-V Ecosystem. Jaume Abella; Sergi Alcaide; Jens Anders; Francisco Bas; Steffen Becker; Elke De Mulder; Nourhan Elhamawy; Frank K. Gürkaynak; Helena Handschuh; Carles Hernandez; Mike Hutter; Leonidas Kosmidis; Ilia Polian; Matthias Sauer; Stefan Wagner and Francesco Regazzoni. In Proceedings of the 26th IEEE European Test Symposium (ETS’21), 2021.
  - BibTeX
  BibTeX
  @inproceedings{abella2021security, abteilung = {hocos}, author = {Abella, Jaume and Alcaide, Sergi and Anders, Jens and Bas, Francisco and Becker, Steffen and De Mulder, Elke and Elhamawy, Nourhan and Gürkaynak, Frank K. and Handschuh, Helena and Hernandez, Carles and Hutter, Mike and Kosmidis, Leonidas and Polian, Ilia and Sauer, Matthias and Wagner, Stefan and Regazzoni, Francesco}, booktitle = {Proceedings of the 26th IEEE European Test Symposium (ETS'21)}, day = {24--28}, isbn = {978-1-6654-1849-2}, month = {05}, title = {Security, Reliability and Test Aspects of the RISC-V Ecosystem}, year = 2021 }
2020
1. An Open-Source Area-Optimized ECEG Cryptosystem in Hardware. Nourhan Elhamawy; Mael Gay and Ilia Polian. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, pp. 120–125. DOI: https://doi.org/10.1109/ISVLSI49217.2020.00031
  Abstract
  Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.
  BibTeX
  @inproceedings{9154961, abstract = {Hardware implementations of advanced cryptographic schemes gain importance for emerging cyber-physical and autonomous systems and with that the need for area-optimized hardware is also increasing. In this paper, we present a scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block. With the help of the Universal Elliptic Curve Arithmetic unit, that is designed to perform elliptic curve point multiplication, doubling and addition, the area has been kept to a minimum to fit on the Xilinx Spartan-6 LX75 FPGA. The design supports the NIST-recommended curves over prime fields.}, abteilung = {hocos}, author = {Elhamawy, Nourhan and Gay, Mael and Polian, Ilia}, booktitle = {2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, doi = {10.1109/ISVLSI49217.2020.00031}, isbn = {978-1-7281-5775-7}, issn = {2159-3477}, month = {07}, pages = {120-125}, title = {An Open-Source Area-Optimized ECEG Cryptosystem in Hardware}, year = 2020 }
  DOI
  10.1109/ISVLSI49217.2020.00031
2. Exploring the mysteries of system-level test. Ilia Polian; Jens Anders; Stefan Becker; Paolo Bernardi; Krishnendu Chakrabarty; Nourhan Elhamawy; Matthias Sauer; Adith Singh; Matteo Sonza Reorda and Stefan Wagner. In Proceedings of the 29th IEEE Asian Test Symposium (ATS’20), 2020.
  - BibTeX
  BibTeX
  @inproceedings{polian2020exploring, abteilung = {hocos}, author = {Polian, Ilia and Anders, Jens and Becker, Stefan and Bernardi, Paolo and Chakrabarty, Krishnendu and Elhamawy, Nourhan and Sauer, Matthias and Singh, Adith and Sonza Reorda, Matteo and Wagner, Stefan}, booktitle = {Proceedings of the 29th IEEE Asian Test Symposium (ATS'20)}, month = {11}, title = {Exploring the mysteries of system-level test.}, year = 2020 }

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Nourhan Elhamawy

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2020

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