Concurrent Self-Test with Paritially Specified Patterns for Low Test Latency and Overhead

Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. In this talk an improved concurrent BIST techniques based on a deterministic test set is discussed. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to trade- off fault coverage, test latency and hardware overhead.

Test Encoding for Extreme Response Compaction

Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a single parity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.

This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns.

In this talk a new iterative approach to test set encoding will be discussed, which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.

Power and Area Estimation of Error Detection and Error Correction Schemes for On-chip Buses

In recent years, the structure size on a chip has been scaled down to only a few nanometers. A tight power budget, like in mobile devices, makes low power consumption a strong requirement. For high computing power devices the cooling capacity has also taken into account and requires a low power design techniques. This is often achieved by a low supply voltage.
Yet a low voltage swing, small structures and the impact of process variations lead to a decrease in reliability of many modules in a chip. Focusing on buses, crosstalk and soft errors may impair the integrity of data and control signals. Error correcting schemes based on error detecting and error correcting codes are a feasible solution to this problem. These schemes use redundancy to protect the transmitted data on the bus. The redundancy is either information redundancy or temporal redundancy via retransmission of data. Error correcting codes rely on information redundancy. Temporal redundancy is used in error detection and retransmission schemes.
In this talk well known and theoretically proved error detecting and correcting schemes are evaluated in an AMBA bus setup.

Encoding by making phase shifter programmable

The increasing complexity of digital circuits necessitates the development of new test methods that could maintain low costs of test by offering better efficiencies compared to available solutions.
In most of the schemes, multiple scan chains are employed to guarantee acceptable test application time. This necessitates the use of two dimensional test pattern generation that can load the scan chains in parallel.
A phase shifter is used to overcome the problem of structural dependencies introduced by test generator(e.g: LFSR). For test pattern encoding, reseeding and test set embedding have been proven efficient and are widely used in industry to reduce test costs.
In this talk i will present initial analysis and design that shows the potential of an efficient encoding scheme by making phase shifter programmable.

Restrict Encoding for Mixed--Mode BIST

Programmable mixed--mode BIST schemes combine pseudo--random pattern testing and deterministic test. This talk presents a synthesis technique for a mixed--mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50% hardware costs compared with the best schemes known so far while complete programmability is still preserved.

Efficient programmable deterministic self-test

Mixed-mode BIST is attractive because of offering high test quality with moderate hardware overhead. Available mixed-mode schemes are a variation of self-test methods known as reseeding and test set embedding. Reseeding is programmable but requires significant storage while test set embedding is efficient in terms of test information storage but lacks programmability as the information is stored hardwired. In order to optimize quality and cost for rapidly growing circuits, new self-test schemes are required that can exploit the synergy between reseeding and test set embedding. While testing a circuit, full fault coverage and programmability are always desired but hardware overhead and test time might have varying acceptable levels under varying applications. In this talk, the basic ideas and experimental results for three new mixed-mode self-test methods would be presented that offer different trade offs between hardware overhead and test time while maintaining full fault coverage and programmability.

Low Power Test Planning for Arbitrary Transition Test Clock Schemes

Transition tests are launched using shift or capture clocks, and tailored at-speed tests are using arbitrary sequences of the two. These complex clocking schemes make low power test planning more difficult and require a sequential circuit representation. Sequential circuits are often mapped to numerous graph representations in modern EDA tools, such as circuit and S-graphs.

This talk presents a consistent way to generate all of these graphs such that the final graphs reflect the circuit behavior under a given clock sequence. The method is used to generate the graphs required for low-power built-in self-test planning. Experimental results for a set of industrial circuits show that even rather complex test clocking schemes can be subject of an efficient low power test plan.

Fault Diagnosis in NoC Switches

Network-on-Chip (NoC) is an interconnect infrastructure to solve the complexity problem of traditional bus interconnects and meet the communication requirements of the large SoCs. As designers try to utilize NoC benefits in design methodologies, test engineers are also working on various test aspects in the NoC architectures. In this work, we propose a diagnosis procedure for NoC switches. The procedure considers the impact of each potential defect on the switch functionality. The main functionality of the switch is summarized in the routing of the incoming packets to the appropriate output ports. In addition, data path part of the switch transports incoming data packets to the determined output ports. Our diagnosis method specifies the faulty routing paths according to the potential defects. Also, the method diagnoses the impact of a potential defect in data path. With regard to the determined faulty behavior we infer performance of the switch even in the presence of fault.

Soft Error Correction in Embedded Memories

In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. In arrays, error correcting coding is the dominant technique to achieve acceptable soft-error rates. For low power applications, often latches are clock gated and have to retain their states during longer periods while miniaturization has led to elevated susceptibility and further increases the need for protection.
This talk presents a correction scheme that is able to recover from soft-errors. After the fault occurence is detected the fault location is determined. Flipping the bit holding the wrong value due to the soft-error then recovers the internal state. The implementation of the bit-fixing latch is shown together with results regarding the introduced latency and area overheads.
Experimental results for the complete scheme show the feasability and the advantages against other protection schemes.

C++ basiertes Framework für die Entwurfsautomatisierung (SOPRA)

T.B.A.

GaP: GPU and PPSFP

In dieser Studienarbeit soll ausgehend von einem existierenden Fehlersimulator (Ata- lanta PPFSP) eine parallelisierte Version entwickelt werden, die durch GPGPUs beschleu- nigt wird. Dazu soll zunächst untersucht werden, welche Teile des Fehlersimulators sich effizient parallelisieren lassen. Als nächster Schritt sollen diese Teile auf eine GPGPU portiert werden und eine erste Analyse, welche die Auswirkung der Leistungssteigerung zeigt, erstellt werden.

State of the Art Approaches for Reliability Assessment of Combinational Logic Circuits - Common Assumptions and Inherent Fallacies

The reliability of combinational logic circuits is gaining more and more attention, as the current technology suffers from an increasing susceptibility to process variations and environmental factors. What is more, some new, inherently unreliable technologies emerge. Therefore, there is a growing need for methods that would allow to assess the reliability of combinational circuits taking into account realistic fault models, operating conditions, and possibly aging effects as well.
In this presentation I will introduce the state of the art in the reliability analysis of combinational circuits. Existing methods will be introduced together with their justification, area of application and analysis of common shortcomings. The reasoning will be supported by experimental results acquired on benchmark circuits.