This lecture covers advanced concepts in computer architecture. Beside classical concepts like processor design and manufacturing, performance evaluation and optimization, and computer arithmetic new trends are discussed like low power design. Low power design is essential in mobile computing and communication which is expected to be a dominating application of microprocessors in a few years.

Computation power is increasing by exploiting parallelism on all levels of computation. In this course we will discuss instruction level parallelism, thread level parallelism and multiprocessor systems.

The lecture provides a solid background for the courses:

• Design & Test of Systems-on-a-Chip
• Hardware Verification
• Self-Testable Systems
• Fault Tolerant Systems

News

The results of the examination are available at our institute. Exam discussion will take place on friday, september 28th 9:00-10:00 in our seminar room ITI-3.175.

Course Information

INFOTECH: 3L+1E, 3rd semester course.

Staff

• Lecture: Prof. H.-J. Wunderlich
• Exercises, Contact: Dipl.-Inf Stefan Holst office: 3.164, Pfaffenwaldring 47

Schedule

• Mondays, 15:45-17:15, Lecture in room V38.03
• Thursdays, 15:45-17:15, Lecture/Exercises in room V38.03

Material

Here you can download the latest revisions of the lecture slides and additional material using login and password given in the first lecture. If you find any errors or typos, drop me a mail. I'll correct them and publish new revisions here.

• Chapter 1: Scope of Computer Architecture (Rev 1)
• Chapter 2: Technology (Rev 1)
  • Additional slides on manufacturing, test and silicon debug
  • Problem Sheet
• Chapter 3: Power and Performance (Rev 2)
  • Singh, K.J.; Wang, A.R.; Brayton, R.K.; Sangiovanni-Vincentelli, A.: Timing Optimization of Combinational Logic Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on, Vol., Iss., 7-10 Nov 1988, pp 282-285.
  • McGeer, P.C.; Brayton, R.K.; Sangiovanni-Vincentelli, A.L.; Sahni, S.K.: Performance Enhancement Through the Generalized Bypass Transform Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp 184-187.
  • Keutzer, K.; Malik, S.; Saldanha, A.: Is Redundancy Necessary to Reduce Delay? Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.10, Iss.4, Apr 1991, pp 427-435.
  • Berman, C.L.; Hathaway, D.J.; LaPaugh, A.S.; Trevillyan, L.H.: Efficient Techniques for Timing Correction Circuits and Systems, 1990., IEEE International Symposium on, Vol., Iss., 1-3 May 1990, pp 415-419, vol.1.
  • Touati, H.J.; Savoj, H.; Brayton, R.K.: Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp. 188-191.
  • Eugene L. Lawler, Karl N. Levitt, James Turner: Module Clustering to Minimize Delay in Digital Networks IEEE Trans. on Computers, Vol.C-18, Number 1, pp. 47-57, Jan 1969.
  • Problem Sheet 1
  • Problem Sheet 2
• Chapter 4: Technology Scaling (Rev 2)
  • Gonzalez, R.; Gordon, B.M.; Horowitz, M.A.: Supply and Threshold Voltage Scaling for Low Power CMOS Solid-State Circuits, IEEE Journal of, Vol.32, Iss.8, Aug 1997, pp 1210-1216.
• Chapter 5: Computer Arithmetic (Rev 3)
  • Vojin G. Oklobdzija, Earl R. Barnes: Some optimal schemes for ALU implementation in VLSI technology Proc. 7th Symp. Comput. Arithmetic, 1985.
  • Problem Sheet
• Chapter 6: Memory Hierarchy (Rev 1)
• Chapter 7: Parallelism (Rev 1)
  • Problem Sheet
• Script winter term 2005 Warning: This script is outdated and currently not maintained!