Advances in production technology allows billions of transistors using nanometer-sized structures. Designing these systems requires tools that are able to handle both the large size and the complex effects. To model these effects like large process variations leading to varying area and power statistical methods are applied.

Embedded systems depend on a comprehensive design flow - known as hardware-software co-design - in order to achieve better results by clever using a clever system partitioning. As energy consumption is critical with those systems, the ability to accurately estimate the energy in early design stages is crucial to comply with tight energy budgets.

Automatic design needs to make sure that implementations on various abstraction levels in the design flow are functionally equivalent. Methods of validation and formal verification are applied for this task. Test and debug methods ensure that the required product quality is achieved during chip manufacturing.

This seminar will deal with the required tools as well as the underlying algorithms and methods on all abstraction levels.

News

The seminar on July 10th has been moved by one week to July 17th.

Supervisors

• Prof. Dr. Martin Radetzki
• Prof. Dr. H.-J. Wunderlich
• Dipl.-Inf. Tobias Bergmann
• Dipl.-Inf. Stefan Holst

Topics and Schedule

• Tuesdays, 9:45-11:15 in room ITI-3.175 (Pfaffenwaldring 47)

#	Topic	Preliminary Date	Supervisor	Name	Report	Slides
0	First Meeting	17.4.2007				slides
1	Accurate energy estimation using heterogeneous power models	15.5.2007	TB	Bartek Chechelski	report	slides
2	High Level Synthesis for Low-Power	15.5.2007	TB	Ghazanfar Farooq	report	slides
3	Schedule Optimization Using Integer Linear Programming	22.5.2007	MR	Yijun Qu	report	slides
4	Evolutionary Algorithm for Embedded System Topology Optimization	22.5.2007	MR	Haowei Wang	report	slides
5	Dynamic Task Binding Algorithm for Reconfigurable Networks	5.6.2007	MR	Carlos Querada Moldon	report	slides
6	Test program generation for high level validation	5.6.2007	TB	Wei Lai	report	slides
7	Synthesis of RTL Descriptions for Architecture Exploration	26.6.2007	TB	Yazan Boshmaf	report	slides
8	SAT-based unbounded symbolic model checking	26.6.2007	TB	Yuan Zhan	report	slides
9	Logic debug of digital circuits	3.7.2007	SH	Peng Deng	report	slides
10	Transition Fault Test for Scan Circuits	3.7.2007	SH	Zhe Wang	report	slides
11	Logic Diagnosis with improved resolution	17.7.2007	SH	Alejandro Cook	report	slides
12	Optimizations of layout synthesis	9.8.2007	TB	Mohamad Amer Wafai	report	slides

General Material

• Guidelines for the written seminar report
• Guidelines for preparing the talk
• IEEE Citation Style Guide