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unilogo Universität Stuttgart
Institut für Technische Informatik

(Haupt-)Seminar: Algorithms for Design-Automation - Mastering Nanoelectronic Systems


Advances in production technology allows billions of transistors using nanometer-sized structures. Designing these systems requires tools that are able to handle both the large size and the complex effects. To model these effects like large process variations leading to varying area and power statistical methods are applied.

Embedded systems depend on a comprehensive design flow - known as hardware-software co-design - in order to achieve better results by clever using a clever system partitioning. As energy consumption is critical with those systems, the ability to accurately estimate the energy in early design stages is crucial to comply with tight energy budgets.

Automatic design needs to make sure that implementations on various abstraction levels in the design flow are functionally equivalent. Methods of validation and formal verification are applied for this task. Test and debug methods ensure that the required product quality is achieved during chip manufacturing.

This seminar will deal with the required tools as well as the underlying algorithms and methods on all abstraction levels.


The seminar on July 10th has been moved by one week to July 17th.


Topics and Schedule

  • Tuesdays, 9:45-11:15 in room ITI-3.175 (Pfaffenwaldring 47)

#TopicPreliminary DateSupervisorNameReportSlides
0First Meeting17.4.2007 slides
1Accurate energy estimation using heterogeneous power models15.5.2007TBBartek Chechelski report slides
2High Level Synthesis for Low-Power15.5.2007TBGhazanfar Farooq report slides
3Schedule Optimization Using Integer Linear Programming22.5.2007MRYijun Qu report slides
4Evolutionary Algorithm for Embedded System Topology Optimization22.5.2007MRHaowei Wang report slides
5Dynamic Task Binding Algorithm for Reconfigurable Networks5.6.2007MRCarlos Querada Moldon report slides
6Test program generation for high level validation5.6.2007TBWei Lai report slides
7Synthesis of RTL Descriptions for Architecture Exploration26.6.2007TBYazan Boshmaf report slides
8SAT-based unbounded symbolic model checking26.6.2007TBYuan Zhan report slides
9Logic debug of digital circuits3.7.2007SHPeng Deng report slides
10Transition Fault Test for Scan Circuits3.7.2007SHZhe Wang report slides
11Logic Diagnosis with improved resolution17.7.2007SHAlejandro Cook report slides
12Optimizations of layout synthesis9.8.2007TBMohamad Amer Wafai report slides

General Material