Traditional methods of timing analysis for digital circuits are based on
worst-case estimations of gate and network delays which are intervals given as
input parameters to critical path analysis. For current and future technologies
in 90 nm and beyond this approach is no longer feasible and a fundamental
paradigm shift is necessary.
Here, the functionality of essential components is determined by only few
atoms so parameters such as switching speed and power consumption vary heavily.
Reasons for this are not just production tolerance because of resolution
limitations in lithography but also physical quantum effects.
For this reason modern design tools model physical structures and parameter
as random variables, compute random variables for the behavior of components
and finally random variables of the whole system.
In this seminar all steps of modern statistical design, of timing analysis
and of statistical test for highest integrated circuits using data mining will
be covered. Presentations may be given in German or English.