Hanieh Jafarzadeh

Abstract

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since timing variations can invalidate the effectiveness of such patterns, different circuit instances may show a different fault coverage for the same test pattern set. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings introduced by process and temperature-induced variations. The method overcomes the limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations due to the computational complexity. A statistical learning scheme maximises the coverage of SDFs in circuits following the variation parameters of a calibrated in- dustrial FinFET transistor model. The method combines efficient ATPG for Transition Faults (TFs) with fast timing-aware fault simulation on GPUs. Simulation experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detection for transition faults, while the fault coverage even increases.

Abstract

Logic Built-In Self-Test (LBIST) with stored de- terministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solu- tion significantly outperforms traditional N-detect for transition faults in terms of test set size, test application time and fault efficiency.

Abstract

It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into Stuck-at-faults. It is often overlooked that Vmin testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vmin is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first test pattern generation algorithm specifically tuned for Vmin testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage.

Abstract

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectivity of such patterns, different circuit instances may show a different fault coverage. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the complexity limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations. A statistical learning scheme maximises the coverage of SDFs in an entire circuit population following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults with fast timing-aware fault simulation on GPUs. Experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detect while the fault coverage even increases compared to both N-detect and timing-aware ATPG

Abstract

The Preconditioned Conjugate Gradient (PCG) method is well-established for solving linear equations systems. Running the PCG method on a hardware accelerator ensures fast and efficient computation. At the same time, each hardware accelerator may be slightly different due to process variability or aging. To handle the variability, a rather pessimistic frequency selection for the whole population of accelerators is often utilized. Increasing the frequency may improve the performance but may also increase the risk of computational errors, affect the convergence of PCG or even corrupt the PCG results. In this paper, we present a method to determine the frequency for each hardware accelerator instance which optimizes the execution time and the energy efficiency of the PCG method. First, a technique is presented to analyze the error resilience of a PCG algorithm to overclocking. Based on the analysis results, we increase the frequency to speed up the convergence while keeping the error rate below the required threshold.

Abstract

Many applications from Artificial Intelligence (AI) and Scientific Computing rely on efficient algorithms for solving large systems of linear equations. The Preconditioned Conjugate Gradient (PCG) algorithm is a promising option and it is a perfect candidate to be executed on specialized hardware accelerators widely used in AI. Hardware accelerators, like other modern devices, are prone to process variations. A conventional approach to handle the variability is to use pessimistic guard�bands for all the devices within the population, which implies that the best and even the average accelerators are slowed down significantly. Since the PCG algorithm is inherently error resilient to some extent, it may also tolerate an error rate increase due to overclocking. On another side, increasing the frequency may increase the total execution time if more arithmetic operations are needed until the convergence. This paper presents a method to ensure efficient computing on each hardware accelerator instance running the PCG algorithm. A cross-layer approach identifies an optimized frequency that minimizes the total time to complete the PCG algorithm. Simple high-level checks ensure the quality of the solution. Experimental results validate the feasibility of the developed approach for large systems of linear equations.

Abstract

System health monitoring is an integral concept that involves observing, evaluating, and adapting the system behavior under varying operating conditions. The data can be collected from embedded instruments throughout the lifetime. Various techniques, including machine learning, have to be used to analyze the data and adapt the underlying system behavior. At the same time, the behavior of modern devices is affected by different types of variations. In order to develop an efficient and precise health monitoring scheme, the underlying analysis and adaptation techniques must be robust even in the presence of those variations. This contribution explores various strategies for overcoming this challenge across the system stack.