| Time: | May 9, 2019 |
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15:00-16:00, ITI-Seminar room 3.175,
Institute of Computer Architecture and Computer Engineering
Concurrent error detection (CED) techniques play important roles for mission-critical applications. In recent years, a new CED method which relies on the existing invariant relationships between wires inside the circuit, called implications, has been proposed. It has been shown that this method has outstanding flexibility and advantages on both online and offline applications. However, the induced pin-count overhead greatly increases the hardware cost of implication-based CED. In this presentation, we propose a method to reduce the pin-count overhead while maintaining all the existing advantages.