Herr Prof. Dr. rer. nat. habil.

Ilia Polian

Institutsleiter und Lehrstuhlinhaber Hardwareorientierte Informatik
Institut für Technische Informatik
Hardwareorientierte Informatik

Kontakt

+49 711 685-60764
+49 711 685-88288

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 3.160

Fachgebiet

Research Interests and Activities

  • Hardware-oriented security: Fault-injection attacks; hardware realizations of postquantum cryptography; hardware Trojans; physical unclonable functions
  • Robustness: Test methods for nano and microelectronic circuits; defect modeling; power-aware test; test of embedded SRAMs; reliability and functional safety; safety vs. security
  • Emerging architectures: Stochastic circuits and their use in neuromorphic applications; architectures with memristive components; security aspects of emerging architectures
  • Quantum computing: Design and validation of advanced quantum error-correcting schemes (topological QEC) 

Major Projects

Active Ongoing Collaborations

 

  1. 2019

    1. Toward Error-Correcting Architectures for Cryptographic Circuits Based on Rabii-Keren Codes. Mael Gay; Batya Karp; Osnat Keren and Ilia Polian. Embedded Systems Letters 11, 4 (2019), pp. 115–118.
    2. Automatic construction of fault attacks on cryptographic hardware implementations. Ilia Polian; Maël Gay; Tobias Paxian; Matthias Sauer and Bernd Becker. In Automated Methods in Cryptographic Fault Analysis, Jakub Breier; Xiaolu Hou and Shivam Bhasin (eds.). Springer International Publishing, Cham, 2019, pp. 151–170. DOI: https://doi.org/10.1007/978-3-030-11333-9_6
    3. Secure Composition for Hardware Systems (Dagstuhl Seminar 19301). Divya Arora; Ilia Polian; Francesco Regazzoni and Patrick Schaumont. Dagstuhl Reports 9, 7 (2019), pp. 94–116.
    4. On the Limits of Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In ICRC, 2019, pp. 98–105.
    5. Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support. Maël Gay; Tobias Paxian; Devanshi Upadhyaya; Bernd Becker and Ilia Polian. In FDTC, 2019, pp. 25–32.
    6. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1--2. DOI: https://doi.org/10.1515/itit-2019-0008
    7. Security in Autonomous Systems. Stefan Katzenbeisser; Ilia Polian; Francesco Regazzoni and Marc Stöttinger. In ETS, 2019, pp. 1–8.
    8. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019., 2019, pp. 59--66. DOI: https://doi.org/10.1145/3310273.3323050
    9. Improving Testability and Reliability of Advanced SRAM Architectures. Josef Kinseher; Moritz Völker and Ilia Polian. IEEE Trans. Emerging Topics Comput. 7, 3 (2019), pp. 456–467.
    10. Fault Sensitivity Analysis of Lattice-Based Post-Quantum Cryptographic Components. Felipe Valencia; Ilia Polian and Francesco Regazzoni. In SAMOS, 2019, pp. 107–123.
    11. Hardware-oriented security. Ilia Polian. it - Information Technology 61, 1 (2019), pp. 1–2.
    12. On the maximum function in stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In CF, 2019, pp. 59–66.
  2. 2018

    1. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018., 2018, pp. 173--178. DOI: https://doi.org/10.1145/3229631.3264737
    2. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In 12th European Workshop on Microelectronics Education, EWME 2018, Braunschweig, Germany, September 24-26, 2018, 2018, pp. 59--62. DOI: https://doi.org/10.1109/EWME.2018.8629483
    3. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316--326. DOI: https://doi.org/10.1016/j.micpro.2018.06.009
    4. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018, 2018, pp. 1--6. DOI: https://doi.org/10.1109/DCIS.2018.8681476
    5. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018, 2018, pp. 68--82.
    6. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    7. Test and Reliability Challenges for Approximate Circuitry. Ilia Polian. Embedded Systems Letters 10, 1 (2018), pp. 26--29. DOI: https://doi.org/10.1109/LES.2017.2754446
    8. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1--31:21. DOI: https://doi.org/10.1145/3183345
    9. Quantum era challenges for classical computers. Francesco Regazzoni; Austin G. Fowler and Ilia Polian. In SAMOS, 2018, pp. 173–178.
    10. Hardware-oriented Security in a Computer Science Curriculum. Ilia Polian and Mael Gay. In EWME, 2018, pp. 59–62.
    11. S-box-based random number generation for stochastic computing. Florian Neugebauer; Ilia Polian and John P. Hayes. Microprocessors and Microsystems - Embedded Hardware Design 61, (2018), pp. 316–326.
    12. Security-oriented Code-based Architectures for Mitigating Fault Attacks. Batya Karp; Mael Gay; Osnat Keren and Ilia Polian. In DCIS, 2018, pp. 1–6.
    13. Detection and Correction of Malicious and Natural Faults in Cryptographic Modules. Batya Karp; Maël Gay; Osnat Keren and Ilia Polian. In PROOFS@CHES, 2018, pp. 68–82.
    14. Security: the dark side of approximate computing? Francesco Regazzoni; Cesare Alippi and Ilia Polian. In Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018, pp. 44. DOI: https://doi.org/10.1145/3240765.3243497
    15. Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. Florian Neugebauer; Ilia Polian and John P. Hayes. JETC 14, 2 (2018), pp. 31:1-31:21.
  3. 2017

    1. Building a Better Random Number Generator for Stochastic Computing. Florian Neugebauer; Ilia Polian and John P. Hayes. In Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017, 2017, pp. 1--8. DOI: https://doi.org/10.1109/DSD.2017.29
    2. Framework for quantifying and managing accuracy in stochastic circuit design. Florian Neugebauer; Ilia Polian and John P. Hayes. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 1--6. DOI: https://doi.org/10.23919/DATE.2017.7926949
    3. AutoFault: Towards Automatic Construction of Algebraic Fault Attacks. Jan Burchard; Mael Gay; Ange Salome Messeng Ekossono; Jan Horácek; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2017, Taipei, Taiwan, September 25, 2017, 2017, pp. 65--72. DOI: https://doi.org/10.1109/FDTC.2017.13
    4. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Josef Kinseher; Leonhard Heis and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 852--857. DOI: https://doi.org/10.23919/DATE.2017.7927106
    5. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017, 2017, pp. 194--199. DOI: https://doi.org/10.1109/ASPDAC.2017.7858319
    6. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, 2017, pp. 102--107. DOI: https://doi.org/10.1109/SOCC.2017.8226017
    7. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    8. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, 2017, pp. 1--10. DOI: https://doi.org/10.1109/ETS.2017.7968230
    9. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
    10. Introduction to hardware-oriented security for MPSoCs. Ilia Polian; Francesco Regazzoni and Johanna Sepúlveda. In SoCC, 2017, pp. 102–107.
    11. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In DATE, 2017, pp. 680–685.
    12. Securing the hardware of cyber-physical systems. Francesco Regazzoni and Ilia Polian. In ASP-DAC, 2017, pp. 194–199.
    13. Sensitized path PUF: A lightweight embedded physical unclonable function. Matthias Sauer; Pascal Raiola; Linus Feiten; Bernd Becker; Ulrich Rührmair and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017, pp. 680--685. DOI: https://doi.org/10.23919/DATE.2017.7927076
    14. Counteracting malicious faults in cryptographic circuits. Ilia Polian and Francesco Regazzoni. In ETS, 2017, pp. 1–10.
    15. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Jan Burchard; Ange Salome Messeng Ekossono; Jan Horácek; Mael Gay; Bernd Becker; Tobias Schubert; Martin Kreuzer and Ilia Polian. In IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017, 2017, pp. 7--12. DOI: https://doi.org/10.1109/IVSW.2017.8031537
  4. 2016

    1. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869--1881. DOI: https://doi.org/10.1109/TC.2015.2458869
    2. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In 25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016, 2016, pp. 179--184. DOI: https://doi.org/10.1109/ATS.2016.63
    3. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    4. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, 2016, pp. 984--989.
    5. Detection Performance of MIMO Unique Word OFDM. Victor Tomashevich and Ilia Polian. In WSA 2016, 20th International ITG Workshop on Smart Antennas, Munich, Germany, 9-11 March 2016., 2016, pp. 1--8.
    6. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In 24th European Signal Processing Conference, EUSIPCO 2016, Budapest, Hungary, August 29 - September 2, 2016, 2016, pp. 1623--1627. DOI: https://doi.org/10.1109/EUSIPCO.2016.7760523
    7. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72--93. DOI: https://doi.org/10.4230/DagRep.6.5.72
    8. PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. Matthias Sauer; Bernd Becker and Ilia Polian. IEEE Trans. Computers 65, 6 (2016), pp. 1869–1881.
    9. On Optimal Power-Aware Path Sensitization. Matthias Sauer; Jie Jiang; Sven Reimer; Kohei Miyase; Xiaoqing Wen; Bernd Becker and Ilia Polian. In ATS, 2016, pp. 179–184.
    10. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In ETS, 2016, pp. 1–2.
    11. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Josef Kinseher; Moritz Völker; Leonardo Bonet Zordan and Ilia Polian. In 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, 2016, pp. 1--2. DOI: https://doi.org/10.1109/ETS.2016.7519324
    12. Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher; Leonardo Bonet Zordan; Ilia Polian and Andreas Leininger. In DATE, 2016, pp. 984–989.
    13. Memory error resilient detection for massive MIMO systems. Victor Tomashevich and Ilia Polian. In EUSIPCO, 2016, pp. 1623–1627.
    14. Hardware Security (Dagstuhl Seminar 16202). Osnat Keren; Ilia Polian and Mark M. Tehranipoor. Dagstuhl Reports 6, 5 (2016), pp. 72–93.
  5. 2015

    1. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, 2015, pp. 61:1--61:6. DOI: https://doi.org/10.1145/2744769.2747921
    2. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In Reversible Computation - 7th International Conference, RC 2015,Grenoble, France, July 16-17, 2015, Proceedings, 2015, pp. 139--154. DOI: https://doi.org/10.1007/978-3-319-20860-2_9
    3. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    4. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    5. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, 2015, pp. 61--66. DOI: https://doi.org/10.1109/ATS.2015.18
    6. Design automation challenges for scalable quantum architectures. Ilia Polian and Austin G. Fowler. In DAC, 2015, pp. 61:1-61:6.
    7. A Fully Fault-Tolerant Representation of Quantum Circuits. Alexandru Paler; Ilia Polian; Kae Nemoto and Simon J. Devitt. In RC, 2015, pp. 139–154.
    8. Fault-based attacks on the Bel-T block cipher family. Philipp Jovanovic and Ilia Polian. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, 2015, pp. 601--604.
    9. Formal Vulnerability Analysis of Security Components. Linus Feiten; Matthias Sauer; Tobias Schubert; Victor Tomashevich; Ilia Polian and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 34, 8 (2015), pp. 1358--1369. DOI: https://doi.org/10.1109/TCAD.2015.2448687
    10. On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs. Josef Kinseher; Leonardo Bonet Zordan and Ilia Polian. In ATS, 2015, pp. 61–66.
  6. 2014

    1. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237--238. DOI: https://doi.org/10.1049/iet-cdt.2014.0194
    2. Test digitaler Schaltkreise. Stephan Eggersglüß; Görschwin Fey and Ilia Polian. De Gruyter Oldenbourg, Berlin, Boston.2014.
    3. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d’Aro, Girona, Spain, July 7-9, 2014, 2014, pp. 43--48. DOI: https://doi.org/10.1109/IOLTS.2014.6873670
    4. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847794
    5. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192--202. DOI: https://doi.org/10.1515/itit-2013-1038
    6. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014, 2014, pp. 40--45. DOI: https://doi.org/10.1109/DFT.2014.6962084
    7. Reliability analysis of MIMO channel preprocessing by fault injection. Victor Tomashevich; Christina Gimmler-Dumont; Norbert Wehn and Ilia Polian. In 2014 IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2014, Noordwijk, Netherlands, October 30-31, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/WiSEE.2014.6973066
    8. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014, pp. 1--4. DOI: https://doi.org/10.7873/DATE.2014.137
    9. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    10. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 783.
    11. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 133--138. DOI: https://doi.org/10.1109/VLSID.2014.30
    12. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014, 2014, pp. 56--61. DOI: https://doi.org/10.1109/VLSID.2014.17
    13. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Reversible Computation - 6th International Conference, RC 2014,Kyoto, Japan, July 10-11, 2014. Proceedings, 2014, pp. 189--200. DOI: https://doi.org/10.1007/978-3-319-08494-7_15
    14. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, 2014, pp. 246--249. DOI: https://doi.org/10.1109/DDECS.2014.6868800
    15. Guest Editorial. Ilia Polian and Mark Mohammad Tehranipoor. IET Computers & Digital Techniques 8, 6 (2014), pp. 237–238.
    16. Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. IACR Cryptology ePrint Archive 2014, (2014), pp. 782.
    17. Protecting cryptographic hardware against malicious attacks by nonlinear robust codes. Victor Tomashevich; Yaara Neumeier; Raghavan Kumar; Osnat Keren and Ilia Polian. In DFT, 2014, pp. 40–45.
    18. Software-based Pauli tracking in fault-tolerant quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In DATE, 2014, pp. 1–4.
    19. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
    20. Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware. Raghavan Kumar; Philipp Jovanovic; Wayne P. Burleson and Ilia Polian. In 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2014, Busan, South Korea, September 23, 2014, 2014, pp. 18--28. DOI: https://doi.org/10.1109/FDTC.2014.12
    21. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. Ravi Kanth Uppu; Ravi Tej Uppu; Adit D. Singh and Ilia Polian. In VLSI Design, 2014, pp. 133–138.
    22. SAT-Based Test Pattern Generation with Improved Dynamic Compaction. Alexander Czutro; Sudhakar M. Reddy; Ilia Polian and Bernd Becker. In VLSI Design, 2014, pp. 56–61.
    23. Cross-Level Validation of Topological Quantum Circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In RC, 2014, pp. 189–200.
    24. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Victor Tomashevich; Christina Gimmler-Dumont; Christian Fesl; Norbert Wehn and Ilia Polian. In DDECS, 2014, pp. 246–249.
    25. Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis. Raghavan Kumar; Philipp Jovanovic and Ilia Polian. In IOLTS, 2014, pp. 43–48.
    26. Detection conditions for errors in self-adaptive better-than-worst-case designs. Ilia Polian; Jie Jiang and Adit D. Singh. In ETS, 2014, pp. 1–6.
    27. Hardware security and test: Friends or enemies? Ilia Polian. it - Information Technology 56, 4 (2014), pp. 192–202.
    28. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In ETS, 2014, pp. 1–6.
  7. 2013

    1. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    2. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, 2013, pp. 12--17. DOI: https://doi.org/10.1109/DDECS.2013.6549781
    3. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81--88. DOI: https://doi.org/10.1109/MDT.2012.2230297
    4. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013, pp. 95--100. DOI: https://doi.org/10.1109/DFT.2013.6653589
    5. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, 2013, pp. 448--453. DOI: https://doi.org/10.7873/DATE.2013.100
    6. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013, pp. 533--539. DOI: https://doi.org/10.1109/ASPDAC.2013.6509651
    7. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, 2013, pp. 1--6. DOI: https://doi.org/10.1109/LATW.2013.6562657
    8. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Aza\"ıs; Michel Renovell and Ilia Polian. In 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, 2013, pp. 177--182. DOI: https://doi.org/10.1109/ATS.2013.41
    9. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    10. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013, 2013, pp. 1. DOI: https://doi.org/10.1109/VTS.2013.6548944
    11. Fault-based attacks on cryptographic hardware. Ilia Polian and Martin Kreuzer. In DDECS, 2013, pp. 12–17.
    12. SAT-Based Analysis of Sensitizable Paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. IEEE Design & Test 30, 4 (2013), pp. 81–88.
    13. Approximate simulation of circuits with probabilistic behavior. Alexandru Paler; Josef Kinseher; Ilia Polian and John P. Hayes. In DFTS, 2013, pp. 95–100.
    14. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Matthias Sauer; Sven Reimer; Tobias Schubert; Ilia Polian and Bernd Becker. In DATE, 2013, pp. 448–453.
    15. Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. M. Aparicio; Mariane Comte; Florence Azaïs; Michel Renovell; J. Jiang; Ilia Polian and Bernd Becker. In LATW, 2013, pp. 1–6.
    16. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. J. Jiang; M. Aparicio; Mariane Comte; Florence Azaïs; Michel Renovell and Ilia Polian. In Asian Test Symposium, 2013, pp. 177–182.
    17. Multi-Stage Fault Attacks on Block Ciphers. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2013, (2013), pp. 778.
    18. Special session 12A: Hot topic counterfeit IC identification: How can test help? Ilia Polian and Mohammad Tehranipoor. In VTS, 2013, pp. 1.
    19. Provably optimal test cube generation using quantified boolean formula solving. Matthias Sauer; Sven Reimer; Ilia Polian; Tobias Schubert and Bernd Becker. In ASP-DAC, 2013, pp. 533–539.
  8. 2012

    1. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 418--423. DOI: https://doi.org/10.1109/DATE.2012.6176507
    2. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233026
    3. Digital Tarnkappe: Stealth Technology for the Internet of Things: Symposium des Centre for Security and Society. Bernd Becker; Günter Müller and Ilia Polian. . 2012, pp. 139–149. DOI: https://doi.org/10.5771/9783845238098-139
    4. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    5. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012, 2012, pp. 30--36. DOI: https://doi.org/10.1145/2429384.2429391
    6. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, 2012, pp. 181--187. DOI: https://doi.org/10.1145/2765491.2765524
    7. \#SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012, 2012, pp. 49--54. DOI: https://doi.org/10.1109/DFT.2012.6378198
    8. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012, 2012, pp. 170--175. DOI: https://doi.org/10.1109/VTS.2012.6231098
    9. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012, 2012, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2012.6401550
    10. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, 2012, pp. 181--186. DOI: https://doi.org/10.1109/ASPDAC.2012.6164942
    11. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    12. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In Constructive Side-Channel Analysis and Secure Design - Third InternationalWorkshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings, 2012, pp. 120--134. DOI: https://doi.org/10.1007/978-3-642-29912-4_10
    13. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, 2012, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2012.6233027
    14. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    15. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    16. On the optimality of K longest path generation algorithm under memory constraints. Jie Jiang; Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In DATE, 2012, pp. 418–423.
    17. Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking. Ilia Polian. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 49. DOI: https://doi.org/10.1109/ATS.2012.88
    18. Small-delay-fault ATPG with waveform accuracy. Matthias Sauer; Alexander Czutro; Ilia Polian and Bernd Becker. In ICCAD, 2012, pp. 30–36.
    19. Synthesis of topological quantum circuits. Alexandru Paler; Simon J. Devitt; Kae Nemoto and Ilia Polian. In NANOARCH, 2012, pp. 181–187.
    20. #SAT-based vulnerability analysis of security components - A case study. Linus Feiten; Matthias Sauer; Tobias Schubert; Alexander Czutro; Eberhard Böhl; Ilia Polian and Bernd Becker. In DFT, 2012, pp. 49–54.
    21. Functional test of small-delay faults using SAT and Craig interpolation. Matthias Sauer; Stefan Kupferschmid; Alexander Czutro; Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In ITC, 2012, pp. 1–8.
    22. An Algebraic Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. IACR Cryptology ePrint Archive 2012, (2012), pp. 400.
    23. A Fault Attack on the LED Block Cipher. Philipp Jovanovic; Martin Kreuzer and Ilia Polian. In COSADE, 2012, pp. 120–134.
    24. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    25. Cross-level protection of circuits against faults and malicious attacks. Victor Tomashevich; Sudarshan Srinivasan; Fabian Foerg and Ilia Polian. In 18th IEEE International On-Line Testing Symposium, IOLTS 2012, Sitges, Spain, June 27-29, 2012, 2012, pp. 150--155. DOI: https://doi.org/10.1109/IOLTS.2012.6313862
    26. Multi-conditional SAT-ATPG for power-droop testing. Alexander Czutro; Matthias Sauer; Ilia Polian and Bernd Becker. In European Test Symposium, 2012, pp. 1–6.
    27. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Alexander Czutro; Matthias Sauer; Tobias Schubert; Ilia Polian and Bernd Becker. In VTS, 2012, pp. 170–175.
    28. Detection and diagnosis of faulty quantum circuits. Alexandru Paler; Ilia Polian and John P. Hayes. In ASP-DAC, 2012, pp. 181–186.
    29. On the quality of test vectors for post-silicon characterization. Matthias Sauer; Alexander Czutro; Bernd Becker and Ilia Polian. In European Test Symposium, 2012, pp. 1–6.
  9. 2011

    1. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011, 2011, pp. 108--113. DOI: https://doi.org/10.1109/ATS.2011.43
    2. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    3. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54--63. DOI: https://doi.org/10.1109/MDT.2010.120
    4. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011, 2011, pp. 93--98. DOI: https://doi.org/10.1109/DDECS.2011.5783055
    5. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, 2011, pp. 944--949. DOI: https://doi.org/10.1109/DATE.2011.5763153
    6. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 104--110. DOI: https://doi.org/10.1109/IOLTS.2011.5993819
    7. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537--547. DOI: https://doi.org/10.1109/TDSC.2010.26
    8. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    9. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece, 2011, pp. 182--185. DOI: https://doi.org/10.1109/IOLTS.2011.5993836
    10. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    11. Efficient SAT-Based Search for Longest Sensitisable Paths. Matthias Sauer; Jie Jiang; Alejandro Czutro; Ilia Polian and Bernd Becker. In Asian Test Symposium, 2011, pp. 108–113.
    12. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    13. Selective Hardening: Toward Cost-Effective Error Tolerance. Ilia Polian and John P. Hayes. IEEE Design & Test of Computers 28, 3 (2011), pp. 54–63.
    14. SAT-based analysis of sensitisable paths. Matthias Sauer; Alexander Czutro; Tobias Schubert; Stefan Hillebrecht; Ilia Polian and Bernd Becker. In DDECS, 2011, pp. 93–98.
    15. Adaptive voltage over-scaling for resilient applications. Philipp Klaus Krause and Ilia Polian. In DATE, 2011, pp. 944–949.
    16. Estimation of component criticality in early design steps. Matthias Sauer; Alejandro Czutro; Ilia Polian and Bernd Becker. In IOLTS, 2011, pp. 104–110.
    17. Modeling and Mitigating Transient Errors in Logic Circuits. Ilia Polian; John P. Hayes; Sudhakar M. Reddy and Bernd Becker. IEEE Trans. Dependable Sec. Comput. 8, 4 (2011), pp. 537–547.
    18. Tomographic Testing and Validation of Probabilistic Circuits. Alexandru Paler; Armin Alaghi; Ilia Polian and John P. Hayes. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 63--68. DOI: https://doi.org/10.1109/ETS.2011.43
    19. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
    20. An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. Matthias Sauer; Victor Tomashevich; Jörg Müller; Matthew D. T. Lewis; Andreas Spilla; Ilia Polian; Bernd Becker and Wolfram Burgard. In IOLTS, 2011, pp. 182–185.
    21. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813–1826.
  10. 2010

    1. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    2. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, 2010, pp. 130. DOI: https://doi.org/10.1109/VTS.2010.5469594
    3. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189--194. DOI: https://doi.org/10.1524/itit.2010.0590
    4. Fault Modeling for Simulation and ATPG. Bernd Becker and Ilia Polian. In Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault. Springer Netherlands, Dordrecht, 2010, pp. 105--131. DOI: https://doi.org/10.1007/978-90-481-3282-9_4
    5. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    6. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185--202. DOI: https://doi.org/10.1007/s10766-009-0124-7
    7. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, 2010, pp. 376--381. DOI: https://doi.org/10.1109/EWDTS.2010.5742135
    8. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326--338. DOI: https://doi.org/10.1166/jolpe.2010.1075
    9. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    10. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    11. Special session 4B: Panel low-power test and noise-aware test: Foes or friends? Ilia Polian. In VTS, 2010, pp. 130.
    12. Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien). Ilia Polian and Bernd Becker. it - Information Technology 52, 4 (2010), pp. 189–194.
    13. Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. International Journal of Parallel Programming 38, 3–4 (2010), pp. 185–202.
    14. Advanced modeling of faults in Reversible circuits. Ilia Polian and John P. Hayes. In EWDTS, 2010, pp. 376–381.
    15. Power Supply Noise: Causes, Effects, and Testing. Ilia Polian. J. Low Power Electronics 6, 2 (2010), pp. 326–338.
  11. 2009

    1. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan, 2009, pp. 187--190. DOI: https://doi.org/10.1109/ATS.2009.31
    2. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1--56:21. DOI: https://doi.org/10.1145/1562514.1596831
    3. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    4. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, 2009, pp. 21--26. DOI: https://doi.org/10.1109/VTS.2009.57
    5. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal, 2009, pp. 269--274. DOI: https://doi.org/10.1109/IOLTS.2009.5196027
    6. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    7. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 682--687. DOI: https://doi.org/10.1109/DATE.2009.5090752
    8. Dynamic Compaction in SAT-Based ATPG. Alejandro Czutro; Ilia Polian; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In Asian Test Symposium, 2009, pp. 187–190.
    9. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. Alejandro Czutro; Ilia Polian; Matthew D. T. Lewis; Piet Engelke; Sudhakar M. Reddy and Bernd Becker. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, 2009, pp. 227--232. DOI: https://doi.org/10.1109/VLSI.Design.2009.20
    10. An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. Nicolas Houarche; Mariane Comte; Michel Renovell; Alejandro Czutro; Piet Engelke; Ilia Polian and Bernd Becker. In VTS, 2009, pp. 21–26.
    11. ATPG-based grading of strong fault-secureness. Marc Hunger; Sybille Hellebrand; Alejandro Czutro; Ilia Polian and Bernd Becker. In IOLTS, 2009, pp. 269–274.
    12. Reducing temperature variability by routing heat pipes. Kunal P. Ganeshpure; Ilia Polian; Sandip Kundu and Bernd Becker. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009, pp. 63--68. DOI: https://doi.org/10.1145/1531542.1531560
    13. SUPERB: Simulator utilizing parallel evaluation of resistive bridges. Piet Engelke; Bernd Becker; Michel Renovell; Jürgen Schlöffel; Bettina Braitling and Ilia Polian. ACM Trans. Design Autom. Electr. Syst. 14, 4 (2009), pp. 56:1-56:21.
    14. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Viacheslav Izosimov; Ilia Polian; Paul Pop; Petru Eles and Zebo Peng. In DATE, 2009, pp. 682–687.
  12. 2008

    1. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, 2008, pp. 257--262. DOI: https://doi.org/10.1109/ISVLSI.2008.22
    2. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008, pp. 181--186. DOI: https://doi.org/10.1109/VTS.2008.30
    3. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Piet Engelke; Ilia Polian; Michel Renovell; Sandip Kundu; Bharath Seshadri and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 27, 2 (2008), pp. 327--338. DOI: https://doi.org/10.1109/TCAD.2007.913382
    4. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 113--118. DOI: https://doi.org/10.1109/ETS.2008.19
    5. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, 2008, pp. 32--41. DOI: https://doi.org/10.1109/DSN.2008.4630068
    6. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    7. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 263--271. DOI: https://doi.org/10.1109/DFT.2008.26
    8. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2008.4700642
    9. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, 2008, pp. 263--266. DOI: https://doi.org/10.1109/DDECS.2008.4538798
    10. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    11. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, 2008, pp. 245--253. DOI: https://doi.org/10.1109/DFT.2008.20
    12. Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. Ilia Polian; Sudhakar M. Reddy and Bernd Becker. In ISVLSI, 2008, pp. 257–262.
    13. A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. Alejandro Czutro; Nicolas Houarche; Piet Engelke; Ilia Polian; Mariane Comte; Michel Renovell and Bernd Becker. In European Test Symposium, 2008, pp. 113–118.
    14. A study of cognitive resilience in a JPEG compressor. Damian Nowroth; Ilia Polian and Bernd Becker. In DSN, 2008, pp. 32–41.
    15. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, 2008, pp. 628--633. DOI: https://doi.org/10.1109/DATE.2008.4484747
    16. Selective Hardening of NanoPLA Circuits. Ilia Polian and Wenjing Rao. In DFT, 2008, pp. 263–271.
    17. Resistive Bridging Fault Simulation of Industrial Circuits. Piet Engelke; Ilia Polian; Jürgen Schlöffel and Bernd Becker. In DATE, 2008, pp. 628–633.
    18. Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. Stefan Hillebrecht; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In ITC, 2008, pp. 1–10.
    19. Diagnosis of Realistic Defects Based on the X-Fault Model. Ilia Polian; Kohei Miyase; Yusuke Nakamura; Seiji Kajihara; Piet Engelke; Bernd Becker; Stefan Spinner and Xiaoqing Wen. In DDECS, 2008, pp. 263–266.
    20. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    21. On Reducing Circuit Malfunctions Caused by Soft Errors. Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang and Bernd Becker. In DFT, 2008, pp. 245–253.
    22. Automatic Test Pattern Generation for Interconnect Open Defects. Stefan Spinner; Ilia Polian; Piet Engelke; Bernd Becker; Martin Keim and Wu-Tung Cheng. In VTS, 2008, pp. 181–186.
  13. 2007

    1. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, 2007, pp. 249--255. DOI: https://doi.org/10.1109/VTS.2007.13
    2. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    3. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
    4. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, 2007, pp. 201--202. DOI: https://doi.org/10.1109/IOLTS.2007.38
    5. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276--284. DOI: https://doi.org/10.1109/MDT.2007.77
    6. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. Ilia Polian and Hideo Fujiwara. J. Electronic Testing 23, 5 (2007), pp. 445--455. DOI: https://doi.org/10.1007/s10836-007-5013-7
    7. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    8. Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors. Stefan Spinner; J. Bartholomeyczik; Bernd Becker; M. Doelle; Oliver Paul; Ilia Polian; R. Roth; K. Seitz and Patrick Ruther. CoRR abs/0711.3289, (2007).
    9. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. CoRR abs/0710.4670, (2007).
    10. Identification of Critical Errors in Imaging Applications. Ilia Polian; Damian Nowroth and Bernd Becker. In IOLTS, 2007, pp. 201–202.
    11. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. IEEE Design & Test of Computers 24, 3 (2007), pp. 276–284.
    12. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    13. An Analysis Framework for Transient-Error Tolerance. John P. Hayes; Ilia Polian and Bernd Becker. In VTS, 2007, pp. 249–255.
  14. 2006

    1. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006, pp. 105--110. DOI: https://doi.org/10.1109/IOLTS.2006.10
    2. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    3. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme;  DFG-Project – Test and Reliability of Nano-Electronic Systems. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. it - Information Technology 48, 5 (2006), pp. 304--311. DOI: https://doi.org/10.1524/itit.2006.48.5.304
    4. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, 2006, pp. 274--279. DOI: https://doi.org/10.1109/DFT.2006.40
    5. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006, pp. 243--250. DOI: https://doi.org/10.1109/ICCD.2006.4380824
    6. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, 2006, pp. 15--20. DOI: https://doi.org/10.1109/DDECS.2006.1649563
    7. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, July 4, 2006, Dresden, Germany, 2006.
    8. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181--2192. DOI: https://doi.org/10.1109/TCAD.2006.871626
    9. Automatic Test Pattern Generation for Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. J. Electronic Testing 22, 1 (2006), pp. 61--69. DOI: https://doi.org/10.1007/s10836-006-6392-x
    10. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006, pp. 1039--1044. DOI: https://doi.org/10.1109/DATE.2006.243927
    11. An Improved Technique for Reducing False Alarms Due to Soft Errors. Sandip Kundu and Ilia Polian. In IOLTS, 2006, pp. 105–110.
    12. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme;  DFG-Project – Test and Reliability of Nano-Electronic Systems. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. it - Information Technology 48, 5 (2006), pp. 304--311. DOI: https://doi.org/10.1524/itit.2006.48.5.304
    13. Low-Cost Hardening of Image Processing Applications Against Soft Errors. Ilia Polian; Bernd Becker; Masato Nakasato; Satoshi Ohtake and Hideo Fujiwara. In DFT, 2006, pp. 274–279.
    14. Power Droop Testing. Ilia Polian; Alejandro Czutro; Sandip Kundu and Bernd Becker. In ICCD, 2006, pp. 243–250.
    15. Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. Jochen Eisinger; Ilia Polian; Bernd Becker; Alexander Metzner; Stephan Thesing and Reinhard Wilhelm. In DDECS, 2006, pp. 15–20.
    16. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193–202.
    17. A Definition and Classification of Timing Anomalies. Jan Reineke; Björn Wachter; Stephan Thesing; Reinhard Wilhelm; Ilia Polian; Jochen Eisinger and Bernd Becker. In WCET, 2006.
    18. Simulating Resistive-Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. IEEE Trans. on CAD of Integrated Circuits and Systems 25, 10 (2006), pp. 2181–2192.
    19. Functional constraints vs. test compression in scan-based delay testing. Ilia Polian and Hideo Fujiwara. In DATE, 2006, pp. 1039–1044.
  15. 2005

    1. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications). Ilia Polian. it - Information Technology 47, 3 (2005), pp. 172--174. DOI: https://doi.org/10.1524/itit.47.3.172.65613
    2. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005, pp. 1124--1129. DOI: https://doi.org/10.1109/DATE.2005.144
    3. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 266--271. DOI: https://doi.org/10.1109/ATS.2005.83
    4. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
    5. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, pp. 422--427. DOI: https://doi.org/10.1109/ATS.2005.9
    6. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, 2005, pp. 343--348. DOI: https://doi.org/10.1109/VTS.2005.72
    7. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
    8. Modeling Feedback Bridging Faults with Non-Zero Resistance. Ilia Polian; Piet Engelke; Michel Renovell and Bernd Becker. J. Electronic Testing 21, 1 (2005), pp. 57--69. DOI: https://doi.org/10.1007/s10836-005-5287-6
    9. Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. Ilia Polian; Sandip Kundu; Jean Marc Gallière; Piet Engelke; Michel Renovell and Bernd Becker. In VTS, 2005, pp. 343–348.
    10. Evolutionary Optimization in Code-Based Test Compression. Ilia Polian; Alejandro Czutro and Bernd Becker. In DATE, 2005, pp. 1124–1129.
    11. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Sandip Kundu; Piet Engelke; Ilia Polian and Bernd Becker. In Asian Test Symposium, 2005, pp. 266–271.
    12. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
    13. A Family of Logical Fault Models for Reversible Circuits. Ilia Polian; Thomas Fiehn; Bernd Becker and John P. Hayes. In Asian Test Symposium, 2005, pp. 422–427.
    14. Transient fault characterization in dynamic noisy environments. Ilia Polian; John P. Hayes; Sandip Kundu and Bernd Becker. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, 2005, pp. 10. DOI: https://doi.org/10.1109/TEST.2005.1584070
  16. 2004

    1. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181--197. DOI: https://doi.org/10.1023/B:JETT.0000023681.25483.59
    2. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, 2004, pp. 171--178. DOI: https://doi.org/10.1109/VTEST.2004.1299240
    3. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
    4. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    5. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In 9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004, 2004, pp. 160--165. DOI: https://doi.org/10.1109/ETSYM.2004.1347652
    6. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004, 2004, pp. 65--75.
    7. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. Polian Ilia. In VDI Fortschritt-Berichte. VDI-Verlag, Düsseldorf, 2004, pp. 218.
    8. Testing for Missing-Gate Faults in Reversible Circuits. John P. Hayes; Ilia Polian and Bernd Becker. In 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, 2004, pp. 100--105. DOI: https://doi.org/10.1109/ATS.2004.84
    9. Automatic test pattern generation for resistive bridging faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In European Test Symposium, 2004, pp. 160–165.
    10. Scalable Delay Fault BIST for Use with Low-Cost ATE. Ilia Polian and Bernd Becker. J. Electronic Testing 20, 2 (2004), pp. 181–197.
    11. The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. Piet Engelke; Ilia Polian; Michel Renovell; Bharath Seshadri and Bernd Becker. In VTS, 2004, pp. 171–178.
    12. Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems. Bernd Becker; Markus Behle; Friedrich Eisenbrand; Martin Fränzle; Marc Herbstritt; Christian Herde; Jörg Hoffmann; Daniel Kröning; Bernhard Nebel; Ilia Polian and Ralf Wimmer. In MBMV, 2004, pp. 65–75.
  17. 2003

    1. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423
    2. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003, 2003, pp. 164--173.
    3. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, 2003, pp. 11184--11185. DOI: https://doi.org/10.1109/DATE.2003.10051
    4. Reducing ATE Cost in System-on-Chip Test. Ilia Polian and Bernd Becker. In IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 2003, pp. 337--342.
    5. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25--44. DOI: https://doi.org/10.1016/S0167-9260(03)00003-8
    6. Simulating Resistive Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 1051--1059. DOI: https://doi.org/10.1109/TEST.2003.1271093
    7. Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting. Jonathan Bradford; Hartmut Delong; Ilia Polian and Bernd Becker. J. Electronic Testing 19, 4 (2003), pp. 387--395. DOI: https://doi.org/10.1023/A:1024635824944
    8. On non-standard fault models for logic digital circuits. Ilia Polian. In Ausgezeichnete Informatikdissertationen 2003, 2003, pp. 169--178.
    9. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. J. Electronic Testing 19, 1 (2003), pp. 37--48. DOI: https://doi.org/10.1023/A:1021991828423
    10. Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. Ilia Polian; Bernd Becker and Sudhakar M. Reddy. In DATE, 2003, pp. 11184–11185.
    11. The Case for 2-POF. Ilia Polian; Wolfgang Günther and Bernd Becker. In MBMV, 2003, pp. 164–173.
    12. Pattern-based verification of connections to intellectual property cores. Ilia Polian; Wolfgang Günther and Bernd Becker. Integration 35, 1 (2003), pp. 25–44.
    13. Simulating Resistive Bridging and Stuck-At Faults. Piet Engelke; Ilia Polian; Michel Renovell and Bernd Becker. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, 2003, pp. 1051--1059. DOI: https://doi.org/10.1109/TEST.2003.1271093
    14. On non-standard fault models for logic digital circuits. Ilia Polian. In Ausgezeichnete Informatikdissertationen 2003, 2003, pp. 169--178.
  18. 2002

    1. Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Ilia Polian; Irith Pomeranz and Bernd Becker. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002, pp. 2--14. DOI: https://doi.org/10.1109/ATS.2002.1181677
    2. Stop & Go BIST. Ilia Polian and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 147--151. DOI: https://doi.org/10.1109/OLT.2002.1030198
    3. Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. Ilia Polian; Piet Engelke and Bernd Becker. In 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, 2002, pp. 216--223. DOI: https://doi.org/10.1109/ISMVL.2002.1011092
    4. Sequential n -Detection Criteria: Keep It Simple. Ilia Polian; Martin Keim; Nicolai Mallig and Bernd Becker. In 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, 2002, pp. 189. DOI: https://doi.org/10.1109/OLT.2002.1030213
    5. Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. Ilia Polian; Irith Pomeranz and Bernd Becker. In Asian Test Symposium, 2002, pp. 2–14.
    6. Stop & Go BIST. Ilia Polian and Bernd Becker. In IOLTW, 2002, pp. 147–151.
    7. Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. Ilia Polian; Piet Engelke and Bernd Becker. In ISMVL, 2002, pp. 216–223.
    8. Sequential n -Detection Criteria: Keep It Simple. Ilia Polian; Martin Keim; Nicolai Mallig and Bernd Becker. In IOLTW, 2002, pp. 189.
  19. 2001

    1. Efficient Pattern-Based Verification of Connections to IP Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001, pp. 443--448. DOI: https://doi.org/10.1109/ATS.2001.990324
    2. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. In 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, 2001, pp. 88--93. DOI: https://doi.org/10.1109/VTS.2001.923423
    3. Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Meißen, Germany, February 19-21, 2001, 2001, pp. 111--120.
    4. Efficient Pattern-Based Verification of Connections to IP Cores . Ilia Polian; Wolfgang Günther and Bernd Becker. In Asian Test Symposium, 2001, pp. 443–448.
    5. Efficient Pattern-Based Verification of Connections to Intellectual Property Cores. Ilia Polian; Wolfgang Günther and Bernd Becker. In MBMV (1), 2001, pp. 111–120.
    6. Multiple Scan Chain Design for Two-Pattern Testing. Ilia Polian and Bernd Becker. In VTS, 2001, pp. 88–93.

Teaching and Advising

  • Graduate (Master-level) courses in Stuttgart: «Hardware-oriented Security», «Computer Architecture and Organization», «Electronic Design Automation», «Robust System Design», research-oriented seminars «Hardware-oriented Security», «Emerging Architectures»
  • Undergraduate (Bachelor-level) courses in Stuttgart: «Computer Organization I», «Computer Organization II» (practical)
  • Courses in Passau (before 2017): «Combinational and Sequential Circuits», «Computer Engineering», «Computer Architecture», «Embedded Systems» «Electronic Design Automation», «Robust System Design»
  • Courses in Freiburg (before 2010): «Computer Engineering», «Computer Architecture», «Embedded Systems», «Test and Reliability» 

Teaching-oriented Functions and Contributions

Current Doctoral Students in Stuttgart

  • Sebastian Brandhofer
    Preliminary topic: Synthesis of Robust Quantum Computers
  • Mael Gay
    Preliminary topic: Fault-injection Attacks and Countermeasures
  • Florian Neugebauer
    Preliminary topic: Stochastic Circuits 

Visiting Doctoral Students in Stuttgart

  • Felipe Valencia (August 2018 – July 2019)
    Home institution: Universita della Svizzera Italiana, Lugano (advisor: F. Regazzoni)
    Topic: Hardware Acceleration for Post-quantum Cryptography

     

Doctoral Students Supervised in Nassau

  • Jie Jiang (2010 – 2016)
    Title: Delay Testing in Nanoscale Technology under Process Variations
  • Philipp Jovanovic (2011 – 2015, co-supervised by Prof. Martin Kreuzer, summa cum laude)
    Title: Analysis and Design of Symmetric Cryptographic Algorithms Current employer: EPFL Lausanne
  • Josef Kinseher (2014 – 2018)
    Title: New Methods for Improving Embedded Memory Manufacturing Tests Current employer: Intel Wireless, Munich
  • Alexandru Paler (2010 – 2014)
    Title: Design Methods for Reliable Quantum Circuits Current employer: University of Linz
  • Victor Tomashevich (2010 – 2016)
    Title: Fault Tolerance Aspects of Virtual Massive MIMO Systems

Visiting Doctoral Students in Passau

  • Raghavan Kumar (July – December 2013)
    Home institution: University of Massachusetts, Amherst (advisor: Wayne P. Burleson)
    Topic: Hardware Trojans for fault-based attacks
  • Sudarshan Srinivasan (July – December 2011)
    Home institution: University of Massachusetts, Amherst (advisor: Sandip Kundu)
    Topic: Cross-level protection against faults and attacks

Doctoral Students Co-Supervised in Freiburg (before 2010)

  • Piet Engelke (2003 – 2009, summa cum laude)
    Title: Resistive bridging faults
    Current employer: Infineon Technologies, Munich
  • Stefan Spinner (2005 – 2010, married and changed name to Hillebrecht in 2008)
    Title: Interconnect reliability and test
    Current employer: Advantest, Böblingen
  • Alexander Czutro (2007 – 2013)
    Title: Efficiency and Applications of SAT-Based Test Pattern Generation – Complex fault models and optimisation problems
    Current employer: Besi Switzerland AG
  • Matthias Sauer (2010 – 2013, summa cum laude)
    Title: Testing time – time to test
    Current employer: University of Freiburg
  • Philipp-Klaus Krause (2009 – 2010; moved to University of Frankfurt in 2010)
    Topic: Adaptive voltage over-scaling

 

Brief Biography

Since 10/2017:

Full Professor and Director of ITI, University of Stuttgart, Germany

04/2010 – 10/2017:

Full Professor and Chair of Computer Engineering, University of Passau, Germany

10/2013 – 09/2015:

Dean of the Faculty of Computer Science and Mathematics, University of Passau, Germany

12/2008 – 03/2008:

Managing Director, Freiburg Centre for Security and Society

12/2003 – 03/2010:

Senior postdoctoral researcher (C1) and leader of the sub-group «test and reliability», Computer Architecture Group, University of Freiburg

10/1999 – 11/2003:

Researcher, Computer Architecture Group, University of Freiburg

Degrees

  • Diploma (MSc) 1999
  • Dr. rer. nat. (PhD; summa cum laude) 2003
  • Habilitation (professor's qualification exam) 2008,
    all in Computer Science and from the University of Freiburg
  • Diploma in Economics (with distinction) from the University of Hagen 2008

Longer Research Visits and Internships

04/2016 – 07/2016:

FRIAS Fellow, Freiburg Institute of Advanced Studies, Freiburg, Germany

06/2012 – 07/2012:

Research visitor, University of Michigan, Ann Arbor, USA

05/2005 – 09/2005:

JSPS Visiting Research Fellow, Nara Institute of Science and Technology, Japan

07/1998 – 10/1998:

Intern, IBM Deutschland Entwicklung GmbH, Böblingen, Germany

10/1997 – 03/1998:

Intern, Micronas Intermetall, Freiburg

 

  • Best paper award, IEEE European Test Symposium 2014
  • Best paper award nomination, ACM/IEEE ASP-DAC Conference 2013
  • Best paper award in category «Test», IEEE DDECS Symposium 2011
  • Two papers (from 2004 and 2010) selected for the compendium volume «Best papers 2002–2011 of the IEEE Asian Test Symposium»
  • IEEE Senior Member (since 2007)
  • Ph.D. thesis proposed for German Informatics Society Outstanding Dissertation Award abstract published in «Outstanding Computer Science Dissertations 2003» by German Computer Science Society.
  • Wolfgang-Gentner Award 2004 for outstanding scientific performance of a young researcher (link in German; sponsored by Volksbank Freiburg; co-laureate with Felix Klädtke and Maren Bennewitz).
  • European Champion and Vice World Champion at ACM International Collegiate Programming Contest 1999 (final results and a report in a newspaper)
  • VDI Award 1999 (sponsored by VDI, the German Engineering Association; co-laureate with Immanuel Herrmann and Daniel Fleig)
  • Referent for foreign student affairs at AStA (Student Union); 1994-95
  • DAAD Award 1995 (sponsored by DAAD, the German Academic Exchange Program) 

Awards and Recognitions Obtained by Students during my Supervision

  • Faculty Award for the best doctoral dissertation for Philipp Jovanovic (2016)
  • Authenticated stream cipher NORX by Philpp Jovanovic selected for the third round of the CAESAR competition (2015). Invited talk at 31C3 congress in Berlin.
  • Successful attack on the Open Smart Grid Protocol by Philipp Jovanovic
  • Wolfgang Gentner Award for outstanding doctoral thesis of Matthias Sauer. The thesis finishes second in the best thesis competition at IEEE European Test Symposium (2014)
  • Alexandru Paler invited to Heidelberg Laureate Forum (2013)
  • Piet Engelke wins the best thesis competition at IEEE European Test Symposium (2009) 

Membership and Functions in Professional Organizations

 

Conference Organization

Program Committee Member

Past Program Committee Member

Organization of Dagstuhl Seminars

  • Hardware Security (May 2016) – with Osnat Keren (Bar Ilan University, IL), Mark M. Tehranipoor (University of Florida, US), Pim Tuyls (Intrinsic-ID, BE)
  • Secure Composition for Hardware Systems (July 2019) – with Arora Divya (Intel, US), Francesco Regazzoni (USI Lugano, CH), Patrick Schaumont (Virginia Tech, US)

Other Service for Conferences and Journals

  • Guest Editor of the Special Issue on Hardware-oriented Security, it – Information Technology, 2019
  • Guest Editor of the Special Issue «Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels», Journal of Low Power and Applications (JLPEA), 2016
  • Guest Editor of the Special Issue on Hardware Security, IET Computers & Digital Techniques, 2014
  • Panel organizer or panelist: IEEE WRTLT 2007 (Hongkong), IEEE ETS 2007 (Freiburg), ITC 2008 (Santa Clara), IEEE RASDAT 2010 (Bangalore), IEEE VTS 2010 (Santa Cruz), IEEE RASDAT 2011 (Chennai), IEEE ETS 2013 (Avignon), IVSW 2016 (Sant Feliu de Guixols), FDTC 2017 (Taipeh), IVSW 2018 (Platja d'Aro)
  • Special Session Organizer: WDSN 2010 (Chicago), LPonTR 2010 (Prague), WDSN 2010 (Chicago), IEEE ATS 2010 (Shanghai), LPonTR 2011 (Trondheim), LPonTR 2012 (Annecy), IEEE ATS 2012 (Niigata), IEEE VTS 2013 (Berkeley), ACM/IEEE DAC 2015 (San Francisco), IEEE SOCC 2017 (Munich), ICCAD 2018 (San Diego)
  • Tutorial presenter: GI/ITG/GMM ZUE 2007 (Munich), LPonTR 2009 (Sevilla), IEEE DDECS 2013 (Karlowy Vary), TRUDEVICE Training School 2016 (Leukerbad)
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