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Neue Methoden für den Massiv-Parallel Test im Hochvolumen, Yield Learning und Beste Testqualität

05.2006 - 04.2009, BMBF-Project    

Until 2008 digital circuitry will increase up to nearly 100 million gate equivalences; that will result in about 4 times more test vec-tors than required today. The costs of testing these new ICs and their huge data volume produced will add up to at least a factor of three, the required test time to a factor of 10. Even if not considering the increased number of pins, test cost per IC will explode to a factor of 120. The project MAYA will address this challenge by developing and integrating innovative technology for capturing data massively in parallel on-chip as well as multisite testing, and fast data processing to off-chip. These solutions will meet the demand for the next higher through-put increase of high-volume production testing at high quality.

Förderung

  • Förderinitiative Ekompass des Bundesministerium für Bildung, Wissenschaft, Forschung und Technologie (BMBF)

Publikationen

  • Programmable Deterministic Built-in Self-test
    A.-W. Hakmi, H.-J. Wunderlich, C.G. Zoellin, A. Glowatz, J. Schloeffel, F. Hapke
    19th ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Erlangen, Germany, 2007, pp. 61-65.

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