Martin Radetzki

Zusammenfassung

Embedded systems design has lately become particularly challenging due to fast increasing system complexities, realtime demands and reliability requirements. At the same time, designs are constrained by stringent power budgets, limited memory capacity and short time-to-markets. Recently, various methods to automatically generate, analyze, and optimize different stages of the design flow have been investigated. The evaluation of these methods, however, often focuses on a single associated field of research and thus may not consider the domain-crossing effects that stem from the interaction of different design methods. This paper presents a complete and fully automated workflow that covers model-based generation, analysis, and optimization aspects for embedded firmware and demonstrates it on a virtual system prototype of a typical inertial sensor node. We illustrate the integration of different design and evaluation methods on a realistic example and show potential opportunities for the application of gathered information in order to improve the design.

Zusammenfassung

In order to tolerate faults that emerge in operating Networks-on-Chip, diagnosis techniques are employed for fault detection and localization. On various network layers, diverse diagnosis methods can be employed which differ in terms of their impact on network performance (e.g. by operating concurrently vs. pre-empting regular network operation) and the quality of diagnostic results. In this contribution, we show how diagnosis techniques of different network layers of a Network-on-Chip can be combined into multi-layer solutions. We present the cross-layer information flow used for the interaction between the layers and show the resulting benefit of the combination compared to layer-specific diagnosis. For evaluation, we investigate the diagnosis quality and the impact on system performance to explore the entire design space of layer-specific techniques and their multi-layer combinations. We identify pareto-optimal combinations that offer an increase of system performance by a factor of four compared to the single-layer diagnosis.

Zusammenfassung

Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.

Zusammenfassung

Dieser Artikel stellt eine Methode vor, den Entwurfsraum beim prüfgerechten Entwurf (engl. Design-for-Test, DfT) zu untersuchen und Teststrategien und Testschedules zu validieren. Alle Teile der Testinfrastruktur, wie etwa die Testeranbindung (Test Access Mechanisms), die Testwrapper, die Testdatenkompression sowie die entsprechenden Steuerwerke werden auf Transaktionsebenenmodelle (TLMs) abgebildet. Die kommunikationsbezogene Sicht der TLMs eignet sich besonders, da viele Aspekte des Tests die Übertragung großer Mengen an Teststimuli und -antworten erfordern. An einer Fallstudie wird der Einsatz von TLMs in frühen Entwurfsphasen erläutert. Der vorgestellte Ansatz hat wesentlich höhere Simulationseffizienz als Ansätze auf Register-Transfer- und Gatterebene.