Michael Imhof

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Universität Stuttgart

	Institut für Technische Informatik
	Michael Imhof

	Name:	Dipl.-Inf. Michael Imhof
	Adress:	University of Stuttgart Institute of Computer Architecture and Computer Engineering Pfaffenwaldring 47 D-70569 Stuttgart Germany
	Room:	3.170
	Phone:	(+49) (0)711 / 7816-393
	Fax:	(+49) (0)711 / 7816-288
	E-Mail:	michael.imhof@iti.uni-stuttgart.de

Teaching

SS 2009: Hardwarepraktikum

(Haupt-)Seminar: Reliable Networks-On-Chip in the Many-Core Era

SS 2008: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Hardwarepraktikum

WS 2007: Konzeption und Implementation von EDA-Werkzeugen
Rechnerorganisation / Technische Informatik II

SS 2007: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Hardwarepraktikum

SS 2006: Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik
Designing High Performant Systems: Statistical Timing Analysis and Optimization

Research

Projects

	REALTEST: Test and Reliability of nanoelectronic Systems In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.

IBM CAS Project: Improved Testing of VLSI Chips with Power Constraints

The elevated power dissipation during test has severe impact on test time, test reliability and product reliability, especially for high-performance processors like the Cell Processor.
In the course of this project, new methods for test planning that take advantage of clock gating and power gating are developed.

Project Partner: IBM Deutschland Entwicklung

SIMTECH: Cluster of Excellence "Simulation-Technology": Mapping Simulation Algorithms to NoC MPSoC Computers

Technology scaling of nanoelectronic circuits currently introduces a fundamental paradigm shift of architectures for high-performance computing. Due to power and noise issues, single chip architectures have to gain increased performance by increased parallelism instead of increased frequency. Goal of this project is a methodology to map compute intensive portions of simulation algorithms to configurable Network-on-Chip Multi-Processor System on a Chip (NoC MPSoCs).

Publications

Journals and Conference Proceedings

Test Exploration and Validation Using Transaction Level Models
Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
Design, Automation and Test in Europe (DATE'09), Nice, France, April 20-24, 2009

Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung
Detection of transient faults in circuits with reduced power dissipation
M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
2. GMM/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Ingolstadt, Germany, 29.09. - 01.10.2008, pp. 107-114
pdf (504 KB)

Integrating Scan Design and Soft Error Correction in Low-Power Applications
M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin
14th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece, July 7-9, 2008, pp. 59-64
pdf (417 KB)

Scan Chain Clustering for Test Power Reduction
M. Elm, M. E. Imhof, H.-J. Wunderlich, C. G. Zoellin, J. Leenstra, N. Maeding
45th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 8-13, 2008, pp. 828-833
pdf (523 KB)

Test Set Stripping Limiting the Maximum Number of Specified Bits
Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich
4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008, pp. 581-586
Best paper award pdf (477 KB)

Scan Test Planning for Power Reduction
M.E. Imhof, C.G. Zoellin, H.-J. Wunderlich
44th ACM/IEEE Design Automation Conference (DAC), San Diego, CA, USA, June 4-8, 2007, pp. 521-526
pdf (700 KB)
Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute
M.E. Imhof, C.G. Zoellin, H.-J. Wunderlich, N. Maeding, J. Leenstra
Tagung Zuverlässigkeit und Entwurf (ZuD 2007), München, Deutschland, 26. - 28. März 2007, pp. 69-76
pdf (258 KB)

Workshop Contributions

Test Exploration und Validierung auf der Transaktionsebene
Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
21th ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen", Bremen, Germany, February 15-17, 2009

Integrating Scan Design and Soft Error Correction in Low-Power Applications
Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin
1st Workshop on Low Power Design Impact on Test and Reliability (LPonTR08), Verbania, Italy, May 25-29, 2008

Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information
Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin, Jens Leenstra, Nicolas Maeding
20th ITG/GI/GMM Workshop "Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen", Wien, Austria, February 24-26, 2008

Invited Presentations

Soft Error Correction in Embedded Storage Elements
South European Test Seminar, Valmorel, France, March 2009

Integrating Scan Design and Soft Error Correction in Low-Power Applications
South European Test Seminar, Obergurgl, Austria, March 2008

Scan Test Planning for Power Reduction
South European Test Seminar, Sestriere, Italy, March 2007

Computing-Cluster-Based ATPG for Combinational Circuits
South European Test Seminar, Neustift im Stubaital, Austria, March 2006

Master/Diploma Theses:

Proposals

Software infrastructure for CAD support of complex test architectures

Current

Completed

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