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Timing Simulation of Systems with Adaptive Voltage Scaling on GPUs

Kategorie: Open Seminar - Rechnerarchitektur

09:45 - 10:30, Hotel Zollernblick, Freudenstadt, Dipl.-Inf. Eric Schneider, Institut für Technische Informatik

Modern designs often utilize adaptive voltage and frequency scaling (AVFS) to adapt performance and power consumption of the circuit to operational conditions. With the influence of parameter variations on the circuit delay, accurate validation of the circuit timing plays an important role in today’s design and test validation and design exploration. While simulation at logic level is considered timing-accurate and widely used, conventional time simulation at logic level does not take parameter variations into account in an efficient and practical manner to be applied for million gate designs.

This paper presents a novel highly-parallel approach for timing-accurate simulation with parameter-variation-aware gate delays at logic level on graphics processing units (GPUs). The delay modelling utilizes regression analysis over simulation data from SPICE to approximates the delay behavior under realistic parameter variations. During simulation the delays of circuit instances are drawn in parallel with negligible runtime impact allowing for an efficient simulation of circuit instances for different parameter configurations. Experimental results on a recent 15nm FinFET technology prove the efficiency and accuract of the presented approach.


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