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< Timing Simulation of Systems with Adaptive Voltage Scaling on GPUs

Power-Aware Test Scheduling for Faster-than-At-Speed Test

Kategorie: Open Seminar - Rechnerarchitektur

11:00 - 11:45, Hotel Zollernblick, Freudenstadt, Dr. Chang Liu, Institut für Technische Informatik

As a good indicator of early life failures and performance marginal devices, small delay faults require thorough testing, even though they may neither alter the functional behavior of a system nor violate any aging guardband. The size of such delay faults may be smaller than the slack of sensitized paths in the circuit, thus often targeted by the Faster-than-At-Speed Test (FAST). The high test power induced by the significant increase of switching activities during FAST can cause over-testing, and even hardware damage thus reduces the test throughput and manufacturing yield.
Besides, the IR-drop which comes along with the high power consumption raises the circuit path length and makes the detection of small delay faults easier.

This work takes the test power influence into account. By efficiently analyzing the timing impact of the extra power dissipation, an improved small delay fault coverage can be achieved with the optimized test schedule.


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