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26.07.17

IR-Drop Analysis for Faster-than-at-Speed Test

Kategorie: Open Seminar - Rechnerarchitektur, SS 17

13:45 - 14:30, Haus der Kirche, Bad Herrenalb, M.Sc. Chang Liu, Institut für Technische Informatik


Defects such as resistive opens, resistive bridges, gate-oxide
defects or parametric deviations of transistors often manifest
themselves as small delay faults (SDF), introducing an additional small
delay at cells or interconnects. SDF may indicate marginal hardware that
degrades into an early life failure (ELF). When the fault magnitude of
an SDF is smaller than the slack of the longest sensitizable path
through the fault site, the fault effect is unobservable by at-speed or
even timing-aware delay test. Thus, those SDFs are often targeted by
faster-than-at-speed test (FAST), which applies test patterns at
frequencies above the nominal operation speed.

During high-speed testing, IR-drop effects become an important issue
causing the voltage drop in the power grid due to the nonnegligible
resistance between the rail and each circuit node. Significant IR-drop
may lead to overtesting and increase the risk of yield loss. In this
work, we perform a case study of IR-drop effects during FAST by HSPICE
simulation.