Denis Schwachhofer

Zusammenfassung

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description.

Zusammenfassung

System-Level Test (SLT) has been an integral part of integrated circuit test flows for over a decade and continues to be significant. Nevertheless, there is a lack of systematic approaches for generating test programs, specifically focusing on the non-functional aspects of the Device under Test (DUT). Currently, test engineers manually create test suites using commercially available software to simulate the end-user environment of the DUT. This process is challenging and laborious and does not assure adequate control over non-functional properties. This paper proposes to use Large Language Models (LLMs) for SLT program generation. We use a pre-trained LLM and fine-tune it to generate test programs that optimize non-functional properties of the DUT, e.g., instructions per cycle. Therefore, we use Gem5, a microarchitectural simulator, in conjunction with Reinforcement Learning-based training. Finally, we write a prompt to generate C code snippets that maximize the instructions per cycle of the given architecture. In addition, we apply hyperparameter optimization to achieve the best possible results in inference.

Zusammenfassung

The rising complexity of integrated devices has led to new defect types and failure modes at the system level that are not detected by structural tests. System-Level Test (SLT) is another test step to combat this challenge. SLT is in charge of exercising system-level interactions between hardware components and software. Non-functional properties, e.g., temperature, play a major role in SLT.This work focuses on the automatic generation of assembly test programs for SLT that aim to indirectly maximize a particular non-functional property, for example, the temperature. It is based on two-step generation with genetic algorithms. First, a fast architectural simulation is used with the genetic algorithm to provide a structure for the test programs. Afterward, an additional generation is done on the hardware to optimize the initial register contents of the program.The case study for gathering experimental results is a super-scalar out-of-order RISC-V processor, the Berkeley Out-of-Order Machine (BOOM). Experimental results show that the two-step generation is more effective in converging to a better power-hungry test program than only using the power consumption as a fitness function for the genetic algorithm.