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Using NoC as TAM for Online Switch Diagnosis (Closed)


Current System-on-Chips (SoCs) integrate hundred and thousands of cores into a single chip. To decrease the communication complexity among the cores in the SoC, Network-on-Chip (NoC) is used as communication infrastructure to supersede the traditional bus structures. Like any other digital system, NoC may become defect either during production or in the life time. In this thesis, the faults which appear during the life time are of interest.

We assume that the faulty switches are identified by an online test strategy. Structural offline diagnosis for NoC switches showed that it is possible to identify and retain the fault-free switch ports for system use instead of disabling the defective switches. This improves performance and yield. To reuse this offline method for the online purposes, we assume that the diagnosis analysis is
performed in the diagnosis service point off or on the chip. However, structural test data must be applied to the switch under diagnosis and the responses must be carried to the diagnosis service point for the analysis.

The objective of this thesis is to deploy the on chip resources in order to apply the test patterns to the defective switch and gather the test responses and transport them to the diagnosis service point. After isolation of defective components, using NoC as test access mechanism (TAM) test data is transported over the functioning NoC as test packets. A wrapper must be designed to extract the test data of an incoming packet and apply it to the switch test infrastructure. Then, the test responses are
captured by the wrapper and the wrapper embeds the test responses in the test packets and injects them to the network toward the diagnosis service point to be analyzed. To reduce the test application time, the scan chains of the switch are restructured such that the test data bits which are arriving in parallel via the test packet can be stored to the multiple scan chains simultaneously.

From the diagnosis results the ports of the switch which are not in hand any more are determined. Then, the defect state of the switch is sent by the reconfiguration packets and is stored both in the defective switch and the switches in the neighborhood for the further configuration decisions. A high-level NoC simulator is used to implement the TAM for test packet distribution. The wrapper and the switch containing the DfT structure are implemented as synthesizable RTL models. The impact
of test packets transmission on the latency and throughput of the system is measured in a multi-level simulation platform.


Lectures: Advanced Processor Architecture/Grundlagen der Rechnerarchitektur, Design and Test of System on a Chip or Hardware Verification and Quality Assessment or Hardware Based Fault Tolerance

Programming: strong VHDL or Verilog knowledge


The thesis can be written in English or German.



Atefe Dalirsani (Email: dalirsani@informatik.uni-stuttgart.de)
Hans-Joachim Wunderlich (Email: wu@informatik.uni-stuttgart.de)


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