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Structural Software-­based Self­-test for Speed Binning of Micro­processors

With nanoscale circuit integration, modern microprocessors become susceptible to variations in the manufacturing process [1]. In order to avoid a decrease of production yield due to variations, speed binning is employed. Produced chips are classified with regards to the maximum frequency, at which they are tested to operate correctly. Customers can then purchase chips of a specific speed grade.

Scan-based test methods are prohibitive for speed grading, as they require expensive external automatic test equipment (ATE). Built-in self-test (BIST) schemes eliminate the need for external ATE, but may conflict with design requirements when facing high-performance microprocessors. Software-based self-test (SBST) is a beneficial approach for speed grading, as neither external ATE nor additional test structures are necessary.

Traditionally, existing functional test patterns from validation/verification are reused for speed grading. Research in this field has shown that structural test patterns can be used to target related path delay faults in a more systematic way [2].

In this work, the use of structural software-based self-testing for speed binning is investigated. Therefore, the first task of this work is to identify functionally sensitizable, critical paths. Then, an existing SAT-based ATPG is employed to generate path delay test patterns for an open-source processor component (i.e. from MiniMIPS or OR1200, [3]). In the third step, an abstract model for variations is derived, in order to validate the effectiveness of previously generated test patterns for speed grading.


Requirements:

  • VHDL/Verilog
  • C++

[1]Becker et al: Massive statistical process variations: A grand challenge for testing nanoelectronic circuits, WDSN'10

[2] Zeng et al: On correlating structural tests with functional tests for speed binning of high performance design, ITC'04

 [3] http://opencores.org

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