Application-Dependent In-Field Delay Characterization of FPGA Interconnection
Process variations during manufacturing as well as aging-induced circuit degra dation change the electrical parameters, and thus the timing behavior, of the components of an FPGA. This includes the logic elements in the FPGA as well as the programmable and static interconnection.
During operation, a delay increase of the components may cause a timing failure if a design is implemented in the FPGA with a critical path exceeding the clock period. If the delay of the FPGA components used by the target design (application) can be measured and evaluated in the field, a warning can be issued to the user before a timing failure occurs.
The goal of this thesis is the development and evaluation of a delay characterization method for the interconnection in the FPGA used by a target design. This method comprises:
- The extraction of the interconnection used by the implementation of the target design,
- The scheduling of the characteri-zation (serial vs. parallel measure-ment of interconnections), and
- The design of hardware structures to measure the delay of FPGA interconnection (e.g. ring oscillators or at-speed test methods).
Ring oscillator for delay measurement
The proposed method shall be validated by simulation. A hardware prototype on a Xilinx Virtex-5 FPGA shall be developed.
The thesis can be completed in German or English
- Background in hardware test (e.g. lectures HVQA or HBFT)
- Knowledge of the structure of FPGAs
- Prof. Dr. rer. nat. habil. Hans Joachim Wunderlich