Dieses Bild zeigt Victor van Santen

Victor van Santen

Herr Dr.-Ing.

Wissenschaftlicher Mitarbeiter
Institut für Technische Informatik
Test und Diagnose von Halbleitersystemen

Kontakt

+49 711 685 88282
 +49 711 685 88288

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 2.172

  1. 2023

    1. Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. van Santen Victor; Jose M. Gata-Romero; Juan Nunez; Roca Eli and Hussam Amrouch. In Proceedings of the IEEE 61st International Reliability Physics Symposium  (IRPS’23), Monterey, California, U.S., 2023.
    2. Design Automation for Cryogenic CMOS Circuits. Victor van Santen; Marcel Walter; Florian Klemme; Shivendra Parihar; Girish Pahwa; Yogesh Chauhan; Robert Wille and Hussam Amrouch. In Proceedings of the 60th Annual Design Automation Conference (DAC’23), San Francisco, USA, 2023.
    3. Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits. Victor van Santen; Florian Klemme; Paul R. Genssler and Hussam Amrouch. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023.

  2. 2022

    1. CARAT: A Framework for Analysis of BTI-HCD Aging in Digitial and AMS Circuits. Narendra Gangwar; Chaitanya Pasupuleti; M van Santen Victor; Uma Sharma; Hussam Amrouch and Souvik Mahapatra. Solid-State Electronics (SSE’22) (2022).

  3. 2021

    1. Machine Learning for Semiconductor Test and Reliability. Hussam Amrouch; Animesh Basak Chowdhury; Wentian Jin; Ramesh Karri; Khorrami Farshad; Prashanth Krishnamurthy; Ilia Polian; Victor M. van Santen; Benjamin Tan and Sheldon Tan. In IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.
    2. Impact of Transistor Self-Heating  on Logic Gates. Victor M. van Santen; Linda Schillinger and Hussam Amrouch. In IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’21), Virtual, 2021.
    3. On the Reliability of FeFET On-Chip Memory. Paul R. Genssler; Victor M. van Santen; Joerg Henkel and Hussam Amrouch. IEEE Transactions on Computers (TC’21) (2021).
    4. Adv-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. Divya Praneetha; Rajesh Kedia; Victor van Santen; Preeti Panda and Hussam Amrouch. IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (2021).
    5. Containing Self-Heating Effects in Advanced Technologies. S. Salamin; V. van Santen; M. Rapp; J. Henkel and H. Amrouch. The Multidisciplinary Open Access Journal IEEE Access (IEEE Access’21) (2021).
    6. Comprehensive Design-Space Exploration for NCFET-based SRAM  Arrays. Victor M van Santen; Simon Thomann; Yogesh S. Chauhan; Joerg Henkel and Hussam Amrouch. In Proceedings of IEEE VLSI Test Symposium (VTS’21), Virtual, 2021.

  4. 2020

    1. NCFET to Rescue Technology Scaling: Opportunities and Challenges. Hussam Amrouch; Victor M. van Santen; Girish Pahwa; Yogesh Chauhan and Jörg Henkel. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20), 2020.
    2. Massively Parallel Circuit Setup in GPU-SPICE. V. van Santen; F. Florian Diep; J. Henkel and H. Amrouch. IEEE Transactions on Computers (TC’20) (2020).
    3. Impact of Self-Heating On Performance, Power and Reliability in FinFET Technology. Victor M. van Santen; Paul R. Genssler; Om Prakash; S. Thomann; Jörg Henkel and Hussam Amrouch. In 25th Asia and South Pacific Design Automation Conference (ASP-DAC’20, 2020.
    4. Modeling Emerging Technologies using Machine Learning:  Challenges and Opportunities. Florian Klemme; Jannik Prinz; Victor M. van Santen; Joerg Henkel and Hussam Amrouch. In IEEE/ACM 38th International Conference on Computer-Aided Design (ICCAD’20), 2020.
    5. BTI and HCI Degradation in a Complete 32X64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity. Victor van Santen; Simon Thomann; C. Pasupuleti; P. Genssler; N. Gangwar; U. Sharma; J. Henkel; S. Mahapatra and H. Amrouch. In Proceedings of the IEEE 58th International Reliability Physics Symposium  (IRPS’20), Dallas, Texas, U.S., Dallas, Texas, 2020.

  5. 2019

    1. Reliability Challenges with Self-Heating in FinFET Technology. H. Amrouch; V. M. van Santen; O. Prakash; H. Kattan; S. Salamin; S. Thomann and J. Henkel. In IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS’19), 2019.
    2. On the Workload Dependence of Self-Heating in FinFET Circuits. Victor M van Santen; Hussam Amrouch; Pooja Sharma and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’19) (2019).
    3. New Worst-Case Timing for Standard Cells Under Aging Effects. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Device and Materials Reliability (T-DMR’19) 19, 1 (2019), pp. 149--158.
    4. Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’19) (2019).
    5. Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. Sami Salamin; Victor M van Santen; Hussam Amrouch; Narendra Parihar; Souvik Mahapatra and Jörg Henkel. IEEE Transactions on Very Large Scale Integration Systems (TVLSI’19) (2019).

  6. 2018

    1. Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE. V. M. van Santen; H. Amrouch and J. Henkel. In IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS’18), 2018, pp. 143–146.
    2. Modeling and Evaluating the Gate Length Dependence of BTI. Victor M van Santen; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II’18) (2018).
    3. Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV. V. M. van Santen; J. Martin-Martinez; H. Amrouch; M. M. Nafria and J. Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I’18) 65, 1 (2018), pp. 293–306.
    4. Estimating and Optimizing BTI Aging Effects: From Physics to CAD. Hussam Amrouch; Victor M. van Santen and Jörg Henkel. In Proceedings of the International Conference on Computer-Aided Design (ICCAD’18), San Diego, California, 2018, pp. 125:1--125:6.
    5. Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. V. M. van Santen; J. Diaz-Fortuny; H. Amrouch; J. Martin-Martinez; R. Rodriguez; R. Castro-Lopez; E. Roca; F. V. Fernandez; J. Henkel and M. Nafria. In IEEE International Reliability Physics Symposium (IRPS’18), 2018, pp. P-CR.6-1-P-CR.6-6.

  7. 2017

    1. Impact of BTI on dynamic and static power: From the physical to circuit level. H. Amrouch; S. Mishra; V. van Santen; S. Mahapatra and J. Henkel. In 017 IEEE International Reliability Physics Symposium (IRPS’17), 2017, pp. CR-3.1-CR-3.6.
    2. Interdependencies of Degradation Effects and Their Impact on Computing. H. Amrouch; V. M. van Santen and J. Henkel. IEEE Design and Test Magazine (DNT’17) 34, 3 (2017), pp. 59–67.

  8. 2016

    1. Designing guardbands for instantaneous aging effects. V. M. van Santen; H. Amrouch; J. Martin-Martinez; M. Nafria and J. Henkel. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16), 2016, pp. 1–6, redHiPEAC Paper Award.
    2. Aging-aware voltage scaling. V. M. van Santen; H. Amrouch; N. Parihar; S. Mahapatra and J. Henkel. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE’16), 2016, pp. 576–581.

  9. 2015

    1. Connecting the physical and application level towards grasping aging effects. H. Amrouch; J. Martin-Martinez; V. M. van Santen; M. Moras; R. Rodriguez; M. Nafria and J. Henkel. In IEEE International Reliability Physics Symposium (IRPS’15), 2015, pp. 3D.1.1-3D.1.8.

  10. 2014

    1. Towards interdependencies of aging mechanisms. H. Amrouch; V. M. van Santen; T. Ebi; V. Wenzel and J. Henkel. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’14), 2014, pp. 478–485.

Victor van Santen received the Dipl. Inform. (M.Sc.) degree in computer science in 2014 at the Karlsruhe Institute of Technology (KIT), where he is finalizing his Ph.D at the Chair for Embedded Systems (CES). He is a researcher at Chair for Semiconductor Test and Reliability (STAR). His research topics include microprocessor reliability estimation, circuit and transistor simulation, failure analysis and reliability estimation with a special interest in aging phenomena.

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