Herr Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich

Lehrstuhlinhaber Rechnerarchitektur
Institut für Technische Informatik
Rechnerarchitektur

Kontakt

+49 711 685-88391
+49 711 685-88288

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 2.170

  1. 2019

    1. Security Compliance Analysis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In to appear in Proceedings of the IEEE International TestConference (ITC’19), Washington DC, USA, 2019.
    2. Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans Joachim Wunderlich. In to appear in Proceedings of the IEEE International Test Conference(ITC’19), Washington DC, USA, 2019.
    3. On Secure Data Flow in Reconfigurable Scan Networks. Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker and Matthias Sauer. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’19), Florence, Italy, 2019, pp. 1016--1021. DOI: https://doi.org/10.23919/DATE.2019.8715172
    4. Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395--416. DOI: https://doi.org/10.1049/PBPC022E_ch16
    5. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
  2. 2018

    1. Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures  in Low-Power Scan Testing. Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 149--154. DOI: https://doi.org/10.1109/ATS.2018.00037
    2. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
    3. Online Prevention of Security Violations in Reconfigurable Scan Networks. Ahmed Atteya; Michael A. Kochte; Matthias Sauer; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE European Test Symposium (ETS’18), Bremen, Germany, 2018, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2018.8400685
    4. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
    5. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2018), pp. 1--13. DOI: https://doi.org/10.1109/TCAD.2018.2864255
    6. Guest Editors’ Introduction. Sybille Hellebrand; Jörg Henkel; Anand Raghunathan and Hans-Joachim Wunderlich. IEEE Embedded Systems Letters 10, 1 (2018), pp. 1--1. DOI: https://doi.org/10.1109/LES.2018.2789942
    7. Guest Editor’s Introduction. Hans-Joachim Wunderlich and Yervant Zorian. IEEE Design & Test 35, 3 (2018), pp. 5--6. DOI: https://doi.org/10.1109/MDAT.2018.2799806
  3. 2017

    1. Quantifying Security in Reconfigurable Scan Networks. Laura Rodríguez Gómez; Michael A. Kochte; Ahmed Atteya and Hans-Joachim Wunderlich. In 2nd International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Limassol, Cyprus, 2017.
    2. Probabilistic Sensitization Analysis for Variation-Aware Path Delay Fault Test Evaluation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968226
    3. Specification and Verification of Security in Reconfigurable Scan Networks. Michael A. Kochte; Matthias Sauer; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE European Test Symposium (ETS’17), Limassol, Cyprus, 2017, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2017.7968247
    4. Energy-efficient and Error-resilient Iterative Solvers for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE International Symposium on  On-Line Testing and Robust System Design (IOLTS’17), Thessaloniki, Greece, 2017, pp. 237--239. DOI: https://doi.org/10.1109/IOLTS.2017.8046244
    5. Aging Monitor Reuse for Small Delay Fault Testing. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 35th VLSI Test Symposium (VTS’17), Caesars Palace, Las Vegas, Nevada, USA, 2017, pp. 1--6. DOI: https://doi.org/10.1109/VTS.2017.7928921
    6. Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich and Martin Radetzki. IEEE Trans. Computers 66, 5 (2017), pp. 848--861. DOI: https://doi.org/10.1109/TC.2016.2628058
    7. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, 6 (2017), pp. 957--970. DOI: https://doi.org/10.1109/TC.2016.2616405
  4. 2016

    1. Hardware/Software Co-Characterization for Approximate Computing. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Pittsburgh, Pennsylvania, USA, 2016.
    2. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.
    3. Functional Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 246--251. DOI: https://doi.org/10.1109/ATS.2016.18
    4. Applying Efficient Fault Tolerance to Enable the Preconditioned  Conjugate Gradient Solver on Approximate Computing Hardware. Alexander Schöll; Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance  in VLSI and Nanotechnology Systems (DFT’16), University of Connecticut, USA, 2016, pp. 21–26. DOI: https://doi.org/10.1109/DFT.2016.7684063
    5. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    6. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    7. Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS’16), Amsterdam, The Netherlands, 2016, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
    8. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    9. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
    10. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
    11. Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’16), Toulouse, France, 2016, pp. 251--262. DOI: https://doi.org/10.1109/DSN.2016.31
  5. 2015

    1. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    2. Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    3. ABFT with Probabilistic Error Bounds for Approximate and Adaptive-Precision Computing Applications. Claus Braun and Hans-Joachim Wunderlich. In Workshop on Approximate Computing, Paderborn, Germany, 2015.
    4. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, 2015, pp. 5:1--5:8. DOI: https://doi.org/10.1145/2786572.2788708
    5. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    6. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    7. Multi-Layer Test and Diagnosis for Dependable NoCs. Hans-Joachim Wunderlich and Martin Radetzki. In Proceedings of the 9th IEEE/ACM International Symposium on Networks-on-Chip (NOCS’15), Vancouver, BC, Canada, 2015. DOI: https://doi.org/10.1145/2786572.2788708
    8. Efficient Observation Point Selection for Aging Monitoring. Chang Liu; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 176--181. DOI: https://doi.org/10.1109/IOLTS.2015.7229855
    9. Efficient On-Line Fault-Tolerance for the Preconditioned Conjugate  Gradient Method. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS’15), Elia, Halkidiki, Greece, 2015, pp. 95--100. DOI: https://doi.org/10.1109/IOLTS.2015.7229839
    10. Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver. Alexander Schöll; Claus Braun; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI  and Nanotechnology Systems (DFT’15), Amherst, Massachusetts, USA, 2015, pp. 60–65. DOI: https://doi.org/10.1109/DFT.2015.7315136
    11. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    12. High-Throughput Logic Timing Simulation on GPGPUs. Stefan Holst; Michael E. Imhof and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 3 (2015), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2714564
    13. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    14. Adaptive Multi-Layer Techniques for Increased System Dependability. Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes M. Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich and Hongyan Zhang. it - Information Technology 57, 3 (2015), pp. 149--158. DOI: https://doi.org/10.1515/itit-2014-1082
    15. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
  6. 2014

    1. A-ABFT: Autonomous Algorithm-Based Fault Tolerance on GPUs. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In International Workshop on Dependable GPU Computing, in conjunction with the ACM/IEEE DATE’14 Conference, Dresden, Germany, 2014.
    2. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    3. Variation-aware deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014, 2014, pp. 1--6. DOI: https://doi.org/10.1109/ETS.2014.6847806
    4. A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. Claus Braun; Sebastian Halder and Hans-Joachim Wunderlich. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’14), Atlanta, Georgia, USA, 2014, pp. 443--454. DOI: https://doi.org/10.1109/DSN.2014.48
    5. Diagnosis of Multiple Faults with Highly Compacted Test Responses. Alejandro Cook and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 27--30. DOI: https://doi.org/10.1109/ETS.2014.6847796
    6. FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects. Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2014.7035360
    7. Area-Efficient Synthesis of Fault-Secure NoC Switches. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 20th  IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro, Catalunya, Spain, 2014, pp. 13--18. DOI: https://doi.org/10.1109/IOLTS.2014.6873662
    8. Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Ulrich Abelein and Piet Engelke. In Proceedings of the 51st ACM/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--9. DOI: https://doi.org/10.1145/2593069.2602971
    9. Incremental Computation of Delay Fault Detection Probability for Variation-Aware Test Generation. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 81--86. DOI: https://doi.org/10.1109/ETS.2014.6847805
    10. Verifikation Rekonfigurierbarer Scan-Netze. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’14), Böblingen, Germany, 2014, pp. 137--146.
    11. Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the  IEEE International Test Conference (ITC’14), Seattle, Washington, USA, 2014, pp. 1--10. DOI: https://doi.org/10.1109/TEST.2014.7035350
    12. Adaptive Parallel Simulation of a Two-Timescale-Model for Apoptotic Receptor-Clustering on GPUs. Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’14), Belfast, United Kingdom, 2014, pp. 424--431. DOI: https://doi.org/10.1109/BIBM.2014.6999195
    13. On Covering Structural Defects in NoCs by Functional Tests. Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ATS.2014.27
    14. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
    15. Structural Software-Based Self-Test of Network-on-Chip. Atefe Dalirsani; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE VLSI Test Symposium (VTS’14), Napa, California, USA, 2014. DOI: https://doi.org/10.1109/VTS.2014.6818754
    16. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23.
    17. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
    18. GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. Hongyan Zhang; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California, USA, 2014, pp. 1--6. DOI: https://doi.org/10.1145/2593069.2593146
    19. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (3. neu bearbeitete Auflage), Christian Siemers and Axel Sikora (eds.). Carl Hanser Verlag GmbH & Co. KG, 2014, pp. 262--285.
    20. Multi-Level Simulation of Non-Functional Properties by Piecewise Evaluation. Nadereh Hatami; Rafal Baranowski; Paolo Prinetto and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 4 (2014), pp. 37:1--37:21. DOI: https://doi.org/10.1145/2647955
    21. Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-chip Resilience. Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. Elsevier Microelectronics Reliability Journal 54, 6--7 (2014), pp. 1066--1074. DOI: https://doi.org/10.1016/j.microrel.2013.12.012
    22. Adaptive Bayesian Diagnosis of Intermittent Faults. Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 5 (2014), pp. 527--540. DOI: https://doi.org/10.1007/s10836-014-5477-1
    23. Exact Logic and Fault Simulation in Presence of Unknowns. Dominik Erb; Michael A. Kochte; Matthias Sauer; Stefan Hillebrecht; Tobias Schubert; Hans-Joachim Wunderlich and Bernd Becker. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19, 3 (2014), pp. 28:1--28:17. DOI: https://doi.org/10.1145/2611760
    24. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    25. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Duc A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovich and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 4 (2014), pp. 401--413. DOI: https://doi.org/10.1007/s10836-014-5459-3
  7. 2013

    1. Cross-Layer Dependability Modeling and Abstraction in Systems on Chip. Andreas Herkersdorf; Michael Engel; Michael Glaß; Jörg Henkel; Veit B. Kleeberger; Michael A. Kochte; Johannes M. Kühn; Sani R. Nassif; Holm Rauchfuss; Wolfgang Rosenstiel; Ulf Schlichtmann; Muhammad Shafique; Mehdi B. Tahoori; Jürgen Teich; Norbert Wehn; Christian Weis and Hans-Joachim Wunderlich. In Selse-9: The 9th Workshop on Silicon Errors in Logic - System Effects, Stanford, California, USA, 2013.
    2. Adaptive Test and Diagnosis of Intermittent Faults. Alejandro Cook; Laura Rodriguez; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In 14th Latin American Test Workshop (LATW’13), Cordoba, Argentina, 2013.
    3. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
    4. Synthesis of Workload Monitors for On-Line Stress Prediction. Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, New York, USA, 2013, pp. 137--142. DOI: https://doi.org/10.1109/DFT.2013.6653596
    5. Accurate Multi-Cycle ATPG in Presence of X-Values. Dominik Erb; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.53
    6. Securing Access to Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE Asian Test Symposium (ATS’13), Yilan, Taiwan, 2013. DOI: https://doi.org/10.1109/ATS.2013.61
    7. SAT-based Code Synthesis for Fault-Secure Circuits. Atefe Dalirsani; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’13), New York City, NY, USA, 2013, pp. 38--44. DOI: https://doi.org/10.1109/DFT.2013.6653580
    8. Efficacy and Efficiency of Algorithm-Based Fault Tolerance on GPUs. Hans-Joachim Wunderlich; Claus Braun and Sebastian Halder. In Proceedings of the IEEE International On-Line Testing Symposium (IOLTS’13), Crete, Greece, 2013, pp. 240--243. DOI: https://doi.org/10.1109/IOLTS.2013.6604090
    9. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 436--441. DOI: https://doi.org/10.7873/DATE.2013.098
    10. Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications. Marcus Wagner and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13), Grenoble, France, 2013, pp. 276--281. DOI: https://doi.org/10.7873/DATE.2013.069
  8. 2012

    1. Fault Modeling in Testing. Stefan Holst; Michael A. Kochte and Hans-Joachim Wunderlich. In RAP Day Workshop, DFG SPP 1500, Munich, Germany, 2012.
    2. Variation-Aware Fault Grading. Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In 21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    3. Exact Stuck-at Fault Classification in Presence of Unknowns. Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 17th IEEE European Test Symposium (ETS’12), Annecy, France, 2012, pp. 98--103. DOI: https://doi.org/10.1109/ETS.2012.6233017
    4. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures. Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM’12), Philadelphia, Pennsylvania, USA, 2012, pp. 1--6. DOI: https://doi.org/10.1109/BIBM.2012.6392661
    5. Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; H. Randoll and S. Döhren. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 214--219. DOI: https://doi.org/10.1109/ATS.2012.32
    6. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures. Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo and Joachim Gross. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12), Montreal, Canada, 2012, pp. 207--212. DOI: https://doi.org/10.1109/ICCD.2012.6378642
    7. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz and Hans-Joachim Wunderlich. In Proceedings of the 13th IEEE Latin-American Test Workshop (LATW’12), Quito, Ecuador, 2012, pp. 1--4. DOI: https://doi.org/10.1109/LATW.2012.6261229
    8. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Aida Todri; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE VLSI Test Symposium (VTS’12), Hyatt Maui, Hawaii, USA, 2012, pp. 50--55. DOI: https://doi.org/10.1109/VTS.2012.6231079
    9. Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’12), Anaheim, California, USA, 2012, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2012.6401555
    10. OTERA: Online Test Strategies for Reliable Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, Germany, 2012, pp. 38--45. DOI: https://doi.org/10.1109/AHS.2012.6268667
    11. Transparent Structural Online Test for Reconfigurable Systems. Mohamed S. Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. In Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges, Spain, 2012, pp. 37--42. DOI: https://doi.org/10.1109/IOLTS.2012.6313838
    12. Variation-Aware Fault Grading. A. Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; M. Sauer; Bernd Becker; Ilia Polian and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 344--349. DOI: https://doi.org/10.1109/ATS.2012.14
    13. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 28, 6 (2012), pp. 831--841. DOI: https://doi.org/10.1007/s10836-012-5329-9
    14. Accurate X-Propagation for Test Applications by SAT-Based Reasoning. Michael A. Kochte; Melanie Elm and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 31, 12 (2012), pp. 1908--1919. DOI: https://doi.org/10.1109/TCAD.2012.2210422
  9. 2011

    1. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Ena, Gifu, Japan, 2011.
    2. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011.
    3. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011.
    4. Mixed-Mode-Mustererzeugung für hohe Defekterfassung beim Eingebetteten Test. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In 23rd GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’11), Passau, Germany, 2011, pp. 55--58.
    5. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter C. Maxwell. In 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    6. Towards Variation-Aware Test Methods. Ilia Polian; Bernd Becker; Sybille Hellebrand; Hans-Joachim Wunderlich and Peter Maxwell. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 219--225. DOI: https://doi.org/10.1109/ETS.2011.51
    7. Structural Test for Graceful Degradation of NoC Switches. Atefe Dalirsani; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 183--188. DOI: https://doi.org/10.1109/ETS.2011.33
    8. Embedded Test for Highly Accurate Defect Localization. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 213--218. DOI: https://doi.org/10.1109/ATS.2011.60
    9. Soft Error Correction in Embedded Storage Elements. Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 169--174. DOI: https://doi.org/10.1109/IOLTS.2011.5993832
    10. Efficient BDD-based Fault Simulation in Presence of Unknown Values. Michael A. Kochte; S. Kundu; Kohei Miyase; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 383--388. DOI: https://doi.org/10.1109/ATS.2011.52
    11. Diagnostic Test of Robust Circuits. Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011, pp. 285--290. DOI: https://doi.org/10.1109/ATS.2011.55
    12. Design and Architectures for Dependable Embedded Systems. Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; Daniel Lohmann; Peter Marwedel; Marco Platzner; Wolfgang Rosenstiel; Ulf Schlichtmann; Olaf Spinczyk; Mehdi Tahoori; Jürgen Teich; Norbert Wehn and Hans-Joachim Wunderlich. In Proceedings of the 9th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS’11), Taipei, Taiwan, 2011, pp. 69--78. DOI: https://doi.org/10.1145/2039370.2039384
    13. Eingebetteter Test zur hochgenauen Defekt-Lokalisierung. Abdullah Mumtaz; Michael E. Imhof; Stefan Holst and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 43--47.
    14. Korrektur transienter Fehler in eingebetteten Speicherelementen. Michael E. Imhof and Hans-Joachim Wunderlich. In 5. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’11), Hamburg-Harburg, Germany, 2011, pp. 76--83.
    15. SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’11), Grenoble, France, 2011, pp. 1303--1308. DOI: https://doi.org/10.1109/DATE.2011.5763209
    16. Structural In-Field Diagnosis for Random Logic Circuits. Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich and Ulrich Abelein. In Proceedings of the 16th IEEE European Test Symposium (ETS’11), Trondheim, Norway, 2011, pp. 111--116. DOI: https://doi.org/10.1109/ETS.2011.25
    17. Fail-Safety in Core-Based System Design. Rafal Baranowski and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens, Greece, 2011, pp. 278--283. DOI: https://doi.org/10.1109/IOLTS.2011.5994542
    18. P-PET: Partial Pseudo-Exhaustive Test for High Defect Coverage. Abdullah Mumtaz; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’11), Anaheim, California, USA, 2011. DOI: https://doi.org/10.1109/TEST.2011.6139130
    19. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Duc Anh Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 20th IEEE Asian Test Symposium (ATS’11), New Delhi, India, 2011. DOI: https://doi.org/10.1109/ATS.2011.89
    20. Variation-aware fault modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. SCIENCE CHINA Information Sciences 54, 9 (2011), pp. 1813--1826. DOI: https://doi.org/10.1007/s11432-011-4367-8
  10. 2010

    1. Application Dependent Vulnerability of Combinational Circuits. Rafal Baranowski and Hans-Joachim Wunderlich. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    2. On Determining the Real Output Xs by SAT-Based Reasoning. Melanie Elm; Michael A. Kochte and Hans-Joachim Wunderlich. In Fault Tolerant Computing Workshop (FTC Kenkyuukai), Chichibu, Japan, 2010.
    3. Effiziente Fehlersimulation auf Many-Core-Architekturen. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian Zöllin. In 22nd ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
    4. Low-Capture-Power Post-Processing of Test Vectors for Test Compression Using SAT Solver. K. Miyase; Michael A. Kochte; X. Wen; S. Kajihara and Hans-Joachim Wunderlich. In IEEE International Workshop on Defect and Data-Driven Testing (D3T’10), Austin, Texas, USA, 2010.
    5. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    6. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28 - July 1, 2010., 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    7. Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 3--8. DOI: https://doi.org/10.1109/ATS.2010.10
    8. Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits. Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the 4th Workshop on Dependable and Secure Nanocomputing (DSN-W’10), Chicago, Illinois, USA, 2010, pp. 95--100. DOI: https://doi.org/10.1109/DSNW.2010.5542612
    9. System Reliability Evaluation Using Concurrent Multi-Level Simulation of Structural Faults. Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In IEEE International Test Conference (ITC’10), Austin, Texas, USA, 2010. DOI: https://doi.org/10.1109/TEST.2010.5699309
    10. Algorithm-Based Fault Tolerance for Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE European Test Symposium (ETS’10), Praha, Czech Republic, 2010, pp. 253--253. DOI: https://doi.org/10.1109/ETSYM.2010.5512738
    11. Low-Power Test Planning for Arbitrary At-Speed Delay-Test Clock Schemes. Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 28th VLSI Test Symposium (VTS’10), Santa Cruz, California, USA, 2010, pp. 93--98. DOI: https://doi.org/10.1109/VTS.2010.5469607
    12. Efficient Fault Simulation on Many-Core Processors. Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 47th ACM/IEEE Design Automation Conference (DAC’10), Anaheim, California, USA, 2010, pp. 380--385. DOI: https://doi.org/10.1145/1837274.1837369
    13. BISD: Scan-Based Built-In Self-Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Design Automation and Test in Europe (DATE’10), Dresden, Germany, 2010, pp. 1243--1248.
    14. Variation-Aware Fault Modeling. Fabian Hopsch; Bernd Becker; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren and Hans-Joachim Wunderlich. In Proceedings of the IEEE 19th Asian Test Symposium (ATS’10), Shanghai, China, 2010, pp. 87--93. DOI: https://doi.org/10.1109/ATS.2010.24
    15. Effiziente Simulation von strukturellen Fehlern für die Zuverlässigkeitsanalyse auf Systemebene. Michael A. Kochte; Christian G. Zöllin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo and Paolo Prinetto. In 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’10), Wildbad Kreuth, Germany, 2010, pp. 25--32.
    16. Models for Power-Aware Testing. Patrick Girard and Hans-Joachim Wunderlich. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 187--215. DOI: https://doi.org/10.1007/978-90-481-3282-9_7
    17. Power-Aware Design-for-Test. Hans-Joachim Wunderlich and Christian Zöllin. In Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard; Nicola Nicolici and Xiaoqing Wen (eds.). Springer-Verlag Heidelberg, 2010, pp. 117--146. DOI: https://doi.org/10.1007/978-1-4419-0928-2_4
    18. Generalized Fault Modeling for Logic Diagnosis. Hans-Joachim Wunderlich and Stefan Holst. In Models in Hardware Testing, Hans-Joachim Wunderlich (ed.). Springer-Verlag Heidelberg, 2010, pp. 133--155. DOI: https://doi.org/10.1007/978-90-481-3282-9_5
    19. Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen;  Algorithm-based Fault-Tolerance on Many-Core Architectures. Claus Braun and Hans-Joachim Wunderlich. it - Information Technology 52, 4 (2010), pp. 209--215. DOI: https://doi.org/10.1524/itit.2010.0593
  11. 2009

    1. Modellierung der Testinfrastruktur auf der Transaktionsebene. Michael A. Kochte; Christian Zöllin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In 21th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 61--66.
    2. Diagnose mit extrem kompaktierten Fehlerdaten. Stefan Holst and Hans-Joachim Wunderlich. In 21. ITG/GI/GMM Workshop “Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen” (TuZ’09), Bremen, Germany, 2009, pp. 15--20.
    3. Test exploration and validation using transaction level models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    4. Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead. Michael A. Kochte; Christian G. Zoellin and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 53--58. DOI: https://doi.org/10.1109/ETS.2009.26
    5. Test Exploration and Validation Using Transaction Level Models. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo and Paolo Prinetto. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1250--1253. DOI: https://doi.org/10.1109/DATE.2009.5090856
    6. A Diagnosis Algorithm for Extreme Space Compaction. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’09), Nice, France, 2009, pp. 1355--1360. DOI: https://doi.org/10.1109/DATE.2009.5090875
    7. Test Encoding for Extreme Response Compaction. Michael A. Kochte; Stefan Holst; Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 14th IEEE European Test Symposium (ETS’09), Sevilla, Spain, 2009, pp. 155--160. DOI: https://doi.org/10.1109/ETS.2009.22
    8. Restrict Encoding for Mixed-Mode BIST. Abdul-Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke and Andreas Glowatz. In Proceedings of the 27th IEEE VLSI Test Symposium (VTS’09), Santa Cruz, California, USA, 2009, pp. 179--184. DOI: https://doi.org/10.1109/VTS.2009.43
    9. XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad. Melanie Elm and Hans-Joachim Wunderlich. In 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’09), Stuttgart, Germany, 2009, pp. 21--28.
    10. Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen. Hans-Joachim Wunderlich; Melanie Elm and Michael A. Kochte. In Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertungin frühen Entwicklungsphasen, Bernd Bertsche; Peter Göhner; Uwe Jensen; Wolfgang Schinköthe and Hans-Joachim Wunderlich (eds.). Springer-Verlag Heidelberg, 2009, pp. 391--464. DOI: https://doi.org/10.1007/978-3-540-85091-5_8
    11. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 25, 4–5 (2009), pp. 259--268. DOI: https://doi.org/10.1007/s10836-009-5109-3
  12. 2008

    1. Reduktion der Verlustleistung beim Selbsttest durch Verwendung testmengenspezifischer Information. Michael E. Imhof; Hans-Joachim Wunderlich; Christian Zöllin; Jens Leenstra and Nicolas Maeding. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 137--141.
    2. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian Zöllin. In 1st International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR’08), Verbania, Italy, 2008.
    3. Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008.
    4. Prüfpfad Konfigurationen zur Optimierung der diagnostischen Auflösung. Melanie Elm and Hans-Joachim Wunderlich. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 7--11.
    5. On the Reliability Modeling of Embedded Hardware-Software Systems. Michael A. Kochte; Rafal Baranowski and Hans-Joachim Wunderlich. In 1st IEEE Workshop on Design for Reliability and Variability (DRV’08), Santa Clara, California, USA, 2008.
    6. Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. Torsten Coym; Sybille Hellebrand; Stefan Ludwig; Bernd Straube; Hans-Joachim Wunderlich and Christian Zöllin. In 20th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’08), Wien, Austria, 2008, pp. 153--157.
    7. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
    8. Erkennung von transienten Fehlern in Schaltungen mit reduzierter Verlustleistung;  Detection of transient faults in circuits with reduced power dissipation. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’08), Ingolstadt, Germany, 2008, pp. 107--114.
    9. Scan Chain Clustering for Test Power Reduction. Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra and Nicolas Maeding. In Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC’08), Anaheim, California, USA, 2008, pp. 828--833. DOI: https://doi.org/10.1145/1391469.1391680
    10. Signature Rollback – A Technique for Testing Robust Circuits. Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE VLSI Test Symposium (VTS’08), San Diego, California, USA, 2008, pp. 125--130. DOI: https://doi.org/10.1109/VTS.2008.34
    11. Scan Chain Organization for Embedded Diagnosis. Melanie Elm and Hans-Joachim Wunderlich. In Proceedings of the 11th Conference on Design, Automation and Test in Europe (DATE’08), Munich, Germany, 2008, pp. 468--473. DOI: https://doi.org/10.1109/DATE.2008.4484725
    12. Integrating Scan Design and Soft Error Correction in Low-Power Applications. Michael E. Imhof; Hans-Joachim Wunderlich and Christian G. Zoellin. In Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS’08), Rhodes, Greece, 2008, pp. 59--64. DOI: https://doi.org/10.1109/IOLTS.2008.31
    13. Test Set Stripping Limiting the Maximum Number of Specified Bits. Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof and Hans-Joachim Wunderlich. In Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA’08), Hong Kong, China, 2008, pp. 581--586. DOI: https://doi.org/10.1109/DELTA.2008.64
    14. Selective Hardening in Early Design Steps. Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian and Bernd Becker. In Proceedings of the 13th IEEE European Test Symposium (ETS’08), Lago Maggiore, Italy, 2008, pp. 185--190. DOI: https://doi.org/10.1109/ETS.2008.30
  13. 2007

    1. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian Zöllin; Andreas Glowatz; Jürgen Schlöffel and Friedrich Hapke. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 61--65.
    2. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 82--86.
    3. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In 19th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’07), Erlangen, Germany, 2007, pp. 56--60.
    4. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. Phillip Öhler; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), Krakow, Poland, 2007, pp. 185--190. DOI: https://doi.org/10.1109/DDECS.2007.4295278
    5. Verlustleistungsoptimierende Testplanung zur Steigerung von Zuverlässigkeit und Ausbeute. Michael E. Imhof; Christian G. Zöllin; Hans-Joachim Wunderlich; Nicolas Mäding and Jens Leenstra. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 69--76.
    6. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’07), Rome, Italy, 2007, pp. 50--58. DOI: https://doi.org/10.1109/DFT.2007.43
    7. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip (Invited Paper). Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 27--36.
    8. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance (Invited Paper). Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. In Proceedings of 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), Bled, Slovenia, 2007, pp. 3--10.
    9. Domänenübergreifende Zuverlässigkeitsbewertung in frühen Entwicklungsphasen unter Berücksichtigung von Wechselwirkungen. Michael Wedel; Peter Göhner; Jochen Gäng; Bernd Bertsche; Talal Arnaout and Hans-Joachim Wunderlich. In 5. Paderborner Workshop “Entwurf mechatronischer Systeme,” Paderborn, Germany, 2007, pp. 257--272.
    10. Programmable Deterministic Built-in Self-test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Juergen Schloeffel and Laurent Souef. In Proceedings of the International Test Conference (ITC’07), Santa Clara, California, USA, 2007, pp. 1--9. DOI: https://doi.org/10.1109/TEST.2007.4437611
    11. Scan Test Planning for Power Reduction. Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC’07), San Diego, California, USA, 2007, pp. 521--526. DOI: https://doi.org/10.1145/1278480.1278614
    12. Test und Zuverlässigkeit nanoelektronischer Systeme. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. In 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE’07), Munich, Germany, 2007, pp. 139--140.
    13. Adaptive Debug and Diagnosis Without Fault Dictionaries. Stefan Holst and Hans-Joachim Wunderlich. In Proceedings of the 12th IEEE European Test Symposium (ETS’07), Freiburg, Germany, 2007, pp. 7--12. DOI: https://doi.org/10.1109/ETS.2007.9
    14. Test und Diagnose. Hans-Joachim Wunderlich. In Taschenbuch Digitaltechnik (2. Auflage), Christian Siemers and Axel Sikora (eds.). Fachbuchverlag Leipzig im Carl Hanser Verlag, 2007, pp. 267--290.
    15. Debug and Diagnosis: Mastering the Life Cycle of Nano-Scale Systems on Chip. Hans-Joachim Wunderlich; Melani Elm and Stefan Holst. Informacije MIDEM 37, 4(124) (2007), pp. 235--243.
    16. Academic Network for Microelectronic Test Education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich and Jean Pierre Van Der Heyden. The International Journal of Engineering Education 23, 6 (2007), pp. 1245--1253.
    17. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym and Bernd Straube. Informacije MIDEM 37, 4(124) (2007), pp. 212--219.
  14. 2006

    1. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zöllin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 101--103.
    2. Software-basierender Selbsttest von Prozessoren bei beschränkter Verlustleistung. Jun Zhou and Hans-Joachim Wunderlich. In 18th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’06), Titisee, Germany, 2006, pp. 95--100.
    3. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel and Hans-Joachim Wunderlich. In Proceedings of the Conference on Design & Test of Integrated Systems in Nanoscale Technology (DTIS’06), Tunis, Tunisia, 2006, pp. 359--364. DOI: https://doi.org/10.1109/DTIS.2006.1708693
    4. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. Christian Zoellin; Hans-Joachim Wunderlich; Nicolas Maeding and Jens Leenstra. In Proceedings of the International Test Conference (ITC’06), Santa Clara, California, USA, 2006, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2006.297695
    5. Structural-based Power-aware Assignment of Don’t Cares for Peak Power Reduction during Scan Testing. Nabil Badereddine; Patrick Girard; Serge Pravossoudovitch; Christian Landrault; Virazel Arnaud and Hans-Joachim Wunderlich. In Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, 2006, pp. 403--408. DOI: https://doi.org/10.1109/VLSISOC.2006.313222
    6. Deterministic Logic BIST for Transition Fault Testing. Valentin Gherman; Hans-Joachim Wunderlich; Juergen Schloeffel and Michael Garbers. In Proceedings of the 11th European Test Symposium (ETS’06), Southampton, United Kingdom, 2006, pp. 123--130. DOI: https://doi.org/10.1109/ETS.2006.12
    7. Some Common Aspects of Design Validation, Debug and Diagnosis. Talal Arnaout; Günter Bartsch and Hans-Joachim Wunderlich. In Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA’06), Kuala Lumpur, Malaysia, 2006, pp. 3--10. DOI: https://doi.org/10.1109/DELTA.2006.79
    8. Software-Based Self-Test of Processors under Power Constraints. Jun Zhou and Hans-Joachim Wunderlich. In Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE’06), Munich, Germany, 2006, pp. 430--436. DOI: https://doi.org/10.1109/DATE.2006.243798
    9. X-masking during logic BIST and its impact on defect coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Trans. VLSI Syst. 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
    10. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme;  DFG-Project – Test and Reliability of Nano-Electronic Systems. Bernd Becker; Ilia Polian; Sybille Hellebrand; Bernd Straube and Hans-Joachim Wunderlich. it - Information Technology 48, 5 (2006), pp. 304--311. DOI: https://doi.org/10.1524/itit.2006.48.5.304
    11. X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilian Polian; Bernd Becker; Jürgen Schlöffel; Friedrich Hapke and Michael Wittke. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14, 2 (2006), pp. 193--202. DOI: https://doi.org/10.1109/TVLSI.2005.863742
  15. 2005

    1. DLBIST for Delay Testing. Michael Garbers; Jürgen Schlöffel; Valentin Gherman and Hans-Joachim Wunderlich. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 39--43.
    2. Implementing a Scheme for External Deterministic Self-Test. Abdul-Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 27--31.
    3. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilian Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In 17th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’05), Innsbruck, Austria, 2005, pp. 16--20.
    4. Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. Jun Zhou and Hans-Joachim Wunderlich. In INFORMATIK 2005 - Informatik LIVE! Band 1, Beiträge der 35. Jahrestagung der Gesellschaft für Informatik e.V. (GI), Bonn, Germany, 2005, pp. 441--441.
    5. On the Reliability Evaluation of SRAM-based FPGA Designs. Oliver Héron; Talal Arnaout and Hans-Joachim Wunderlich. In Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL’05), Tampere, Finland, 2005, pp. 403--408. DOI: https://doi.org/10.1109/FPL.2005.1515755
    6. Frühe Zuverlässigkeitsanalyse mechatronischer Systeme;  Early Reliability Analysis for Mechatronic Systems. Patrick Jäger; Bernd Bertsche; Talal Arnout and Hans-Joachim Wunderlich. In 22. VDI Tagung Technische Zuverlässigkeit (TTZ’05), Stuttgart, Germany, 2005, pp. 39--56.
    7. Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST. Piet Engelke; Valentin Gherman; Ilia Polian; Yuyi Tang; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, 2005, pp. 11--18.
    8. From Embedded Test to Embedded Diagnosis. Hans-Joachim Wunderlich. In Proceedings of the 10th IEEE European Test Sypmposium (ETS’05), Tallinn, Estonia, 2005, pp. 216--221. DOI: https://doi.org/10.1109/ETS.2005.26
    9. Development of an Audio Player as System-on-a-Chip using an Open Source Platform. Kiatisevi Pattara; Luis Azuara; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’05), Kobe, Japan, 2005, pp. 2935--2938. DOI: https://doi.org/10.1109/ISCAS.2005.1465242
    10. Implementing a Scheme for External Deterministic Self-Test. Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers and Jürgen Schlöffel. In Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS’05), Palm Springs, California, USA, 2005, pp. 101--106. DOI: https://doi.org/10.1109/VTS.2005.50
  16. 2004

    1. EuNICE-Test: European network for test education. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’04), Tatranska Lomnica, Slovakia, 2004.
    2. Masking X-Responses During Deterministic Self-Test. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Garbers and Jürgen Schlöffel. In 16th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’04), Dresden, Germany, 2004, pp. 13--19.
    3. Digital, Memory and Mixed-Signal Test Engineering Education: 5 centers of competence in Europe. Frank Novak; Anton Biasizzo; Yves Bertrand; Marie-Lise Flottes; Joan Figueras; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi and Hans-Joachim Wunderlich. In IEEE International Workshop on Electronic Design, Test and Applications (DELTA’04), Perth, Australia, 2004, pp. 135--140.
    4. X-Masking During Logic BIST and its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In 5th IEEE International Workshop on Test Resource Partitioning (TRP’04), Napa Valley, California, USA, 2004, pp. 442--451.
    5. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian and Bernd Becker. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    6. X-Masking During Logic BIST and Its Impact on Defect Coverage. Yuyi Tang; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilian Polian and Bernd Becker. In Proceedings of the 35th IEEE International Test Conference (ITC’04), Charlotte, New York, USA, 2004, pp. 442--451. DOI: https://doi.org/10.1109/TEST.2004.1386980
    7. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke and Michael Wittke. In Proceedings of the 9th IEEE European Test Sypmposium (ETS’04), Ajaccio, Corsica, France, 2004, pp. 327--332.
    8. Impact of Test Point Insertion on Silicon Area and Timing during Layout. Harald Vranken; Ferry Syafei Sapei and Hans-Joachim Wunderlich. In Proceedings of the 7th Conference on Design, Automation and Test in Europe (DATE’04), Paris, France, 2004, pp. 20810--20815. DOI: https://doi.org/10.1109/DATE.2004.1268981
    9. Efficient Pattern Mapping For Deterministic Logic BIST. Valentin Gherman; Hans-Joachim Wunderlich; Harald Vranken; Friedrich Hapke; Michael Wittke and Michael Garbers. In Proceedings of the 35th IEEE International Test Conference (ITC’04), Charlotte, New York, USA, 2004, pp. 48--56. DOI: https://doi.org/10.1109/TEST.2004.1386936
  17. 2003

    1. Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level. Yves Bertrand; Marie-Lise Flottes; Nicoleta Pricopi and Hans-Joachim Wunderlich. In 15th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’03), Timmendorfer Strand, Germany, 2003.
  18. 2002

    1. Power Conscious BIST Approaches. Arnaud Virazel and Hans-Joachim Wunderlich. In 3. VIVA Schwerpunkt-Kolloquium, Chemnitz, Germany, 2002, pp. 128--135.
    2. Adapting an SoC to ATE Concurrent Test Capabilities. Rainer Dorsch; Ramón Huerta Rivera; Hans-Joachim Wunderlich and Martin Fischer. In Proceedings of the 33rd International Test Conference (ITC’02), Baltimore, Maryland, USA, 2002, pp. 1169--1175. DOI: https://doi.org/10.1109/TEST.2002.1041875
    3. RESPIN++ - Deterministic Embedded Test. Lars Schäfer; Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 7th European Test Workshop (ETW’02), Korfu, Greece, 2002, pp. 37--44. DOI: https://doi.org/10.1109/ETW.2002.1029637
    4. Efficient Online and Offline Testing of Embedded DRAMs. Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets and Vyacheslav N. Yarmolik. IEEE Transactions on Computers 51, 7 (2002), pp. 801--809. DOI: https://doi.org/10.1109/TC.2002.1017700
    5. A Mixed-Mode BIST Scheme Based on Folding Compression. Huaguo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Computer Science and Technology 17, 2 (2002), pp. 203–212. DOI: https://doi.org/10.1007/BF02962213
    6. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (2002), pp. 231--240. DOI: https://doi.org/10.1023/A:1014968930415
    7. High Defect Coverage with Low Power Test Sequences in a BIST Environment. Patrick Girard; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel and Hans-Joachim Wunderlich. IEEE Design & Test of Computers 19, 5 (2002), pp. 44--52. DOI: https://doi.org/10.1109/MDT.2002.1033791
    8. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 18, 2 (2002), pp. 159--170. DOI: https://doi.org/10.1023/A:1014993509806
  19. 2001

    1. Reusing Scan Chains for Test Pattern Decompression. Rainer Dorsch and Hans-Joachim Wunderlich. In European Test Workshop (ETW’01), Stockholm, Sweden, 2001, pp. 307--315.
    2. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Hua-Guo Liang; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 894--902. DOI: https://doi.org/10.1109/TEST.2001.966712
    3. On Applying the Set Covering Model to Reseeding. Silvia Chiusano; Stefano Di Carlo; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE’01), Munich, Germany, 2001, pp. 156--160. DOI: https://doi.org/10.1109/DATE.2001.915017
    4. A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. Patrick Girard; Lois Guiller; Christian Landrault; Serge Pravossoudovitch and Hans-Joachim Wunderlich. In Proceedings of the 19th VLSI Test Symposium (VTS’01), Marina Del Rey, California, USA, 2001, pp. 306--311. DOI: https://doi.org/10.1109/VTS.2001.923454
    5. Circuit Partitioning for Efficient Logic BIST Synthesis. Alexander Irion; Gundolf Kiefer; Harald Vranken and Hans-Joachim Wunderlich. In Proceedings of the 4th Conference on Design, Automation and Test in Europe (DATE’01), Munich, Germany, 2001, pp. 86--91. DOI: https://doi.org/10.1109/DATE.2001.915005
    6. Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability. Michael Kessler; Gundolf Kiefer; Jens Leenstra; Knut Schünemann; Thomas Schwarz and Hans-Joachim Wunderlich. In Proceedings of the 32nd IEEE International Test Conference (ITC’01), Baltimore, Maryland, USA, 2001, pp. 461--469. DOI: https://doi.org/10.1109/TEST.2001.966663
    7. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (2001), pp. 351--362. DOI: https://doi.org/10.1023/A:1012283800306
    8. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Sybille Hellebrand; Hua-Guo Liang and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 17, 3–4 (2001), pp. 341--349. DOI: https://doi.org/10.1023/A:1012279716236
  20. 2000

    1. Application of Deterministic Logic BIST on Industrial Circuits. Gundolf Kiefer; Harald Vranken; Erik Jan Marinissen and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’00), Informal digest, Cascais, Portugal, 2000, pp. 99--104.
    2. Synthesis of Efficient Test Pattern Generators for Deterministic Functional BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In 7th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 2000.
    3. Synthese effizienter Testmustergeneratoren für den deterministischen funktionalen Selbsttest. Rainer Dorsch and Hans-Joachim Wunderlich. In 12th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’00), Grassau, Germany, 2000, pp. 1--7.
    4. Using Mission Logic for Embedded Testing. Rainer Dorsch and Hans-Joachim Wunderlich. In 1st IEEE International Workshop on Test Resource Partitioning (TRP’00), Atlantic City, New Jersey, USA, 2000.
    5. Optimal Hardware Pattern Generation for Functional BIST. Silvia Cataldo; Silvia Chiusano; Paolo Prinetto and Hans-Joachim Wunderlich. In Proceedings of the 7th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Paris, France, 2000, pp. 292--297. DOI: https://doi.org/10.1109/DATE.2000.840286
    6. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (2000), pp. 203--212. DOI: https://doi.org/10.1023/A:1008383013319
    7. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 16, 3 (2000), pp. 169--177. DOI: https://doi.org/10.1023/A:1008374811502
  21. 1999

    1. Deterministic BIST with Partial Scan. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’99), Constance, Germany, 1999, pp. 110--116.
    2. Exploiting Symmetries to Speed Up Transparent BIST. Sybille Hellebrand; Hans-Joachim Wunderlich and Vyacheslav N. Yarmolik. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 12--15.
    3. Minimum Scan Insertion for Generating Pipeline-Structured Modules. Gundolf Kiefer and Hans-Joachim Wunderlich. In 11th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’99), Potsdam, Germany, 1999, pp. 30--33.
    4. Minimized Power Consumption for Scan-Based BIST. Stefan Gerstendörfer and Hans-Joachim Wunderlich. In Proceedings of the 30th IEEE International Test Conference (ITC’99), Atlantic City, New Jersey, USA, 1999, pp. 77--84. DOI: https://doi.org/10.1109/TEST.1999.805616
    5. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 14, 1–2 (1999), pp. 85--93. DOI: https://doi.org/10.1023/A:1008353423305
  22. 1998

    1. Deterministic BIST with Multiple Scan Chains. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’98), Sitges, Barcelona, Spain, 1998, pp. 39--43.
    2. Pattern Selection for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
    3. Scan Path Design for Low-Power Serial Built-In Self Test. M. Zelleröhr; Andre Hertwig and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’98), Herrenberg, Germany, 1998.
    4. Efficient Consistency Checking for Embedded Memories. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In 10th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’98), Herrenberg, Germany, 1998.
    5. Low-Power Serial Built-In Self Test. Andre Hertwig and Hans-Joachim Wunderlich. In IEEE European Test Workshop (ETW’98), Sitges, Barcelona, Spain, 1998, pp. 51.
    6. Efficient Consistency Checking for Embedded Memories. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In 5th IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1998.
    7. Fast Self-Recovering Controllers. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 16th IEEE VLSI Test Symposium (VTS’98), Monterey, California, USA, 1998, pp. 296--302. DOI: https://doi.org/10.1109/VTEST.1998.670883
    8. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. Vyacheslav N. Yarmolik; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st Conference on Design, Automation and Test in Europe (DATE’98), Paris, France, 1998, pp. 173--179. DOI: https://doi.org/10.1109/DATE.1998.655853
    9. Accumulator Based Deterministic BIST. Rainer Dorsch and Hans-Joachim Wunderlich. In Proceedings of the 29th IEEE International Test Conference (ITC’98), Washington, DC, USA, 1998, pp. 412--421. DOI: https://doi.org/10.1109/TEST.1998.743181
    10. Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Madhavi Karkala; Nur A. Touba and Hans-Joachim Wunderlich. In Proceedings of the 7th Asian Test Symposium (ATS’98), Singapore, 1998, pp. 492--499. DOI: https://doi.org/10.1109/ATS.1998.741662
    11. Test and Testable Design. Hans-Joachim Wunderlich. In Architecture Design and Validation Methods, Egon Börger (ed.). Springer-Verlag Heidelberg, 1998, pp. 141--190.
    12. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In On-Line Testing for VLSI, Michael Nicolaidis; Yervant Zorian and Dhiraj K. Pradhan (eds.). Kluwer Academic Publishers, 1998.
    13. Hardware-Optimal Test Register Insertion. Albrecht P. Stroele and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 17, 6 (1998), pp. 531--539. DOI: https://doi.org/10.1109/43.703833
  23. 1997

    1. Using BIST Control for Pattern Generation. Gundolf Kiefer and Hans-Joachim Wunderlich. In IEEE European Test Workshop, Cagliari, Italy, 1997.
    2. Synthesis of Fast On-line Testable Controllers for Data-Dominated Applications. Andre Hertwig; Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
    3. Prüfpfadbasierter Selbsttest mit vollständiger Fehlererfassung und niedrigem Hardware-Aufwand. Gundolf Kiefer and Hans-Joachim Wunderlich. In 9th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’97), Bremen, Germany, 1997, pp. 49--52.
    4. Fast Controllers for Data Dominated Applications. Andre Hertwig and Hans-Joachim Wunderlich. In Proceedings of the European Design & Test Conference (ED&TC’97), Paris, France, 1997, pp. 84--89. DOI: https://doi.org/10.1109/EDTC.1997.582337
  24. 1996

    1. Using Embedded Processors for BIST. Sybille Hellebrand and Hans-Joachim Wunderlich. In 3rd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1996.
    2. Scan-based BIST with Complete Fault Coverage and Low Hardware Overhead. Hans-Joachim Wunderlich and Gundolf Kiefer. In IEEE European Test Workshop, Montpellier, France, 1996, pp. 60--64.
    3. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In 2nd IEEE International On-Line Testing Workshop, Biarritz, France, 1996.
    4. Mixed-Mode BIST Using Embedded Processors. Sybille Hellebrand; Hans-Joachim Wunderlich and Andre Hertwig. In Proceedings of the 27th IEEE International Test Conference (ITC’96), Washington, DC, USA, 1996, pp. 195--204. DOI: https://doi.org/10.1109/TEST.1996.556962
    5. Bit-Flipping BIST. Hans-Joachim Wunderlich and Gundolf Kiefer. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’96), San Jose, California, USA, 1996, pp. 337--343. DOI: https://doi.org/10.1109/ICCAD.1996.569803
  25. 1995

    1. Erfassung realistischer Fehler durch kombinierten IDDQ- und Logiktest. Olaf Stern and Hans-Joachim and Wunderlich. In 7th ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’95), Hannover, Germany, 1995.
    2. Pattern Generation for a Deterministic BIST Scheme. Sybille Hellebrand; Birgit Reeb; Steffen Tarnick and Hans-Joachim Wunderlich. In 2nd IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1995.
    3. Synthesis of Iddq-Testable Circuits: Integrating Built-In Current Sensors. Hans-Joachim Wunderlich; M. Herzog; Joan Figueras; J.A. Carrasco and A. Calderón. In Proceedings of the European Design & Test Conference (ED&TC’95), Paris, France, 1995, pp. 573--580. DOI: https://doi.org/10.1109/EDTC.1995.470342
  26. 1994

    1. Testsynthese für Datenpfade. Albrecht P. Ströle and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 162--171.
    2. Analyse und Simulation realistischer Fehler. Olaf Stern; Wu and Hans-Joachim Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    3. Synthese schneller selbsttestbarer Steuerwerke. Sybille Hellebrand and Hans-Joachim and Wunderlich. In Tagungsband der GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme,” Oberwiesenthal, Germany, 1994, pp. 3--11.
    4. Ein Verfahren zur testfreundlichen Steuerwerkssynthese. Sybille Hellebrand and Hans-Joachim and Wunderlich. In 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’94), Vaals, Netherlands, 1994.
    5. Synthesis for Testability - the ARCHIMEDES Approach. Sybille Hellebrand; J. P. Teixeira and Hans-Joachim and Wunderlich. In 1st IEEE International Test Synthesis Workshop, Santa Barbara, California, USA, 1994.
    6. A Unified Method for Assembling Global Test Schedules. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 3rd Asian Test Symposium (ATS’94), Nara, Japan, 1994, pp. 268--273. DOI: https://doi.org/10.1109/ATS.1994.367220
    7. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the European Design Automation Conference (EDAC/ETC/EuroAsic’94), Paris, France, 1994, pp. 580--585. DOI: https://doi.org/10.1109/EDTC.1994.326815
    8. Configuring Flip-Flops to BIST Registers. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE International Test Conference (ITC’94), Washington, DC, USA, 1994, pp. 939--948. DOI: https://doi.org/10.1109/TEST.1994.528043
    9. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), San Jose, California, USA, 1994, pp. 110--116. DOI: https://doi.org/10.1109/ICCAD.1994.629752
  27. 1993

    1. Synthesis of Self-Testable Controllers. Sybille Hellebrand and Hans-Joachim Wunderlich. In ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support,” Montpellier, France, 1993.
  28. 1992

    1. Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen. Olaf Stern and Hans-Joachim Wunderlich. In 5. ITG-Fachtagung Mikroelektronik für die Informationstechnik, 1992, pp. 117--122. DOI: https://doi.org/10.18419/opus-7903
    2. Efficient Test Set Evaluation. Hans-Joachim Wunderlich and M. Warnecke. In Proceedings of the 3rd European Conference on Design Automation (EDAC’92), Brussels, Belgium, 1992, pp. 428--433. DOI: https://doi.org/10.1109/EDAC.1992.205970
    3. Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Hans-Joachim Wunderlich and Michael H. Schulz. Informatik-Spektrum 15, 1 (1992), pp. 23--32. DOI: https://doi.org/10.18419/opus-7897
    4. The Pseudoexhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 11, 1 (1992), pp. 26--33. DOI: https://doi.org/10.1109/43.108616
  29. 1991

    1. A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. Thomas Kropf and Hans-Joachim Wunderlich. In Proceedings of the 22nd IEEE International Test Conference (ITC’91), Nashville, Tennessee, USA, 1991, pp. 57--66. DOI: https://doi.org/10.1109/TEST.1991.519494
    2. Emulation of Scan Paths in Sequential Circuit Synthesis. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 5th International GI/ITG/GMA Conference on Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment, Nürnberg, Germany, 1991, pp. 136--147. DOI: https://doi.org/10.18419/opus-7904
    3. A Unified Approach for the Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC’91), San Francisco, California, USA, 1991, pp. 372--377. DOI: https://doi.org/10.1145/127601.127697
  30. 1990

    1. Generating Pseudo-Exhaustive Vectors for External Testing. Sybille Hellebrand; Hans-Joachim Wunderlich and Oliver F. Haberl. In IEEE Design for Testability Workshop, Vail, Colorado, USA, 1990.
    2. A Synthesis Approach to Reduce Scan Design Overhead. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 671. DOI: https://doi.org/10.18419/opus-7927
    3. Error Masking in Self-Testable Circuits. Albrecht P. Stroele and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE International Test Conference (ITC’90), Washington, DC, USA, 1990, pp. 544--552. DOI: https://doi.org/10.1109/TEST.1990.114066
    4. The Effectiveness of Different Test Sets for PLAs. Peter C. Maxwell and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 628--632. DOI: https://doi.org/10.1109/EDAC.1990.136722
    5. Tools and Devices Supporting the Pseudo-Exhaustive Test. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 1st European Design Automation Conference (EDAC’90), Glasgow, United Kingdom, 1990, pp. 13--17. DOI: https://doi.org/10.1109/EDAC.1990.136612
    6. Optimized Synthesis of Self-Testable Finite State Machines. Bernhard Eschermann and Hans-Joachim Wunderlich. In Proceedings of the 20th International Symposium on Fault-Tolerant Computing (FTCS-20), Newcastle Upon Tyne, United Kingdom, 1990, pp. 390--397. DOI: https://doi.org/10.1109/FTCS.1990.89393
    7. Multiple Distributions for Biased Random Test Patterns. Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 9, 6 (1990), pp. 584--593. DOI: https://doi.org/10.1109/43.55187
    8. An Analytical Approach to the Partial Scan Problem. Arno Kunzmann and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 1, 2 (1990), pp. 163--174. DOI: https://doi.org/10.1007/BF00137392
    9. Methoden der Testvorbereitung zum IC-Entwurf. Martin H. Schulz and Hans-Joachim Wunderlich. Mikroelektronik 4, 3 (1990), pp. 112--115. DOI: https://doi.org/10.18419/opus-7919
  31. 1989

    1. Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen. F. Kesel and Hans-Joachim Wunderlich. In Proceedings of the ITG-Fachtagung Mikroelektronik für die Informationstechnik, Stuttgart, Germany, 1989, pp. 63--68. DOI: https://doi.org/10.18419/opus-7933
    2. Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern. Frank Kesel and Hans-Joachim Wunderlich. In GMD Berichte, 4. E.I.S.-Workshop, Bonn, Germany, 1989, pp. 75--84. DOI: https://doi.org/10.18419/opus-7936
    3. The Design of Random-Testable Sequential Circuits. Hans-Joachim Wunderlich. In Proceedings of the 19th International Symposium on Fault-Tolerant Computing (FTCS-19), Chicago, Illinois, USA, 1989, pp. 110--117. DOI: https://doi.org/10.1109/FTCS.1989.105552
    4. The Synthesis of Self-Test Control Logic. Oliver F. Haberl and Hans-Joachim Wunderlich. In Proceedings of the CompEuro ’89., “VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks,” Hamburg, Germany, 1989, pp. 5/134--5/136. DOI: https://doi.org/10.1109/CMPEUR.1989.93499
    5. The Pseudo-Exhaustive Test of Sequential Circuits. Hans-Joachim Wunderlich and Sybille Hellebrand. In Proceedings of the 20th IEEE International Test Conference (ITC’89), Washington, DC, USA, 1989, pp. 19--27. DOI: https://doi.org/10.1109/TEST.1989.82273
  32. 1988

    1. Automatisierung des Entwurfs vollständig testbarer Schaltungen. Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 18. GI Jahrestagung II, Hamburg, Germany, 1988, pp. 145--159. DOI: https://doi.org/10.1007/978-3-642-74135-7_10
    2. Weighted Random Patterns with Multiple Distributions. Hans-Joachim Wunderlich. In Proceedings of the 11th International Conference on Fault Tolerant Systems and Diagnostics, Suhl, German Democratic Republic, 1988, pp. 88--93. DOI: https://doi.org/10.18419/opus-7941
    3. Output-maximal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1988, pp. 1011--1020. DOI: https://doi.org/10.1080/00207728808547182
  33. 1987

    1. On Computing Optimized Input Probabilities for Random Tests. Hans-Joachim Wunderlich. In Proceedings of the 24th ACM/IEEE Design Automation Conference (DAC’87), Miami Beach, Florida, USA, 1987, pp. 392--398. DOI: https://doi.org/10.1145/37888.37947
    2. Integrated Tools for Automatic Design for Testability. D. Schmid; Hans-Joachim Wunderlich; F. Feldbusch; Sybille Hellebrand; J. Holzinger and Arno Kunzmann. In Proceedings of the IFIP WG 10.2 Workshop on Tool Integration and Design Environments, Paderborn, Germany, 1987, pp. 233--258. DOI: https://doi.org/10.18419/opus-7942
    3. The Random Pattern Testability of Programmable Logic Arrays. Hans-Joachim Wunderlich. In Proceedings of the IEEE International Conference on Computer Design (ICCD’87), Port Chester, New York, USA, 1987, pp. 682--685. DOI: https://doi.org/10.18419/opus-7944
  34. 1986

    1. The Integration of Test and High Level Synthesis in a General Design Environment. D. Schmid; R. Camposano; Arno Kunzmann; Wolfgang Rosenstiel and Hans-Joachim Wunderlich. In Proceedings of the Integrated Circuits Technology Conference (ICTC’86), Limerick, Ireland, 1986, pp. 317--331. DOI: https://doi.org/10.18419/opus-7947
  35. 1985

    1. PROTEST: A Tool for Probabilistic Testability Analysis. Hans-Joachim Wunderlich. In Proceedings of the 22nd ACM/IEEE Design Automation Conference (DAC’85), Las Vegas, Nevada, USA, 1985, pp. 204--211. DOI: https://doi.org/10.1145/317825.317858
    2. Design Automation of Random Testable Circuits. Arno Kunzmann and Hans-Joachim Wunderlich. In Proceedings of the 11th European Solid-State Circuits Conference (ESSCIRC’85), Toulouse, France, 1985, pp. 277--285. DOI: https://doi.org/10.18419/opus-7949
  36. 1984

    1. Time-optimal control policies for cascaded production-inventory systems with control and state constraints. J. Warschat and Hans-Joachim Wunderlich. In International Journal of Systems Science. Taylor & Francis, 1984, pp. 513--524. DOI: https://doi.org/10.1080/00207729408926580

Ausbildung

Wissenschaftliche Prüfungen

07.1990

Abschluss des Habilitationsverfahrens und Erteilung der Lehrbefugnis für das Fach Informatik, Habilitationsschrift über „Rechnergestützte Verfahren für den prüfgerechten Entwurf und Test hochintegrierter Schaltungen“

12.1986

Promotion zum Dr. rer. nat. an der Fakultät für Informatik der Universität Karlsruhe
(„Mit Auszeichnung“) über „Probabilistische Verfahren zur Verbesserung der Testbarkeit hochintegrierter Schaltungen“

10.1981

Diplom in Mathematik mit Nebenfach Philosophie an der Universität Freiburg

1979-1981

Studium der Mathematik und der Philosophie an der Universität Freiburg

1975-1979

Studium der Mathematik und der Philosophie an der Universität Konstanz

Berufliche Laufbahn

seit 10.2017

09.2002 - 09.2017

Leiter der Abteilung „Rechnerarchitektur“ des Instituts für Technische Informatik an der Universität Stuttgart

Geschäftsführender Direktor des Instituts für Technische Informatik an der Universität Stuttgart

 

10.2010 - 09.2013

Prodekan der Fakultät 5 für Informatik, Elektrotechnik und Informationstechnik

seit 10.1996

Ordentlicher Universitätsprofessor (C4) für „Technische Informatik“ an der Universität Stuttgart, Leiter der Abteilung „Rechnerarchitektur“

12.1991 - 09.1996

Ordentlicher Universitätsprofessor (C4) für „Technische Informatik“ an der Universität/GHS Siegen, Leiter der Fachgruppe „Rechnerstrukturen“

01.1991

Ernennung zum Hochschuldozenten (C2) an der Universität Karlsruhe

10.1990 - 03.1991

Vertretung einer C4-Professur an der Universität/GHS Duisburg für das Fach Informatik

09.1982 - 01.1991

Wissenschaftlicher Angestellter an der Universität Karlsruhe

1982

Freier Mitarbeiter am Fraunhofer Institut für Arbeitswirtschaft und Organisation (IAO) in Stuttgart

Längerfristige wissenschaftliche Tätigkeiten im Ausland

04.2010 - 05.2010

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

04.2005 - 08.2005

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

01.2000 - 03.2000

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

08.1999 - 10.1999

LogicVision Inc., San Jose, CA, USA

01.1996 - 02.1996

Mentor Graphics Corporation, Portland, OR, USA

08.1995 - 03.1996

Visiting Professor am „Center of Reliable Computing“, Stanford University, Stanford, CA, USA

03.1988

Ruf als Visiting Assistant Professor an die McGill University, Montreal, Canada

 

2015

IEEE Computer Society, Test Technology Technical Council: Distinguished Service Award for many years of dedicated distinguishing service in creating, organizing, growing and steering ETS

2014

Guest Professor at Hefei University of Technology, Hefei, China

2009

IEEE Fellow for contributions to very-large-scale-integration circuit testing and fault tolerance

2006

IEEE Computer Society Golden Core Member

2005

IEEE Computer Society Meritorious Service Award

1998 - 2008

IEEE Certificates of Appreciation

2001

Ruf an die TU Wien, Professur: Embedded Computing Systems

2000

Landeslehrpreis 1999 des Landes Baden-Württemberg für das Hardware-Praktikum

Best Paper Awards

  • Schöll, A., Braun, C. und Wunderlich, H.-J.
    "Applying Efficient Fault Tolerance to Enable the Preconditioned Conjugate Gradient Solver on Approximate Computing Hardware"
    Best paper award IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'16), University of Connecticut, USA, 19-20 September 2016
  • Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. und Qian, J.
    "Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch"
    Best paper award 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015
  • Baranowski, R., Kochte, M. A. und Wunderlich, H.-J.
    "Access Port Protection for Reconfigurable Scan Networks"
    Best paper award Journal of Electronic Testing: Theory and Applications (JETTA: best paper of the year 2014), Vol. 30(6), 5 December 2014, pp. 711-723
  • Sauer, M., Polian, I., Imhof, M.E., Mumtaz, A., Schneider, E., Czutro, A., Wunderlich, H.-J. und Becker, B.:
    "Variation-Aware Deterministic ATPG",
    Best paper award 19th IEEE European Test Symposium (ETS), Paderborn, Germany, May 26-30, 2014
  • Elm, M. und Wunderlich, H.-J.:
    "XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad",
    Best paper award VDE Tagung "Zuverlässigkeit und Entwurf" (ZuE), Stuttgart, Germany, September 21-23, 2009.
  • Kochte, M.A., Zoellin, C.G., Imhof, M.E. und Wunderlich, H.-J.:
    "Test Set Stripping Limiting the Maximum Number of Specified Bits,"
    Best paper award 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008.
  • Holst, S. und Wunderlich, H.-J.:
    "Adaptive Debug and Diagnosis without Fault Dictionaries,"
    Best paper award 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007.
  • Öhler, P., Hellebrand, S. und Wunderlich, H.-J.:
    "Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair,"
    Best paper award 10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007

 

2018

Alexander Schöll:

"Efficient Fault Tolerance for Selected Scientific Computing Algorithms on Heterogeneous and Approximate Computer Architectures"

2017

Chang Liu:

“Improvement of Hardware Reliability with Aging Monitors”

2017

Laura Rodríguez Gómez:

“Machine Learning Support for Logic Diagnosis”

2016

Marcus Wagner:

“Efficient Algorithms for Fundamental Statistical Timing Analysis Problems
in Delay Test Applications of VLSI Circuits”

2015

Michael Imhof:

“Fault Tolerance Infrastructure and its Reuse for Offline Testing”

2015

Atefe Dalirsani:

“Self-Diagnosis in Network-on-Chips”

2015

Claus Braun:

“Algorithm-Based Fault Tolerance for Matrix Operations on Graphics Processing
Units: Analysis and Extension to Autonomous Operation”

2014

Michael Kochte:

“Boolean Reasoning for Digital Circuits in Presence of Unknown Values”

2014

Alejandro Cook:

“In-Field Structural Methods for End-to-End Automotive Digital Diagnosis”

2014

Nadereh Hatami:

“Multi-level Analysis of Non-Functional Properties”

2014

Christian Zöllin:

“Test Planning for Low-Power Built-In Self-Test”

2014

Rafal Baranowski:

“Reconfigurable scan networks : formal verification, access optimization,
and protection”

2012

Stefan Holst:

“Efficient Location–Based Logic Diagnosis of Digital Circuits”

2011

Melanie Elm:

“Embedded Hardware Structures for Efficient Volume and In-Field Diagnosis
of Random Logic Circuits”

2010

Abdul-Wahid Hakmi:

“Efficient Programmable Deterministic Self-Test”

2009

Jun Zhou:

“Software-Based Self-Test under Memory, Time, and Power Constraints”

2006

Valentin Gherman:

“Scalable Deterministic Logic Built-In Self-Test”

2003

Huaguo Liang:

“A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST)“

2002

Rainer Dorsch:

“Testverfahren für digitale eingebettete Ein-Chip-Systeme“

1996

Olaf Stern:

“Effiziente Erfassung von realistischen Fehlern in hochintegrierten Schaltungen“

 

Tagungsleitung (Auszug)

  • IEEE European Test Symposium (ETS)
    2008 - 2014 Vorsitzender des Steering Committee
    seit 2015 Mitglied des Steering Committee
    Program Chair: 1996 Montpellier (FRA), 1997 Cagliari (ITA), 2001 Stockholm (SWE)
    General Chair: 1999 Konstanz (GER)
    Vice General Chair: 1998 Sitges (ESP)
    Vice Program Chair: 2006 Southampton (GBR), 2007 Freiburg (GER)
    Member of the organization committee: 1996 - 2009
  • IEEE International Test Conference in Asia (ITC-Asia)
    2017 Taipei City (TW)
  • IEEE VLSI Test Symposium (VTS)
    Vice Program Chair: 1997, 2000, 2001
    Vice General Chair: 2002 - 2008
    Member of the organizing committee: 1995 - 2008
  • IEEE International Conference on Computer Design (ICCD)
    Topic Chair: 2011 (MA, USA), 2012 (CDN)
  • GI/ITG/GMM-Workshop: "Test und Zuverlässigkeit" (TuZ)
    General Chair: 1998 Herrenberg (GER)
    Member of the organization committee: 1989 - 2012
    Scientific Chair: 2015
  • International Conference on Computer-Aided Design (ICCAD)
    Topic Chair: 2005, 2006, 2007 San Jose (CA, USA)
  • GI/ITG/GMM-Fachtagung: "Zuverlässigkeit und Entwurf" (ZuE)
    Program Chair: 2007 München (GER), 2008 Ingolstadt (GER), 2009 Stuttgart (GER), 2010 Wildbad Kreuth (GER), 2011 Hamburg-Harburg (GER)
  • Design, Automation and Test Europe (DATE)
    Topic Chair: 2003 München (GER), 2004 Paris (FRA), 2005 München (GER), 2008 München (GER), 2013 (FRA
  • Asian Test Symposium (ATS)
    Honorary Chair: 2018 Hefei, Anhui (CHN)

Programmkomitees (Auszug)

  • Asia and South Pacific Design Automation Conference (ASP-DAC)
    1998, 2000 Yokohama (JPN)
  • Asian Test Symposium (ATS)
    1994 Nara (JPN), 2001 Kyoto (JPN), 2002 Hagåtña (Guam/USA), 2005 Kalkutta (IND), 2007 Beijing (CHN), 2012 Niigata (JPN), 2013 Yilan (RC), 2014 Hangzhou (CHN), 2015 Mumbai (IND), 2016 Hiroshima (JPN), 2017 Taipei (RC)
  • Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS)
    1998 (POL), 2000 (SVK), 2001 (HUN), 2002 (CZE), 2003 (POL), 2004 (SVK), 2005 (HUN), 2006 (CZE), 2007 (POL), 2009 (CZ), 2010 (AUT), 2011 (GER), 2012 (EST), 2013 (CZ), 2014 (PL), 2015 (SRB), 2016 (SK), 2017 (GER), 2018 (HU), 2019 (RO)
  • Design & Test in Europe (DATE)
    1998 Paris (FRA), 1999 München (GER), 2000 Paris (FRA), 2001 München (GER), 2002 Paris (FRA), 2003 München (GER), 2004 Paris (FRA), 2005 München (GER), 2006 München (GER), 2007 Nizza (FRA), 2012 (GER), 2014 (GER), 2015 (FRA), 2016 (GER), 2018 (GER)
  • East-West Design & Test Workshop (EWDTW)
    2004 Yalta (UKR), 2005 Odessa (UKR)
  • European Conference on Design Automation / European Test Conference (EDAC/ETC)
    1991, 1992, 1994, 1995, 1996
  • GI/ITG/GMM-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen
    1989 - 2010
  • IEEE International Conference on Computer Design (ICCD)
    jährlich 1998 – 2003, 2005
  • IEEE International On-Line Testing Symposium (IOLTS)
    jährlich 1995 – 2015
  • IEEE International Test Synthesis Workshop
    jährlich 1994 – 2003
  • IEEE International Test Synthesis Conference (ITC)
    2014
  • IEEE International Workshop on Electronic Design, Test & Applications (DELTA)
    2006 Kuala Lumpur (MAS), 2008 Hong Kong (CHN), 2010 Ho-Chi-Minh City (VN)
  • IEEE VLSI Design
    1991 New Delhi (IND), 1992 Bangalore (IND), 1993 Bombay (IND), 1994 Kalkutta (IND), 1996 Bangalore (IND), 1998 New Delhi (IND)
  • Latin American Test Workshop (LATW)
    jährlich 2000 – 2004, 2010, 2011, 2012, 2013, 2014
  • Latin American Test Symposium (LATS)
    2015 Puerto Vallarta (MEX), 2016 Foz do Iguaçu (BRA)
  • Symposium on Integrated Circuits and System Design (SBCCI)
    2010 Sao Paulo (BRA), 2011, 2012
  • Symposium on Fault-Tolerant Computing (FTCS)
    1990 Newcastle (GBR), 1991 Montreal (CAN), 1992 Boston, 1993 Toulouse (FRA), 1996 Sendai (JPN).
  • 4th Workshop on Dependable and Secure Nanocomputing, WDSN
    2010 Chicago (USA)

Eingeladene Vorträge (Auszug)

  • Keynote bei Workshop on RTL and High Level Testing (WRTLT) 2018, “Security and Privacy Aspects of Reconfigurable Scan Networks”, Hefei, Anhui, China, October 2018
  • Keynote bei: IEEE Asian Test Symposium (ATS), “The Revival of BIST: From Self-Test to Self-Healing”, Taipeh, Taiwan, November 2017
  • Keynote bei: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), “50 years of self-test: From random patterns to in-field automotive testing and health monitoring”, Dresden, Germany, April 2017
  • Eingeladener Vortrag: International Symposium on Dependable Integrated Systems (DISC): “Options and Organization of Faster-than-at-Speed-Test”, Fukuoka, Japan, November 2016
  • Besondere Plenarsitzung zu Ehren von Prof. Edward J. McCluskey: IEEE Asian Test Symposium (ATS): “Tribute to Prof. Edward J. McCluskey: Learning how to teach”, Hiroshima, Japan, November 2016
  • Keynote bei: IEEE East-West Design & Test Symposium(EWDTS), "Multi-Level High-Throughput Simulation for Design & Test Validation", Yerevan, Armenia, Oktober 2016
  • Eingeladener Vortrag: "R3S: Reliable Runtime Reconfigurable Systems", National Sun-Yat-sen University, Kaohsiung, Taiwan, September 2015
  • Eingeladener Vortrag: "Combining Structural and Functional Test Approaches Across System Levels", National Cheng Kung University, Tainan, Taiwan, September 2015
  • Eingeladener Vortrag: "R3S: Reliable Runtime Reconfigurable Systems", Kyushu Institute of Technology, Fukuoka, Japan, September 2015
  • Keynote bei: IEEE International On-Line Testing Symposium (IOLTS), „Fault Tolerance meets Diagnosis”, Elia, Halkidiki, Greece, 2015
  • Keynote bei: IEEE European Test Symposium (ETS), „Testing Visions”, Cluj-Napoca, Romania, 2015
  • Eingeladener Vortrag: IEEE International On-Line Testing Symposium (IOLTS), "Efficacy And Efficiency of Algorithm Based Fault Tolerance on GPUs", Chania, Crete, Greece, 2013
  • Eingeladener Vortrag: IEEE / IFIP International Conference on Dependable Systems and Networks Systems (DSN), (Workshop on Dependable and Secure Nanocomputing), “Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits: Statistical Test Methods”, Chicago, USA, 2010
  • Eingeladener Vortrag: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), “Software -Based Hardware Fault Tolerance for Many-Core Architectures”, Chicago, USA, 2009
  • Eingeladener Vortrag: Forum on specification & Design Languages (FDL), ECSI Conference, “Model-Based Hardware-Testing”, Valbonne, France, 2009
  • Eingeladener Vortrag: IEEE / TTTC Latin American Test Workshop (LATW), “Embedded Diagnosis - a Key to Reliable Systems”, Buzios, Brasil, 2009
  • Eingeladener Vortrag: IEEE International Test Conference (ITC), "Testing the Infrastructure", Santa Clara, USA, 2008
  • Eingeladener Vortrag: Colloque Groupement de Recherche (CNRS), (GDR-SoC-SiP Workshop), “Challenges in Test and Diagnosis or: Complexity is more than Size”, 2008
  • Eingeladener Vortrag: MIDEM Society, International Conference on Microelectronics, Devices and Materials (MIDEM),“Debug and diagnosis mastering the life cycle of nano scale systems on chip”, , Bled, Slovenia, 2007
  • Eingeladener Vortrag: IEEE East-West Design & Test Symposium (EWDTS), "Challenges in the Diagnosis of Nanoelectronic Systems", Yerevan, Armenia, 2007
  • Eingeladener Vortrag: IEEE International Workshop on Electronic Design, Test & Applications (DELTA), “Some Common Aspects of Design Validation,Debug and Diagnosis” Kuala Lumpur, Malaysia, 2006
  • Eingeladener Vortrag: IEEE European Test Symposium (ETS), “From Embedded Test to Embedded Diagnosis”, Tallinn, Estonia, 2005
  • Eingeladener Vortrag: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), “From BIST to BISD”, Stará Lesná, Slovakia, 2004
  • Eingeladener Vortrag: IEEE European Test Symposium (ETS), “Trends in BIST and Diagnosis”, Ajaccio, Corsica, France, 2004

Aktivitäten in wissenschaftlichen Gremien

  • Sprecher der Fachgruppe Testmethoden und Zuverlässigkeit von Schaltungen und Systemen der Informationstechnischen Gesellschaft und der Gesellschaft für Informatik (GI, GMM, ITG) (2008 - 2012)
  • Mitglied im Leitungsgremium des Fachausschusses Rechnergestützter Schaltungs- und Systementwurf (GI, GMM, ITG) (Informationstechnische Gesellschaft im VDE)
  • Mitherausgeber der Zeitschrift “Journal of Electronic Testing: Theory and Application” (JETTA), Springer
  • Mitherausgeber der Zeitschrift ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM (Association of Computing Machinery)(bis 2009)
  • Mitherausgeber der Zeitschrift “Journal of Low Power Electronics” (JOLPE)
  • Mitherausgeber der Zeitschrift ACM Transactions on Embedded Computing Systems (TECS), ACM (Association of Computing Machinery)(bis 2011)

 

Laufende Projekte

seit 02.2017

DFG-Projekt FAST: Zuverlässigkeitsbewertung durch „Faster-than-at-Speed Test“
(Wu 245/19-1)

seit 02.2016

Projekt SHIVA: „Sichere Hardware in der Informationsverarbeitung“, gefördert durch Baden-Württemberg Stiftung

seit 08.2014

DFG Projekt ACCESS: „Robuster ACCESS: Verifikation, Test und Diagnose konfigurierbarer Scan-Netzwerke“ (WU 245/17-1)

Abgeschlossene Projekte

10.2014 - 12.2018

DFG Projekt PARSIVAL: „Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation“ (WU 245/16-1)

01.2015 - 12.2016

PPP Japan, DAAD-JSPS Joint Research Program: „Hochbeschleunigte Simulation für akkuraten Verzögerungsfehlertest“, Kooperation mit dem Kyushu Institute of Technology, Fukuoka, Japan

07.2012 - 06.2015

DFG Projekt RM-BIST: „Reliability Monitoring and Managing Built-In-Self Test“ (WU 245/13-1)

08.2011 - 12.2015

DFG Projekt ROCK: „Robuste Network-On-Chip Kommunikation durch hierarchische Online-Diagnose und –Rekonfiguration“ (WU 245/12-1)

03.2011 - 12.2014

DFG Projekt: OASIS: „Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen“ (WU 245/11-1)

10.2010 - 06.2017

DFG Projekt: OTERA: “Online Test Strategies for Reliable Reconfigurable Architectures” (WU 245/10-1)

10.2010 - 09.2013

DFG Projekt: INTESYS: “Model-Based Test Generation for the Efficient Test of Hardware/Software Systems” (WU 245/9-1)

07.2010 - 07.2013

BMBF Projekt: DIANA: “End-to-End Diagnostic Capabilities for Automotive Electronics Systems”

06.2009 - 05.2013

“Diagnose von Halbleiterfehlern” mit AUDI AG, Germany

06.2008 - 10.2017

Principal Investigator im Exzellenzcluster Simulation Technology (SRC SimTech): Mapping Simulation Algorithms to NoC MPSoC Computers

01.2006 - 06.2013

DFG Projekt: "RealTest - Test and Reliability of Nanoelectronic System" (WU 245/5-1, WU245/5-2)

01.2007 - 12.2009

DAAD/Vigoni: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics. Kooperation mit der Universität Turin

10.2005 - 12.2009

CAS Projekt: On-Demand Power Reduction during Chip Test. In Kooperation mit IBM Deutschland Entwicklung GmbH

05.2006 - 04.2009

BMBF Projekt: Neue Methoden für den massiv-parallel Test im Hochvolumen, Yield Learning und beste Testqualität (Maya). In Kooperation mit NXP und Infineon Technologies

06.2006 - 05.2009

DFG Projekt: DIADEM - Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie (WU 245/4-1)

09.2002 - 12.2009

DFG Forschergruppe: Zuverlässigkeit mechatronischer Systeme (WU 245/3-1, 3-2, 3-3)

03.2002 - 02.2005

BMBF Projekt in Kooperation mit den Firmen ATMEL, Infineon und Philips: Applikationsspezifische Testmethodik für hochkomplexe Systeme der Kommunikations- und Kraftfahrzeugtechnik (AZTEKE)

09.2000 - 09.2003

Projekt mit Philips Eindhoven, Niederlande: Deterministic BIST

12.2002 - 03.2003

Projekt mit Jiri Gaisler Research, Schwe