Dieses Bild zeigt Chih-Hao Wang

Herr Ph.D.

Chih-Hao Wang

Wissenschaftlicher Mitarbeiter
Institut für Technische Informatik
Rechnerarchitektur

Kontakt

+49 711 685 88294
+49 711 685 88288

Pfaffenwaldring 47
70569 Stuttgart
Deutschland
Raum: 2.160

  1. 2022

    1. Robust Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In To appear in Proceedings of the Conference on Design, Automation and Test in Europe (DATE’22), Antwerp, Belgium, 2022, pp. 1--4.
  2. 2021

    1. Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In To appear in Proceedings of the IEEE International Test Conference (ITC’21), Virtual, 2021, pp. 1--10.
    2. Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. Chih-Hao Wang; Natalia Lylina; Ahmed Atteya; Tong-Yu Hsieh and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS’21), Virtual, 2021, pp. 1--7.
  3. 2020

    1. Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Ahmed Atteya; Chih-Hao Wang and Hans-Joachim Wunderlich. In Proceedings of the IEEE International Test Conference (ITC’20), Washington DC, USA, 2020. DOI: https://doi.org/10.1109/ITC44778.2020.9325227
  4. 2019

    1. An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications. C.-H. Wang and T.-Y. Hsieh. ACM Trans. on Design Automation of Electronic Systems (TODAES) 25, 1 (December 2019), pp. Article No.: 3. DOI: https://doi.org/10.1145/3364681
  5. 2018

    1. On Probability of Detection Lossless Concurrent Error Detection Based on Implications. C.-H. Wang and T.-Y. Hsieh. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 37, 5 (May 2018), pp. 1090--1103. DOI: https://doi.org/10.1109/TCAD.2017.2740289
    2. Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection. C.-H. Wang; C.-H. Ho and and T.-Y. Hsieh. In Proc. 2018 Int’l Test Conf. in Asia (ITC-Asia), 2018, pp. 127--132. DOI: https://doi.org/10.1109/ITC-Asia.2018.00032
  6. 2017

    1. A Hybrid Concurrent Error Detection Scheme for Simultaneous Improvement on Probability of Detection and Diagnosability. C.-H. Wang and T.-Y. Hsieh. In Proc. 2017 Int’l Test Conf. in Asia (ITC-Asia), 2017, pp. 52--57. DOI: https://doi.org/10.1109/ITC-ASIA.2017.8097110
  7. 2016

    1. A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. T.-Y. Hsieh; C.-H. Wang; T.-L. Chih and Y.-H. Chi. IEEE Trans. on Very Large Scale Integration (VLSI) Systems (TVLSI) 24, 2 (February 2016), pp. 784--788. DOI: https://doi.org/10.1109/TVLSI.2015.2410218
  8. 2015

    1. Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement. T.-Y. Hsieh; C.-H. Wang; C.-W. Kuo; S.-Y. Huang and T.-L. Chih. Journal of Electronic Testing: Theory and Applications (JETTA) 31, 5–6 (December 2015), pp. 427--441. DOI: https://doi.org/10.1007/s10836-015-5546-0
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