Herr Dipl.-Inf.

Eric Schneider

Wissenschaftlicher Mitarbeiter
Institut für Technische Informatik
Rechnerarchitektur

Kontakt

+49 711 685-88370
+49 711 685-88288

Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Raum: 2.171

Fachgebiet

Test und Zuverlässigkeit, Modellierung und Simulation, Parallele Algorithmen

Kurzbiographie

Eric Schneider received the diploma degree in computer science (Dipl.-Inf.) from the University of Stuttgart, Germany, in 2012. There he joined the Institute of Computer Architecture and Computer Engineering (ITI), where he is currently working towards his Ph.D. His research interests include circuit test and simulation, delay test, power simulation, fault diagnosis, process/parameter variations, as well as modeling and parallel programming on general purpose programmable graphics processing units (GPUs) to accelerate design and test validation and diagnosis tasks; also FPGAs. He is a Student Member of the IEEE since 2014.

  1. 2019

    1. Variation-Aware Small Delay Fault Diagnosis on Compacted Failure Data. Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen and Hans Joachim Wunderlich. In to appear in Proceedings of the IEEE International Test Conference(ITC’19), Washington DC, USA, 2019.
    2. Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems. Lars Bauer; Hongyan Zhang; Michael A. Kochte; Eric Schneider; Hans-Joachim. Wunderlich and Jörg Henkel. In Many-Core Computing: Hardware and software, B. M. Al-Hashimi and G. V. Merrett (eds.). Institution of Engineering and Technology (IET), 2019, pp. 395--416.
    3. Multi-Level Timing and Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. INTEGRATION, the VLSI Journal -- Special Issue of ASP-DAC 2018 64, (2019), pp. 78--91. DOI: https://doi.org/10.1016/j.vlsi.2018.08.005
    4. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
  2. 2018

    1. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
    2. Built-in Test for Hidden Delay Faults. Matthias Kampmann; Michael A. Kochte; Chang Liu; Eric Schneider; Sybille Hellebrand and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2018), pp. 1--13. DOI: https://doi.org/10.1109/TCAD.2018.2864255
    3. Extending Aging Monitors for Early Life and Wear-out Failure Prevention. Chang Liu; Eric Schneider; Matthias Kampmann; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 27th IEEE Asian Test Symposium (ATS’18), Hefei, Anhui, China, 2018, pp. 92--97. DOI: https://doi.org/10.1109/ATS.2018.00028
  3. 2017

    1. Analysis and Mitigation of IR-Drop Induced Scan Shift-Errors. Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara and Xiaoqing Wen. In Proceedings of the IEEE International Test Conference (ITC’17), Fort Worth, Texas, USA, 2017, pp. 1--8. DOI: https://doi.org/10.1109/TEST.2017.8242055
    2. GPU-Accelerated Simulation of Small Delay Faults. Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 36, 5 (2017), pp. 829--841. DOI: https://doi.org/10.1109/TCAD.2016.2598560
    3. Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jörg Henkel. IEEE Transactions on Computers 66, 6 (2017), pp. 957--970. DOI: https://doi.org/10.1109/TC.2016.2616405
  4. 2016

    1. Timing-Accurate Estimation of IR-Drop Impact on  Logic- and Clock-Paths During At-Speed Scan Test. Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich and Michael A. Kochte. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 19--24. DOI: https://doi.org/10.1109/ATS.2016.49
    2. High-Throughput Transistor-Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 150--155. DOI: https://doi.org/10.1109/ATS.2016.9
  5. 2015

    1. GPU-Accelerated Small Delay Fault Simulation. Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the ACM/IEEE Conference onDesign, Automation and Test in Europe (DATE’15), Grenoble, France, 2015, pp. 1174--1179. DOI: https://doi.org/10.7873/DATE.2015.0077
    2. Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich and Jun Qian. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 103–108. DOI: https://doi.org/10.1109/ATS.2015.25
    3. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand and Hans-Joachim Wunderlich. In Proceedings of the 24th IEEE Asian Test Symposium (ATS’15), Mumbai, India, 2015, pp. 109–114. DOI: https://doi.org/10.1109/ATS.2015.26
    4. Hochbeschleunigte Simulation von Verzögerungsfehlern unter Prozessvariationen. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In 27th GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
    5. STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. Hongyan Zhang; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the 34th IEEE/ACM International Conference onComputer-Aided Design (ICCAD’15), Austin, Texas, USA, 2015, pp. 38–45.
  6. 2014

    1. Data-Parallel Simulation for Fast and Accurate Timing Validation of CMOS Circuits. Eric Schneider; Stefan Holst; Xiaoqing Wen and Hans-Joachim Wunderlich. In Proceedings of the 33rd IEEE/ACM International Conferenceon Computer-Aided Design (ICCAD’14), San Jose, California, USA, 2014, pp. 17--23.
    2. Variation-Aware Deterministic ATPG. Matthias Sauer; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 19th IEEE European Test Symposium (ETS’14), Paderborn, Germany, 2014, pp. 87--92. DOI: https://doi.org/10.1109/ETS.2014.6847806
  7. 2013

    1. Module Diversification: Fault Tolerance and Aging Mitigation for Runtime Reconfigurable Architectures. Hongyan Zhang; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich and Jörg Henkel. In Proceedings of the IEEE International Test Conference (ITC’13), Anaheim, California, USA, 2013. DOI: https://doi.org/10.1109/TEST.2013.6651926
    2. Test Strategies for Reliable Runtime Reconfigurable Architectures. Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang; Jörg Henkel and Hans-Joachim Wunderlich. IEEE Transactions on Computers 62, 8 (2013), pp. 1494--1507. DOI: https://doi.org/10.1109/TC.2013.53
  8. 2012

    1. Scan Test Power Simulation on GPGPUs. Stefan Holst; Eric Schneider and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE Asian Test Symposium (ATS’12), Niigata, Japan, 2012, pp. 155--160. DOI: https://doi.org/10.1109/ATS.2012.23
Student Theses
  • Systematische Charakterisierung zur Parametrisierung von Simulationen auf Switch-Ebene
    (Bachelor Thesis)

    Bussmann, S.
    Oct. 9, 2017 - Apr. 9, 2018.
  • Frequency Optimization for Hidden Delay Fault Testing with Monitor Reuse Framework
    (Master Thesis)

    Hu, X.
    Aug. 22, 2017 - Feb. 21, 2018.
  • Hochbeschleunigte IR-Drop Analyse  von integrierten Schaltungen
    (Bachelor Thesis)

    Hagemann, P.
    Mar. 1 - Oct. 6, 2017.
  • Inter-gate Fault Modeling for GPU-accelerated Fault Simulation
    (Master Thesis
    - Nr. 00731-005)
    Frosi, A.
    May 25 - Nov. 24, 2016.
  • Realistic Gate Model for efficient Timing Analysis of very deep submicron CMOS circuits
    (Master Thesis
    - Nr. 00731-001)
    Murali, D.

    Sep. 14, 2015 - Mar. 15, 2016.
  • Switching activity based estimation of IR-drop
    (Projekt INF)
    Hardes, D., Hagemann, P., Knabben, M.
    Feb. 5 - Aug. 7, 2015.
  • Adaptierung an Zeitverhalten-Variationen in rekonfigurierbaren Hardwarestrukturen
    (Bachelor Thesis - Nr. 179)

    Brandhofer, S.
    Oct. 20, 2014 - Apr. 20, 2015.
  • Analysis of Hardware-Accelerated Applications in Reconfigurable Network-on-a-Chip Based Systems
    (Projekt INF)
    Brandhofer, S., Göttlich, P., Lanksweirt, A.
    Jun. 1 - Dec. 1, 2014.

Contributions to ongoing and completed projects:

FAST – Zuverlässigkeitsbewertung durch „Faster-than-at-Speed Test“

Projektseite: FAST – Zuverlässigkeitsbewertung durch „Faster-than-at-Speed Test“

Ein wichtiges Problem in modernen Fertigungstechnologien in der Nanoelektronik sind  Frühausfälle, die immer wieder Rückrufaktionen erfordern und dadurch Kosten in Milliardenhöhe verursachen.  Ein wichtiger Grund hierfür sind sogenannte schwache Schaltungsstrukturen, die zwar bei der Inbetriebnahme funktionieren, aber der späteren Belastung im Betrieb nicht gewachsen sind.  Solche Strukturen können anhand von nichtfunktionalen Indikatoren, insbesondere auch anhand des Zeitverhaltens, identifiziert werden.  Für einen effektiven  und kosteneffizienten Test dieser Indikatoren sollen im FAST Projekt Schaltungen mit einem prüfgerechten Entwurf und Selbsttest ausgestattet werden, die auch bei Frequenzen jenseits der funktionalen Spezifikation arbeiten können, um kleine Abweichungen des nominalen Zeitverhaltens und damit potentielle Frühausfälle zu erkennen.

seit 2.2017, DFG-Projekt: WU 245/19-1   

HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing

Projektseite: High-Performance Simulation (HiPS) for High Quality Small Delay Fault Testing

Projektpartner:  Department of Creative Informatics - Kyushu Institute of Technology

This project aims to find novel abstraction and algorithm mapping methods to allow highly accurate timing and NFP-aware simulation of multi-million gate circuits on data-parallel architectures such as graphics processing units (GPUs). The expected dramatic speedup compared to the existing state-of-the-art allows fault simulation of millions of faults and thousands of patterns. The increased accuracy of the simulation results allow to optimize test patterns w.r.t. test power and small delay defect coverage in presence of power noise, clock skew or even circuit variations.

01.2015 - 12.2016, DAAD/JSPS PPP Japan Projekt: #57155440  

PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Projektseite: PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration.

In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.

seit 10.2014, DFG-Projekt: WU 245/16-1    

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

Projektseite: ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Due to the increasing complexity, however, the embedded infrastructure and flexible access mechanisms such as Reconfigurable Scan Networks (RSNs) themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE P1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals.

seit 08.2014, DFG-Projekt: WU 245/17-1    

OTERA: Online Test Strategies for Reliable Reconfigurable Architectures

Projektseite: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamisch rekonfigurierbare Architekturen ermöglichen eine signifikante Beschleunigung verschiedener Anwendungen durch die Anpassung und Optimierung der Struktur des Systems zur Laufzeit. Permanente und transiente Fehler bedrohen die zuverlässigen Betrieb einer solchen Architektur. Dieses Projekt zielt darauf ab, die Zuverlässigkeit von Laufzeit-rekonfigurierbaren Systemen durch eine neuartige System- Level-Strategie für Online-Tests und Online-Anpassung an Fehler zu erhöhen. Dies wird erreicht durch (a) Scheduling, so dass Tests für rekonfigurierbare Ressourcen mit minimaler Auswirkung auf die Leistung ausgeführt werden, (b) Ressourcen-Management, so dass teilweise fehlerhafte Ressourcen für Komponenten verwendet werden, die den fehlerhaften Teil nicht verwenden, und (c) Online-Uberwachung und Error-Checking. Um eine zuverlässige Rekonfiguration zur Laufzeit zu gewährleisten, wird jeder Rekonfigurationsprozess durch eine neuartige und effiziente Kombination von Online-Struktur- und Funktionstests gründlich getestet. Im Vergleich zu bisherigen Fehlertoleranzkonzepten vermeidet dieser Ansatz die hohen Hardwarekosten von struktureller Redundanz. Die eingesparten Ressourcen können zur weiteren Beschleunigung der Anwendungen verwendet werden. Dennoch deckt das vorgeschlagene Verfahren Fehler in den rekonfigurierbaren Ressourcen, der Anwendungslogik und Fehler im Rekonfigurationsprozess ab.

10.2010 - 06.2017, DFG-Projekt: WU 245/10-1, 10-2, 10-3   

REALTEST: Test und Zuverlässigkeit nanoelektronischer Systeme

Projektseite: Test und Zuverlässigkeit nanoelektronischer Systeme

Zukünftige nanoelektronische Schaltungen zeigen eine hohe Empfindlichkeit gegenüber sog. Soft Errors, die hier nicht nur die Speicherfelder betrifft, sondern insbesondere auch Speicherelemente in freier Logik (z.B. Flip-Flops). Eines der Ziele von Realtest ist die Entwicklung von robusten Registern für freie Logik die eine bessere Flächeneffizienz besitzen als existierende Ansätze.

01.2006 - 07.2013, DFG-Projekt: WU 245/5-1, 5-2    

12.

Small Delay Fault Diagnosis with Compacted Responses
Holst, S., Schneider, E., Kochte, M.A., Wen, X., Wunderlich, H.-J.
Poster at 56th Design Automation Conf. (DAC), Las Vegas, USA, Jun. 04, 2019.

11.

Poster How-To
Schneider, E., Holst S.

Special lecture at 2016 International Symposium on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Nov. 28, 2016.

10.

Diagnosis of Small Delay Faults
Schneider, E.

2016 Joint Workshop on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Sep. 9, 2016.

9.

High-Throughput Parallel Simulation - The Key to Efficient Design and Test Validation
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 8, 2016.

8.

How to master a Master in Germany?
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 8, 2016.

7.

Hazard-Activated Stuck-Open Fault Simulation
Schneider, E.

2016 Joint DAAD/JSPS Spring Research Workshop (Stuttgart-Iizuka), University of Stuttgart, Stuttgart, DE, Mar. 2-5, 2016.

6.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E.
Invited talk at 2015 Joint Workshop on Dependable Integrated Systems in collaboration with the Kyushu Institute of Technology, Fukuoka, JP, Sep. 3, 2015.

5.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E.
Invited talk at Osaka University, Osaka, JP, Aug. 31, 2015.

4.

44. Jahrestagung der Gesellschaft für Informatik, Informatik 2014, Big Data - Komplexität meistern, 22.-26. September 2014 in Stuttgart
Plödereder, E., Grunske, L., Schneider, E., Ull, D. (Hrsg.)
GI-Edition - Lecture Notes in Informatics (LNI), Vol. P-232, Gesellschaft für Informatik e.V. (GI), Sep. 22-26, 2014,
ISBN: 978-3-88579-626-8, Bonner Köllen Verlag, Bonn, DE, 2014.

3.

Massive Throughput Computing: GPUs and their Application in EDA
Schneider, E.
Special lecture at Kyushu Institute of Technology, Iizuka, JP, Sep. 19, 2014.

2.

Data-Parallel Switch-Level Simulation for Fast and Accurate Timing Validation of CMOS Circuits
Schneider, E., Holst, S., Wen, X., Wunderlich, H.-J.
Poster at 51st Design Automation Conf. (DAC), San Francisco, CA, USA, Jun. 1-5, 2014.

1.

GPU-Accelerated Small Delay Fault Simulation
Schneider, E., Holst, S., Wunderlich, H.-J.
Poster at Dependable GPU Computing Workshop, ACM/IEEE Conf. on Design and Test in Europe (DATE),
Dresden, DE, Mar. 24-28, 2014.