Zahra Paria Najafi Haghi

Zusammenfassung

Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

Zusammenfassung

Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications. Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.

Zusammenfassung

Both process variations and defects in cells can lead to additional small delays within specifications, while the latter must be identified because they may degrade soon into critical faults for circuits and result in threat to reliability. Therefore, discriminating small delays due to defects from those due to variations has drawn increasingly attention in the test community over the recent years. One promising research direction is to formulate the task into binary classification by using delays under a few supply voltages as the only variables for datadriven algorithms. However, many approaches often assume the availability of delay information from both defective and nondefective cells or combinational circuits. This assumption implies a large time consumption for simulation, and considerable costs for manufactured defective devices. To address the issues above, this paper proposes to use unsupervised deep learning technique to train an recognizer on non-defective data only but still can identify defects during inference. Specifically, we have proposed weighted autoencoder with a novel data augmentation technique to solve this problem. Experiments show that our approach has comparable detection capability as supervised learning schemes, while our method does not require any defective data. Moreover, our approach is more robust to unbalanced datasets and to nontarget defects than other methods.

Zusammenfassung

Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.

Zusammenfassung

Small Delay Faults (SDFs) are an indicator of reliability threats even if they do not affect the behavior of a system at nominal speed. Various defects may evolve over time into a complete system failure, and defects have to be distinguished from delays due to process variations which also change the circuit timing but are benign. Based on Monte-Carlo ectrical simulation at cell level, in this work it is shown that a few measurements at different operating points of voltage and frequency are sufficient to identify a defect cell even if its behavior is completely within the specification range. The developed classifier is based on statistical learning and can be annotated to each element of a cell library to support manufacturing test, diagnosis and optimizing the burn-in process or yield.