Contact
+49 711 685 88391
+49 711 685 88288
Email
Pfaffenwaldring 47
D-70569 Stuttgart
Deutschland
Room: 2.170
Education
Academic Studies
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07.1990 |
Habilitation in Computer Science, University of Karlsruhe |
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12.1986 |
Ph.D. (Dr.rer.nat.) degree at the Faculty of Computer Science at the University of Karlsruhe (“with distinction“) |
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10.1981 |
Graduation in mathematics and philosophy at the University of Freiburg |
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1979-1981 |
Study of mathematics and philosophy at the University of Freiburg |
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1975-1979 |
Study of mathematics and philosophy at the University of Constance |
Professional Career
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since 10.2019 |
Leading the Research Group Computer Architecture at the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart |
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10.2017 - 09.2019 |
Director of the chair “Computer Architecture“ of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart |
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09.2002 - 09.2017 |
Head of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart |
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10.2010 - 09.2013 |
Vice Dean of Faculty 5 “Computer Science, Electrical Engineering and Information Technology” |
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10.1996 - 09.2019 |
Full professor (C4) of “Computer Science“ at the University of Stuttgart, Director of the department “Computer Architecture“ |
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12.1991 - 09.1996 |
Full professor (C4) of “Computer Engineering“ at the University - GHS Siegen, Director of the section “Processor Structures“ |
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01.1991 |
Appointment to Assistant Professor (C2) at the University of Karlsruhe |
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10.1990 - 03.1991 |
Full professor (C4) at the University of Duisburg in Computer Science (temporary) |
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09.1982 - 01.1991 |
Academic assistant with the University of Karlsruhe |
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1982 |
Freelancer with the Fraunhofer Institute for Industrial Engineering IAO, Stuttgart. |
International long-term activities
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04.2010 - 05.2010 |
Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France |
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04.2005 - 08.2005 |
Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France |
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01.2000 - 03.2000 |
Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France |
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08.1999 - 10.1999 |
LogicVision Inc., San Jose, CA, USA |
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01.1996 - 02.1996 |
Mentor Graphics Corporation, Portland, OR, USA |
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08.1995 - 03.1996 |
Visiting Professor at the “Center of Reliable Computing“, Stanford University, Stanford, CA, USA |
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03.1988 |
Call to the McGill University, Montreal, Canada, as a Visiting Assistant Professor |
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2020 |
IEEE Life Fellow for contributions to very-large-scale-integration circuit testing and fault tolerance |
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2020 |
Prof. Dr. Wunderlich (i.R.) was honoured with the "ETS Distinguished Service Award" within the 2020 IEEE European Test Symposium. |
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2015 |
IEEE Computer Society, Test Technology Technical Council: Distinguished Service Award for many years of dedicated distinguishing service in creating, organizing, growing and steering ETS |
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2014 |
Guest Professor at Hefei University of Technology, Hefei, China |
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2009 |
IEEE Fellow for contributions to very-large-scale-integration circuit testing and fault tolerance |
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2006 |
IEEE Computer Society Golden Core Member |
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2005 |
IEEE Computer Society Meritorious Service Award |
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1998 - 2008 |
IEEE Certificates of Appreciation |
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2001 |
Call to the TU Vienna for a professorship of Embedded Computing Systems |
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2000 |
Landeslehrpreis 1999 of the federal state Baden-Württemberg |
Best Paper Awards
- Lylina, N., Atteya, A. and Wunderlich, H.-J.
“A Hybrid Protection Scheme for Reconfigurable Scan Networks”
Best paper award IEEE VLSI Test Symposium (VTS’21), Virtual, 26-28 April 2021. - Schöll, A., Braun, C. and Wunderlich, H.-J.
"Applying Efficient Fault Tolerance to Enable the Preconditioned Conjugate Gradient Solver on Approximate Computing Hardware"
Best paper award IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'16), University of Connecticut, USA, 19-20 September 2016 - Asada, K., Wen, X., Holst, S., Miyase, K., Kajihara, S., Kochte, M.A., Schneider, E., Wunderlich, H.-J. and Qian, J.
"Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch"
Best paper award 24th IEEE Asian Test Symposium (ATS'15), Mumbai, India, 22-25 November 2015 - Baranowski, R., Kochte, M. A. and Wunderlich, H.-J.
"Access Port Protection for Reconfigurable Scan Networks"
Best paper award Journal of Electronic Testing: Theory and Applications (JETTA: best paper of the year 2014), Vol. 30(6), 5 December 2014, pp. 711-723 - Sauer, M., Polian, I., Imhof, M.E., Mumtaz, A., Schneider, E., Czutro, A., Wunderlich, H.-J. and Becker, B.:
"Variation-Aware Deterministic ATPG",
Best paper award 19th IEEE European Test Symposium (ETS), Paderborn, Germany, May 26-30, 2014 - Elm, M. and Wunderlich, H.-J.:
"XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad",
Best paper award VDE Tagung "Zuverlässigkeit und Entwurf" (ZuE), Stuttgart, Germany, September 21-23, 2009. - Kochte, M.A., Zoellin, C.G., Imhof, M.E. and Wunderlich, H.-J.:
"Test Set Stripping Limiting the Maximum Number of Specified Bits,"
Best paper award 4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA'08), Hong Kong, January 23-25, 2008. - Holst, S. and Wunderlich, H.-J.:
"Adaptive Debug and Diagnosis without Fault Dictionaries,"
Best paper award 12th IEEE European Test Symposium (ETS), Freiburg, Germany, May 21-24, 2007. - Öhler, P., Hellebrand, S. and Wunderlich, H.-J.:
"Analyzing Test and Repair Times for 2D Integrated Memory Built-In Test and Repair,"
Best paper award 10th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS), Krakow, Poland, April 11-13, 2007
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2019 |
Eric Schneider: |
“Multi-Level Simulation of Nano-Electronic Digital Circuits on GPUs” |
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2018 |
Alexander Schöll: |
“Efficient Fault Tolerance for Selected Scientific Computing Algorithms on Heterogeneous and Approximate Computer Architectures” |
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2017 |
Chang Liu: |
“Improvement of Hardware Reliability with Aging Monitors” |
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2017 |
Laura Rodríguez Gómez: |
“Machine Learning Support for Logic Diagnosis” |
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2016 |
Marcus Wagner: |
“Efficient Algorithms for Fundamental Statistical Timing Analysis Problems |
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2015 |
Michael Imhof: |
“Fault Tolerance Infrastructure and its Reuse for Offline Testing” |
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2015 |
Atefe Dalirsani: |
“Self-Diagnosis in Network-on-Chips” |
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2015 |
Claus Braun: |
“Algorithm-Based Fault Tolerance for Matrix Operations on Graphics Processing |
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2014 |
Michael Kochte: |
“Boolean Reasoning for Digital Circuits in Presence of Unknown Values” |
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2014 |
Alejandro Cook: |
“In-Field Structural Methods for End-to-End Automotive Digital Diagnosis” |
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2014 |
Nadereh Hatami: |
“Multi-level Analysis of Non-Functional Properties” |
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2014 |
Christian Zöllin: |
“Test Planning for Low-Power Built-In Self-Test” |
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2014 |
Rafal Baranowski: |
“Reconfigurable scan networks : formal verification, access optimization, |
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2012 |
Stefan Holst: |
“Efficient Location–Based Logic Diagnosis of Digital Circuits” |
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2011 |
Melanie Elm: |
“Embedded Hardware Structures for Efficient Volume and In-Field Diagnosis |
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2010 |
Abdul-Wahid Hakmi: |
“Efficient Programmable Deterministic Self-Test” |
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2009 |
Jun Zhou: |
“Software-Based Self-Test under Memory, Time, and Power Constraints” |
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2006 |
Valentin Gherman: |
“Scalable Deterministic Logic Built-In Self-Test” |
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2003 |
Huaguo Liang: |
“A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST)“ |
|
2002 |
Rainer Dorsch: |
“Testverfahren für digitale eingebettete Ein-Chip-Systeme“ |
|
1996 |
Olaf Stern: |
“Effiziente Erfassung von realistischen Fehlern in hochintegrierten Schaltungen“ |
Organization (excerpt)
- IEEE European Test Symposium (ETS)
2008 - 2014 chair of the steering committee
since 2015 member of the steering committee
Program Chair: 1996 Montpellier (FRA), 1997 Cagliari (ITA), 2001 Stockholm (SWE)
General Chair: 1999 Konstanz (GER)
Vice General Chair: 1998 Sitges (ESP)
Vice Program Chair: 2006 Southampton (GBR), 2007 Freiburg (GER)
Member of the organization committee: 1996 - 2009 - IEEE International Test Conference in Asia (ITC-Asia)
2017 Taipei City (TW) - IEEE VLSI Test Symposium (VTS)
Vice Program Chair: 1997, 2000, 2001
Vice General Chair: 2002 - 2008
Member of the organizing committee: 1995 - 2008 - IEEE International Conference on Computer Design (ICCD)
Topic Chair: 2011 (MA, USA), 2012 (CDN) - GI/ITG/GMM-Workshop: "Test and Reliability Of Circuits and Systems", "Test und Zuverlässigkeit" (TuZ)
General Chair: 1998 Herrenberg (GER)
Member of the organization committee: 1989 - 2012
Scientific Chair: 2015 - International Conference on Computer-Aided Design (ICCAD)
Topic Chair: 2005, 2006, 2007 San Jose (CA, USA) - GI/ITG/GMM-Fachtagung: "Reliability and Design", "Zuverlässigkeit und Entwurf" (ZuE)
Program Chair: 2007 Munich (GER), 2008 Ingolstadt (GER), 2009 Stuttgart (GER), 2010 Wildbad Kreuth (GER), 2011 Hamburg-Harburg (GER) - Design, Automation and Test Europe (DATE)
Topic Chair: 2003 Munich (GER), 2004 Paris (FRA), 2005 Munich (GER), 2008 Munich (GER), 2013 (FRA) - Asian Test Symposium (ATS)
Honorary Chair: 2018 Hefei, Anhui (CHN)
Member of Program Committees (excerpt)
- Asia and South Pacific Design Automation Conference (ASP-DAC)
1998, 2000 Yokohama (JPN) - Asian Test Symposium (ATS)
1994 Nara (JPN), 2001 Kyoto (JPN), 2002 Hagåtña (Guam/USA), 2005 Kalkutta (IND), 2007 Beijing (CHN), 2012 Niigata (JPN), 2013 Yilan (RC), 2014 Hangzhou (CHN), 2015 Mumbai (IND), 2016 Hiroshima (JPN), 2017 Taipei (RC), 2022 Taichung (RC) - Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS)
1998 (POL), 2000 (SVK), 2001 (HUN), 2002 (CZE), 2003 (POL), 2004 (SVK), 2005 (HUN), 2006 (CZE), 2007 (POL), 2009 (CZ), 2010 (AUT), 2011 (GER), 2012 (EST), 2013 (CZ), 2014 (PL), 2015 (SRB), 2016 (SK), 2017 (GER), 2018 (HU), 2019 (RO) - Design & Test in Europe (DATE)
1998 Paris (FRA), 1999 Munich (GER), 2000 Paris (FRA), 2001 Munich (GER), 2002 Paris (FRA), 2003 Munich (GER), 2004 Paris (FRA), 2005 Munich (GER), 2006 Munich (GER), 2007 Nizza (FRA), 2012 (GER), 2014 (GER), 2015 (FRA), 2016 (GER), 2018 (GER) - East-West Design & Test Workshop (EWDTW)
2004 Yalta (UKR), 2005 Odessa (UKR) - European Conference on Design Automation / European Test Conference (EDAC/ETC)
1991, 1992, 1994, 1995, 1996 - GI/ITG/GMM-Workshop Test and Reliability of Circuits and Systems
1989 - 2010 - IEEE International Conference on Computer Design (ICCD)
yearly 1998 – 2003, 2005 - IEEE International On-Line Testing Symposium (IOLTS)
yearly 1995 – 2015 - IEEE International Test Synthesis Workshop
yearly 1994 – 2003 - IEEE International Test Synthesis Conference (ITC)
2014, 2022 - IEEE International Workshop on Electronic Design, Test & Applications (DELTA)
2006 Kuala Lumpur (MAS), 2008 Hong Kong (CHN), 2010 Ho-Chi-Minh City (VN) - IEEE VLSI Design
1991 New Delhi (IND), 1992 Bangalore (IND), 1993 Bombay (IND), 1994 Kalkutta (IND), 1996 Bangalore (IND), 1998 New Delhi (IND) - Latin American Test Workshop (LATW)
yearly 2000 – 2004, 2010, 2011, 2012, 2013, 2014 - Latin American Test Symposium (LATS)
2015 Puerto Vallarta (MEX), 2016 Foz do Iguaçu (BRA) - Symposium on Integrated Circuits and System Design (SBCCI)
2010 Sao Paulo (BRA), 2011, 2012 - Symposium on Fault-Tolerant Computing (FTCS)
1990 Newcastle (GBR), 1991 Montreal (CAN), 1992 Boston, 1993 Toulouse (FRA), 1996 Sendai (JPN). - 4th Workshop on Dependable and Secure Nanocomputing, WDSN
2010 Chicago (USA)
Invited Talks (excerpt)
- Keynote at Workshop on RTL and High Level Testing (WRTLT) 2018, “Security and Privacy Aspects of Reconfigurable Scan Networks”, Hefei, Anhui, China, October 2018
- Keynote at: IEEE Asian Test Symposium (ATS), “The Revival of BIST: From Self-Test to Self-Healing”, Taipei, Taiwan, November 2017
- Keynote at: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), “50 years of self-test: From random patterns to in-field automotive testing and health monitoring”, Dresden, Germany, April 2017
- Invited talk: International Symposium on Dependable Integrated Systems (DISC): “Options and Organization of Faster-than-at-Speed-Test”, Fukuoka, Japan, November 2016
- Special Plenary in Honor of Prof. Edward J. McCluskey: IEEE Asian Test Symposium (ATS): “Tribute to Prof. Edward J. McCluskey: Learning how to teach”, Hiroshima, Japan, November 2016
- Keynote at: IEEE East-West Design & Test Symposium(EWDTS), "Multi-Level High-Throughput Simulation for Design & Test Validation", Yerevan, Armenia, Oktober 2016
- Invited talk: "R3S: Reliable Runtime Reconfigurable Systems", National Sun-Yat-sen University, Kaohsiung, Taiwan, September 2015
- Invited talk: "Combining Structural and Functional Test Approaches Across System Levels", National Cheng Kung University, Tainan, Taiwan, September 2015
- Invited talk: "R3S: Reliable Runtime Reconfigurable Systems", Kyushu Institute of Technology, Fukuoka, Japan, September 2015
- Keynote at: IEEE International On-Line Testing Symposium (IOLTS), „Fault Tolerance meets Diagnosis”, Elia, Halkidiki, Greece, 2015
- Keynote at: IEEE European Test Symposium (ETS), „Testing Visions”, Cluj-Napoca, Romania, 2015
- Invited talk: IEEE International On-Line Testing Symposium (IOLTS), "Efficacy And Efficiency of Algorithm Based Fault Tolerance on GPUs", Chania, Crete, Greece, 2013
- Invited talk: IEEE / IFIP International Conference on Dependable Systems and Networks Systems (DSN), (Workshop on Dependable and Secure Nanocomputing), “Massive Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic Circuits: Statistical Test Methods”, Chicago, USA, 2010
- Invited talk: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), “Software -Based Hardware Fault Tolerance for Many-Core Architectures”, Chicago, USA, 2009
- Invited talk: Forum on specification & Design Languages (FDL), ECSI Conference, “Model-Based Hardware-Testing”, Valbonne, France, 2009
- Invited talk: IEEE / TTTC Latin American Test Workshop (LATW), “Embedded Diagnosis - a Key to Reliable Systems”, Buzios, Brasil, 2009
- Invited talk: IEEE International Test Conference (ITC), "Testing the Infrastructure", Santa Clara, USA, 2008
- Invited talk: Colloque Groupement de Recherche (CNRS), (GDR-SoC-SiP Workshop), “Challenges in Test and Diagnosis or: Complexity is more than Size”, 2008
- Invited talk: MIDEM Society, International Conference on Microelectronics, Devices and Materials (MIDEM),“Debug and diagnosis mastering the life cycle of nano scale systems on chip”, , Bled, Slovenia, 2007
- Invited talk: IEEE East-West Design & Test Symposium (EWDTS), "Challenges in the Diagnosis of Nanoelectronic Systems", Yerevan, Armenia, 2007
- Invited talk: IEEE International Workshop on Electronic Design, Test & Applications (DELTA), “Some Common Aspects of Design Validation,Debug and Diagnosis” Kuala Lumpur, Malaysia, 2006
- Invited talk: IEEE European Test Symposium (ETS), “From Embedded Test to Embedded Diagnosis”, Tallinn, Estonia, 2005
- Invited talk: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), “From BIST to BISD”, Stará Lesná, Slovakia, 2004
- Invited talk: IEEE European Test Symposium (ETS), “Trends in BIST and Diagnosis”, Ajaccio, Corsica, France, 2004
Activities in Scientific Community
- Chair of the Technical Board “Test Methods and Reliability of Circuits and Systems” of GI, GMM and ITG (Fachgruppensprecher der FG 6.5) (2008 - 2012)
- Member of the Executive Committee “Computer-aided Design of Circuits and Systems” (Rechnergestützter Schaltungs- und Systementwurf, RSS), GI (Gesellschaft für Informatik), GMM (VDE / VDI Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik) and ITG (Informationstechnische Gesellschaft im VDE)
- Member of the Editorial Board of the “Journal of Electronic Testing: Theory and Application” (JETTA), Springer
- Member of the Editorial Board of the ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM (Association of Computing Machinery)(until 2009)
- Member of the Editorial Board of the “Journal of Low Power Electronics” (JOLPE)
- Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS), ACM (Association of Computing Machinery)(until 2011)
Current Projects
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since 09.2020 |
DFG-Project ACCROSS: „Approximate Computing aCROss the System Stack“ |
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since 02.2017 |
DFG-Project FAST: Reliability Assessment using „Faster-than-at-Speed Test“ |
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since 08.2014 |
DFG project ACCESS: „Robuster ACCESS: Verifikation, Test und Diagnose konfigurierbarer Scan-Netzwerke“ (WU 245/17-1, WU 245/17-2) |
Completed Projects
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02.2016 - 05.2019 |
SHIVA: „Sichere Hardware in der Informationsverarbeitung“, funded by Baden-Württemberg Stiftung |
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10.2014 - 12.2018 |
DFG project PARSIVAL: „Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation“ (WU 245/16-1) |
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01.2015 - 12.2016 |
PPP Japan, DAAD-JSPS Joint Research Program: „HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing“, carried out in cooperation with Kyushu Institute of Technology, Fukuoka, Japan |
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07.2012 - 06.2015 |
DFG project RM-BIST: „Reliability Monitoring and Managing Built-In-Self Test“ (WU 245/13-1) |
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08.2011 - 12.2015 |
DFG project ROCK: „Robuste Network-On-Chip Kommunikation durch hierarchische Online-Diagnose und –Rekonfiguration“ (WU 245/12-1) |
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03.2011 - 12.2014 |
DFG Project: OASIS: „Online-Ausfallvorhersage mikroelektronischer Schaltungen mittels Alterungssignaturen“ (WU 245/11-1) |
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10.2010 - 06.2017 |
DFG Project: OTERA: “Online Test Strategies for Reliable Reconfigurable Architectures” (WU 245/10-1) |
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10.2010 - 09.2013 |
DFG Project: INTESYS: “Model-Based Test Generation for the Efficient Test of Hardware/Software Systems” (WU 245/9-1) |
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07.2010 - 07.2013 |
BMBF Project: DIANA: “End-to-End Diagnostic Capabilities for Automotive Electronics Systems” |
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06.2009 - 05.2013 |
“Diagnose von Halbleiterfehlern” with AUDI AG, Germany |
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06.2008 - 10.2017 |
Principal Investigator in the Cluster of Excellence for Simulation Technology (SRC SimTech): Mapping Simulation Algorithms to NoC MPSoC Computers |
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01.2006 - 06.2013 |
DFG Project: "RealTest - Test and Reliability of Nanoelectronic System" (WU 245/5-1, WU245/5-2) |
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01.2007 - 12.2009 |
DAAD/Vigoni project: “Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics” carried out in cooperation with the Politecnico di Torino, Italy |
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10.2005 - 12.2009 |
CAS project: "On-Demand Power Reduction during Chip Test" carried out in cooperation with IBM Deutschland Entwicklung GmbH |
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05.2006 - 04.2009 |
BMBF project: "New Methods for the massiv-parallel Test in High-volume, Yield Learning and best Testing Quality" (Maya) carried out in cooperation with NXP and Infineon Technologies |
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06.2006 - 05.2009 |
DFG project: “DIADEM - Embedded Diagnosis and Debug Methods for VLSI Systems in Nanometer Technoloy” (WU 245/4-1) |
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09.2002 - 12.2009 |
DFG research group: “Reliability of Mechatronic Systems” (WU 245/3-1, 3-2, 3-3) |
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03.2002 - 02.2005 |
BMBF Project in cooperation with the companies ATMEL, Infineon and Philips “Application specific test method for highly complex systems of communication and automation (AZTEKE)” |
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09.2000 - 05.2005 |
Project with Philips Eindhoven, Netherlands “Deterministic BIST” |
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12.2002 - 03.2003 |
Project with Gaisler Research, Sweden “Memory Management Unit for Leon SoC, Linux port” |
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09.2001 - 07.2004 |
ESPRIT Project with the Universities of Montpellier, UPC Barcelona, Turin and Ljubljana “EuNICE: European Network for Initial and Continuing Education in VLSI/SOC Testing using remote ATE facilities” |
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03.2003 - 10.2005 |
DFG project “Power Conscious Online Test” (Wu 245/2-2) within the framework of the DFG main focus programme VIVA |
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01.2000 - 12.2002 |
Vigoni Program (DAAD) „ASTRO – Advanced Functional Built-In-Self-Test Architectures for Systems-on-a-Chip” with Prof. P. Prinetto, Torino |
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05.1999 - 12.2002 |
DFG Projekt: Leistungs- und Energiebeschränkung im Selbsttest (Wu 245/2-1) im Rahmen des DFG-Schwerpunktprogramms Grundlagen und Verfahren verlustarmer Informationsverarbeitung (VIVA) |
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01.1999 - 03.2003 |
BMBF project “Functional Built-In Self-Test of Digital Systems” in cooperation with Prof. R. Ubar, Tallinn, and Prof. G. Elst, Dresden |
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04.1996 - 12.1998 |
BMBF project (X.023.2) “Transparent Self-test of Storage Components” |
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04.1996 - 12.1998 |
NATO project „Synthesis of Fault-Tolerant Systems Based on Behavioral Descriptions“ (SA.5-2-05(CRG.96034)) in cooperation with Prof. Alex Orailoglu, UCSD, USA |
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10.1995 - 03.2002 |
DFG project “Test and Synthesis of Fast Digital Systems" (Wu 245/1-1,2,3,4) at the University of Siegen, later University of Stuttgart |
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07.1992 - 10.1995 |
ESPRIT project "High-Quality VLSI Systems Testing ARCHIMEDES" (ARCHIMEDES BRA 7107) at the University of Siegen |
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04.1990 - 11.1991 |
DFG project "Test-friendly Functional Representations" at the University of Karlsruhe (with Prof. Dr. D. Schmid) |
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04.1989 - 11.1991 |
BMFT project „ARIADNE/Testcluster“ at the University of Karlsruhe (with Prof. Dr. D. Schmid) |
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07.1986 - 06.1989 |
Research project: “Economical Test Strategies for the Automatic Design of Integrated Circuits“. Funded by the Federal Ministry of Research and Technology (with Prof. Dr. D. Schmid) |