ACCESS

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

since 08.2014, DFG-Project: WU 245/17-1

Project Description

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Examples of instruments for efficient localization of silicon defects and design bugs include trace buffers, performance monitors, event counters, or scan chains. Test instrumentation includes test controllers, test wrappers, scan chains and structures for pattern decompression and compaction. Such instruments are used both in manufacturing test and for in-field test. Maintenance instrumentation is mainly used in regular system operation for monitoring, error detection, and reliability management. It includes, for instance, error monitors, memory repair controllers, and structures for system reprogramming and reconfiguration. Instruments for manufacturability, e.g. process monitors, facilitate the monitoring of chip performance and reliability. Due to the increasing complexity, however, the embedded infrastructure and access mechanisms themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE Std 1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals. This comprises:

  • Unified RSN Modeling
  • Verification of Model Consistency
  • Formal Verification to guarantee operability, safety, and security
  • Efficient Test Generation and Fault Simulation
  • Post-Manufacture and In-Field Test
  • Diagnosis of Scan Infrastructure Faults
  • Robust Access to Faulty Scan Infrastructure

This work is supported by the German Research Foundation (DFG) under grant WU 245/17-1 (2014-2017).

Publications

  1. 2019

    1. SWIFT: Switch Level Fault Simulation on GPUs. Eric Schneider and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, 1 (2019), pp. 122--135. DOI: https://doi.org/10.1109/TCAD.2018.2802871
  2. 2018

    1. Multi-Level Timing Simulation on GPUs. Eric Schneider; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC’18), Jeju Island, Korea, 2018, pp. 470--475. DOI: https://doi.org/10.1109/ASPDAC.2018.8297368
  3. 2017

    1. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (2017), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    2. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
  4. 2016

    1. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.
    2. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    3. Formal Verification of Secure Reconfigurable Scan Network Infrastructure. Michael A. Kochte; Rafal Baranowski; Matthias Sauer; Bernd Becker and Hans-Joachim Wunderlich. In Proceedings of the 21st IEEE European Test Symposium (ETS’16), Amsterdam, The Netherlands, 2016, pp. 1–6. DOI: https://doi.org/10.1109/ETS.2016.7519290
    4. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    5. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
    6. Dependable On-Chip Infrastructure for Dependable MPSOCs. Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 17th IEEE Latin American Test Symposium (LATS’16), Foz do Iguaçu, Brazil, 2016, pp. 183–188. DOI: https://doi.org/10.1109/LATW.2016.7483366
  5. 2015

    1. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    2. Fine-Grained Access Management in Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34, 6 (2015), pp. 937--946. DOI: https://doi.org/10.1109/TCAD.2015.2391266
    3. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863
  6. 2014

    1. Access Port Protection for Reconfigurable Scan Networks. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. Journal of Electronic Testing: Theory and Applications (JETTA) 30, 6 (2014), pp. 711--723. DOI: https://doi.org/10.1007/s10836-014-5484-2
    2. High Quality System Level Test and Diagnosis. Artur Jutman; Matteo Sonza Reorda and Hans-Joachim Wunderlich. In Proceedings of the 23rd IEEE Asian Test Symposium (ATS’14), Hangzhou, China, 2014, pp. 298--305. DOI: https://doi.org/10.1109/ATS.2014.62
Dieses Bild zeigt Wunderlich
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich

Chair of Computer Architecture

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