ACCESS

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

since 08.2014, DFG-Project: WU 245/17-1, WU 245/17-2

 

Project Description (Phase 2)

RSNs were initially brought up to manage the extensive amount of instrumentation in modern systems-on-chip to facilitate cost-efficient bring-up and debug, test, diagnosis and maintenance. Recently, the reuse of RSNs at system runtime for online fault classification and fault management moved into the center of research activities. Reasons are not only the increased complexity and dependability requirements in new technologies, but also the emerging application paradigms of self-aware and autonomous systems. Especially in safety-critical applications, online test, system monitoring and fault tolerance at low cost become mandatory. For example, the standard ISO 26262 specifies critical faults to be detected within certain test intervals at runtime and allows only a maximum fault reaction time until the system has to be transferred into a safe state. The periodic test is usually structure oriented and targets stuck-at, transition and delay faults.

It is common practice that the required tasks for initializing the periodic testing, for fault detection and for fault reaction are executed by the system functionality transparent in the background. Disadvantages of this approach are manifold: The periodic test and test evaluation constitute some significant additional workload, reduce performance, consume a large amount of additional power, and may take too much time for avoiding dangerous situations. Guaranteeing deadlines and verifying fault tolerance is extremely difficult as the properties have to be proven in the presence of faults.An alternative is the use of the non-functional infrastructure for concurrent fault detection and fault management, and first approaches to employ RSNs in in-system runtime tests have already been proposed. These first attempts still require a dedicated regular structure of RSNs and its permanent background operation which should be avoided in practice.

The results of the first phase of ACCESS provide an excellent basis for further research on the runtime use of RSNs. Since RSNs are integrated into the chip any way, the required cost of the modifications for runtime use are affordable even for a mass market like automotive. The goal of the second phase of ACCESS is a technique for a robust online use of RSNs to support safety, fault tolerance and reliability management.

This comprises:

  • In-system run-time test using RSNs
  • System wide collection of diagnosis information
  • Online diagnosis of RSNs
  • Investigation of robust and fault-tolerant RSNs

This work is supported by the German Research Foundation (DFG) under grant WU 245/17-2 (2019-2021).

 

Project Description (Phase 1)

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Examples of instruments for efficient localization of silicon defects and design bugs include trace buffers, performance monitors, event counters, or scan chains. Test instrumentation includes test controllers, test wrappers, scan chains and structures for pattern decompression and compaction. Such instruments are used both in manufacturing test and for in-field test. Maintenance instrumentation is mainly used in regular system operation for monitoring, error detection, and reliability management. It includes, for instance, error monitors, memory repair controllers, and structures for system reprogramming and reconfiguration. Instruments for manufacturability, e.g. process monitors, facilitate the monitoring of chip performance and reliability. Due to the increasing complexity, however, the embedded infrastructure and access mechanisms themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE Std 1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals. This comprises:

  • Unified RSN Modeling
  • Verification of Model Consistency
  • Formal Verification to guarantee operability, safety, and security
  • Efficient Test Generation and Fault Simulation
  • Post-Manufacture and In-Field Test
  • Diagnosis of Scan Infrastructure Faults
  • Robust Access to Faulty Scan Infrastructure

This work is supported by the German Research Foundation (DFG) under grant WU 245/17-1 (2014-2017).

Preliminary work in this field includes:

  • Verifikation Rekonfigurierbarer Scan-Netze
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proc. 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014), Böblingen, Germany, Mar 10-12
  • Securing Access to Reconfigurable Scan Networks
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, Nov 18--21
  • Scan Pattern Retargeting and Merging with Reduced Access Time
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of IEEE European Test Symposium (ETS'13), Avignon, France, May 27-30, pp. 39-45
  • Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of the IEEE International Test Conference (ITC'12), Anaheim, California, USA, November 6-8, pp. 1-9

The First International Test Standards Application Workshop (TESTA) discussed applications of reconfigurable scan networks and provided an open framework for exchanging ideas especially on the best practices around recently released test standards IEEE 1149.1-2013 and IEEE 1687-2014, as well as IEEE 1500-2005. It took place on May 26-27, 2016, co-located with the IEEE European Test Symposium in Amsterdam, The Netherlands. The ITI took part in the workshop organization.

Publications

  1. 2020

    1. Synthesis of Fault-Tolerant Reconfigurable Scan Networks. Sebastian Brandhofer; Michael A. Kochte and Hans-Joachim Wunderlich. In to appear in Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE’20), Grenoble, France, 2020, pp. 1--6.
  2. 2017

    1. Self-Test and Diagnosis for Self-Aware Systems. Michael A. Kochte and Hans-Joachim Wunderlich. IEEE Design & Test 35, 5 (2017), pp. 7--18. DOI: https://doi.org/10.1109/MDAT.2017.2762903
    2. Structure-oriented Test of Reconfigurable Scan Networks. Dominik Ull; Michael A. Kochte and Hans-Joachim Wunderlich. In Proceedings of the 26th IEEE Asian Test Symposium (ATS’17), Taipei, Taiwan, 2017. DOI: https://doi.org/10.1109/ATS.2017.34
  3. 2016

    1. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.
    2. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns. Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. In Proceedings of the 21st Asia and South Pacific  Design Automation Conference (ASP-DAC’16), Macao SAR, China, 2016, pp. 749–754. DOI: https://doi.org/10.1109/ASPDAC.2016.7428101
    3. Test Strategies for Reconfigurable Scan Networks. Michael A. Kochte; Rafal Baranowski; Marcel Schaal and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 113--118. DOI: https://doi.org/10.1109/ATS.2016.35
    4. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In Proceedings of the 25th IEEE Asian Test Symposium (ATS’16), Hiroshima, Japan, 2016, pp. 215--220. DOI: https://doi.org/10.1109/ATS.2016.56
  4. 2015

    1. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values. Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer; Hans-Joachim Wunderlich and Bernd Becker. IEEE Transactions on Computer-Aided Design of Integrated  Circuits and Systems (TCAD) 34, 12 (2015), pp. 2025--2038. DOI: https://doi.org/10.1109/TCAD.2015.2440315
    2. Reconfigurable Scan Networks: Modeling, Verification, and  Optimal Pattern Generation. Rafal Baranowski; Michael A. Kochte and Hans-Joachim Wunderlich. ACM Transactions on Design Automation of Electronic Systems (TODAES) 20, 2 (2015), pp. 30:1--30:27. DOI: https://doi.org/10.1145/2699863

Workshop Contributions

  1. 2016

    1. Autonomous Testing for 3D-ICs with IEEE Std. 1687. Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee and Hans-Joachim Wunderlich. In First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 2016.

Contact

Hans-Joachim Wunderlich (i.R.)
Prof. Dr. rer. nat. habil.

Hans-Joachim Wunderlich (i.R.)

Heading the Research Group Computer Architecture

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