| Time: | January 13, 2020 |
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11:30 - 12:30, FZI 1.021,
Institute of Computer Architecture and Computer Engineering
Abstract:
Three-dimensional (3D) integrated circuit technology becomes more and more important, as it offers an opportunity to integrate a large number of cores and memory in close proximity to each other. 3D System-on-Chips (SoCs) are implemented by means of stacking dies and connecting them with Through-Silicon-Vias (TSVs). The 3D Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication problems in these stacked many-core systems. One downside of technology scaling is to increase the probability of fault occurrence in components of 3D NoCs. However, such a 3D NoC can still operate at the cost of performance degradation. It is challenging to analyze the performance and reliability of degradable 3D NoCs. In this paper, we propose a framework to compute the transient performance of 3D NoCs under consideration of faults in links and TSVs. Moreover, we use a vertically-partially-connected 3D Mesh to demonstrate our methodology. Transient performances of the 3D fault-tolerant negative-first (3D-FTNF) and XYZ routing algorithms are evaluated.
[Picture: ITI]