With the development of integration technology, microprocessor industries moved from single-core to multi-core and many-core architectures. As the number of components on a chip increases, Networks-on-Chip (NoC), a highly scalable and bandwidth-efficient interconnection substrate, has been proposed for further researches into network characteristics. Although technology scaling leads to faster processing speed, the risk of suffering from faults also increases. Normally, redundancy is the main approach for increasing fault tolerance, and the evolution of a NoC can be characterized as a stochastic process. In this thesis, a hexagonal NoC is modeled as a continuous-time Markov chain (CTMC), and its performability under consideration of permanent faults will be evaluated using the Markov reward model (MRM).