Mittwoch 31. Juli 2019
14:00 - 15:00 M. Sc. Ahmed Atteya
"Multi-level Simulation of Reconfigurable Scan Networks"
Simulation of Reconfigurable Scan Networks is important for many applications such as test, diagnosis, validation and verification.
However accurate simulation of RSNs suffers from scalability problems, due to the highly sequential behaviour of these structures.
In this talk a Multi-level simulation environment of RSNs is presented, that aims to model RSNs at different abstractions levels to increase the simulation efficiency. Future developments to the simulation model for specific applications, like test and diagnosis, will be presented and discussed.
15:30 - 16:30 M. Sc. Natalia Lylina
"On Optimal Repair of Security Violations in Reconfigurable Scan Networks"
Modern computing systems integrate an increasing number of connected components, such as processor cores, memories and peripherals with the complex interconnections between them on the same chip. Those components can potentially come from different manufacturers and have different properties, such as trustworthiness and confidentiality levels. Since computing systems can be deployed in such areas as automotive industry, Industry 4.0 or medical appliances, it is extremely important to guarantee their safe operation. In order to obtain a desired reliability level a complex test infrastructure can be created. An efficient and flexible way to access test instruments is proposed by Reconfigurable Scan Networks (RSNs), standardized by IEEE Std. 1687. However, good observability and controllability of instruments, offered by test infrastructure can cause security issues, since a side-channel for attacker appears and potentially can be opened. In this talk I will discuss the possible ways to optimally resolve the security violations, caused by RSN integration. The main idea is that test infrastructure must not extend the allowed information flow. Structural dependencies between components of the targeted system as well as the explicit restrictions on data transfer in the initial design are analyzed and the initial RSN is being modified to correspond to the given security requirements.
Donnerstag 1. August 2019
08:15 - 9:15 Ph.D. candidate Chih-Hao Wang
"Concurrent Error Detection and Fault Detection to Small Delay Faults by Implication"
Implication-based concurrent error detection (CED) has been proven to have advantages for both online and offline applications. High probability of detecting errors as well as diagnosability improvement are achieved. However, neither the effectiveness of detecting erdiscuss these two topics to investigate the resilience of implication-based CED. rors due to small delay faults (SDFs) nor the test of SDF by implication-based CED have been investigated. In this talk, we will discuss these two topics to investigate the resilience of implication-based CED.
09:20 - 10:20 Dipl. Inf. Eric Schneider
"Parametric Delay Modeling in Gate Level Time Simulation"
Timing-accurate simulation poses a serious bottleneck in design and test validation of today's nano-electronic circuits due to high computational efforts.With systems running under different operating conditions, i.e., adaptive voltage and frequency scaling (AVFS) or ambient temperatures, traditional time simulation approaches based on static delays cannot be used anymore for meaningful design space exploration, since they lack the ability to consider parameter dependencies.
However, adding such dependencies into the delay models further increases the computational effort of time simulation to a point where the complexity cannot be handled without the use of efficient parallelization.
In this work, a massively parallel time simulation is presented that provides a compact multi-dimensional parametric delay modeling for design space exploration of AVFS-based systems. Analog simulation of standard cells is used as a preprocessing step to obtain gate delays under different operating points, which are then processed using statistical learning methods to derive delay kernels that compute the gate delays of each cell type during simulation. With the help of Graphics Processing Units and their computational power, the simulator is able to achieve highest simulation throughput with Billions of gate evaluations per second at full timing-accuracy consideration of parametric dependencies enabling large-scale design space exploration of AVFS-based systems for the first time.
Freitag 2. August 2019
09:00 - 10:00 M. Sc. Zahra Paria Najafi Haghi
"Variation aware marginal defects detection"
As devices can work properly in the beginning, weak structures must be identified by analyzing the non-functional circuit behavior with the help of appropriate observables. Besides power consumption, the circuit timing is one of the most important reliability indicators. In particular, small delay faults may indicate marginal hardware that can degrade further under stress and make a failure for a circuit when works in the field. However, these Small Delay Faults can be “hidden” at nominal test frequency. Therefore, conventional approaches for testing reach their limitations and new methods should be applied.
In this work, different defects in FinFET technology which cause extra delay to the circuit will be investigated and modeled. A Faulty FinFET cell will be tested under different circumstances which can effect the duration of the Delay Faults. These varying circumstances means giving different values to the operation point- here Voltage and Temperature- and investigating their effect on Small Delay Faults. On the other hand, varying operation point has different impact on cells with Process Variation and without SDF, which should pass the test. This different impact on the observables- here propagation delay- gives the opportunity to classify cells with SDFs and cells which are delayed due to the Process Variation.
10:30 - 11:30 Ph.D. candidate Tai Song
"Application of Adaptive Adjustment Classification Algorithm in Early Life Failure Test"
In manufacturing test Data Mining, researchers usually overlook the importance of distinguish on process variation defects and marginal defects. It can seriously affect the result of the Early Life Failure (ELF). Theoretically, we use a classifier to identify these two defects. The majority of classifier assumed that the distribution of the data is relatively balanced; but in fact, using a single or fixed classifier often leads to inaccurate predictions. The classifier needs to adjust changes according to defect characteristics or use different classifiers to achieve highest accuracy. This study will explain about classifier adaptive adjustment mechanism according to the defect feature. Adaptive adjustment method provides balancing mechanism for the dataset's distribution, so that the classification results will be enhanced in terms of classification performance. The adaptive adjustment methods produce the accuracy, macro-avg, weighted-avg score as high as 100%, 100 %, 100 % respectively. Hence, the adaptive adjustment methods can be a viable solution for imbalanced class on manufacturing test dataset.